[J-u-boot.git] / drivers / mmc / renesas-sdhi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018 Marek Vasut <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <fdtdec.h>
#include <mmc.h>
#include <dm.h>
#include <linux/compat.h>
#include <linux/dma-direction.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <power/regulator.h>
#include <asm/unaligned.h>

#include "tmio-common.h"

#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)

/* SCC registers */
#define RENESAS_SDHI_SCC_DTCNTL			0x800
#define   RENESAS_SDHI_SCC_DTCNTL_TAPEN		BIT(0)
#define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT	16
#define   RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK		0xff
#define RENESAS_SDHI_SCC_TAPSET			0x804
#define RENESAS_SDHI_SCC_DT2FF			0x808
#define RENESAS_SDHI_SCC_CKSEL			0x80c
#define   RENESAS_SDHI_SCC_CKSEL_DTSEL		BIT(0)
#define RENESAS_SDHI_SCC_RVSCNTL			0x810
#define   RENESAS_SDHI_SCC_RVSCNTL_RVSEN		BIT(0)
#define RENESAS_SDHI_SCC_RVSREQ			0x814
#define   RENESAS_SDHI_SCC_RVSREQ_RVSERR		BIT(2)
#define RENESAS_SDHI_SCC_SMPCMP			0x818
#define RENESAS_SDHI_SCC_TMPPORT2			0x81c

#define RENESAS_SDHI_MAX_TAP 3

static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
{
	u32 reg;

	/* Initialize SCC */
	tmio_sd_writel(priv, 0, TMIO_SD_INFO1);

	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	/* Set sampling clock selection range */
	tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
			   RENESAS_SDHI_SCC_DTCNTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
	reg |= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
	reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);

	tmio_sd_writel(priv, 0x300 /* scc_tappos */,
			   RENESAS_SDHI_SCC_DT2FF);

	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg |= TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	/* Read TAPNUM */
	return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
		RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
		RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
}

static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
{
	u32 reg;

	/* Reset SCC */
	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
	reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);

	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	reg |= TMIO_SD_CLKCTL_SCLKEN;
	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);

	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
}

static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
				       unsigned long tap)
{
	/* Set sampling clock position */
	tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
}

static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
{
	/* Get comparison of sampling data */
	return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
}

static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
				     unsigned int tap_num, unsigned int taps,
				     unsigned int smpcmp)
{
	unsigned long tap_cnt;  /* counter of tuning success */
	unsigned long tap_set;  /* tap position */
	unsigned long tap_start;/* start position of tuning success */
	unsigned long tap_end;  /* end position of tuning success */
	unsigned long ntap;     /* temporary counter of tuning success */
	unsigned long match_cnt;/* counter of matching data */
	unsigned long i;
	bool select = false;
	u32 reg;

	/* Clear SCC_RVSREQ */
	tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);

	/* Merge the results */
	for (i = 0; i < tap_num * 2; i++) {
		if (!(taps & BIT(i))) {
			taps &= ~BIT(i % tap_num);
			taps &= ~BIT((i % tap_num) + tap_num);
		}
		if (!(smpcmp & BIT(i))) {
			smpcmp &= ~BIT(i % tap_num);
			smpcmp &= ~BIT((i % tap_num) + tap_num);
		}
	}

	/*
	 * Find the longest consecutive run of successful probes.  If that
	 * is more than RENESAS_SDHI_MAX_TAP probes long then use the
	 * center index as the tap.
	 */
	tap_cnt = 0;
	ntap = 0;
	tap_start = 0;
	tap_end = 0;
	for (i = 0; i < tap_num * 2; i++) {
		if (taps & BIT(i))
			ntap++;
		else {
			if (ntap > tap_cnt) {
				tap_start = i - ntap;
				tap_end = i - 1;
				tap_cnt = ntap;
			}
			ntap = 0;
		}
	}

	if (ntap > tap_cnt) {
		tap_start = i - ntap;
		tap_end = i - 1;
		tap_cnt = ntap;
	}

	/*
	 * If all of the TAP is OK, the sampling clock position is selected by
	 * identifying the change point of data.
	 */
	if (tap_cnt == tap_num * 2) {
		match_cnt = 0;
		ntap = 0;
		tap_start = 0;
		tap_end = 0;
		for (i = 0; i < tap_num * 2; i++) {
			if (smpcmp & BIT(i))
				ntap++;
			else {
				if (ntap > match_cnt) {
					tap_start = i - ntap;
					tap_end = i - 1;
					match_cnt = ntap;
				}
				ntap = 0;
			}
		}
		if (ntap > match_cnt) {
			tap_start = i - ntap;
			tap_end = i - 1;
			match_cnt = ntap;
		}
		if (match_cnt)
			select = true;
	} else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
		select = true;

	if (select)
		tap_set = ((tap_start + tap_end) / 2) % tap_num;
	else
		return -EIO;

	/* Set SCC */
	tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);

	/* Enable auto re-tuning */
	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
	reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);

	return 0;
}

int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
{
	struct tmio_sd_priv *priv = dev_get_priv(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct mmc *mmc = upriv->mmc;
	unsigned int tap_num;
	unsigned int taps = 0, smpcmp = 0;
	int i, ret = 0;
	u32 caps;

	/* Only supported on Renesas RCar */
	if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
		return -EINVAL;

	/* clock tuning is not needed for upto 52MHz */
	if (!((mmc->selected_mode == MMC_HS_200) ||
	      (mmc->selected_mode == UHS_SDR104) ||
	      (mmc->selected_mode == UHS_SDR50)))
		return 0;

	tap_num = renesas_sdhi_init_tuning(priv);
	if (!tap_num)
		/* Tuning is not supported */
		goto out;

	if (tap_num * 2 >= sizeof(taps) * 8) {
		dev_err(dev,
			"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
		goto out;
	}

	/* Issue CMD19 twice for each tap */
	for (i = 0; i < 2 * tap_num; i++) {
		renesas_sdhi_prepare_tuning(priv, i % tap_num);

		/* Force PIO for the tuning */
		caps = priv->caps;
		priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;

		ret = mmc_send_tuning(mmc, opcode, NULL);

		priv->caps = caps;

		if (ret == 0)
			taps |= BIT(i);

		ret = renesas_sdhi_compare_scc_data(priv);
		if (ret == 0)
			smpcmp |= BIT(i);

		mdelay(1);
	}

	ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);

out:
	if (ret < 0) {
		dev_warn(dev, "Tuning procedure failed\n");
		renesas_sdhi_reset_tuning(priv);
	}

	return ret;
}
#endif

static int renesas_sdhi_set_ios(struct udevice *dev)
{
	int ret = tmio_sd_set_ios(dev);

	mdelay(10);

#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	struct tmio_sd_priv *priv = dev_get_priv(dev);

	renesas_sdhi_reset_tuning(priv);
#endif

	return ret;
}

static const struct dm_mmc_ops renesas_sdhi_ops = {
	.send_cmd = tmio_sd_send_cmd,
	.set_ios = renesas_sdhi_set_ios,
	.get_cd = tmio_sd_get_cd,
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	.execute_tuning = renesas_sdhi_execute_tuning,
#endif
};

#define RENESAS_GEN2_QUIRKS	TMIO_SD_CAP_RCAR_GEN2
#define RENESAS_GEN3_QUIRKS				\
	TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS

static const struct udevice_id renesas_sdhi_match[] = {
	{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
	{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
	{ /* sentinel */ }
};

static int renesas_sdhi_probe(struct udevice *dev)
{
	struct tmio_sd_priv *priv = dev_get_priv(dev);
	u32 quirks = dev_get_driver_data(dev);
	struct fdt_resource reg_res;
	struct clk clk;
	DECLARE_GLOBAL_DATA_PTR;
	int ret;

	if (quirks == RENESAS_GEN2_QUIRKS) {
		ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
				       "reg", 0, &reg_res);
		if (ret < 0) {
			dev_err(dev, "\"reg\" resource not found, ret=%i\n",
				ret);
			return ret;
		}

		if (fdt_resource_size(&reg_res) == 0x100)
			quirks |= TMIO_SD_CAP_16BIT;
	}

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		dev_err(dev, "failed to get host clock\n");
		return ret;
	}

	/* set to max rate */
	priv->mclk = clk_set_rate(&clk, ULONG_MAX);
	if (IS_ERR_VALUE(priv->mclk)) {
		dev_err(dev, "failed to set rate for host clock\n");
		clk_free(&clk);
		return priv->mclk;
	}

	ret = clk_enable(&clk);
	clk_free(&clk);
	if (ret) {
		dev_err(dev, "failed to enable host clock\n");
		return ret;
	}

	ret = tmio_sd_probe(dev, quirks);
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	if (!ret)
		renesas_sdhi_reset_tuning(dev_get_priv(dev));
#endif
	return ret;
}

U_BOOT_DRIVER(renesas_sdhi) = {
	.name = "renesas-sdhi",
	.id = UCLASS_MMC,
	.of_match = renesas_sdhi_match,
	.bind = tmio_sd_bind,
	.probe = renesas_sdhi_probe,
	.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
	.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
	.ops = &renesas_sdhi_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e94cad93 MV	2	/*
e94cad93 MV	3	* Copyright (C) 2018 Marek Vasut <[email protected]>
e94cad93 MV	4	*/
	5
	6	#include <common.h>
	7	#include <clk.h>
	8	#include <fdtdec.h>
	9	#include <mmc.h>
	10	#include <dm.h>
	11	#include <linux/compat.h>
	12	#include <linux/dma-direction.h>
	13	#include <linux/io.h>
	14	#include <linux/sizes.h>
	15	#include <power/regulator.h>
	16	#include <asm/unaligned.h>
	17
cb0b6b03	18	#include "tmio-common.h"
e94cad93	19
f63968ba MV	20	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	21
	22	/* SCC registers */
	23	#define RENESAS_SDHI_SCC_DTCNTL 0x800
	24	#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
	25	#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
	26	#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
	27	#define RENESAS_SDHI_SCC_TAPSET 0x804
	28	#define RENESAS_SDHI_SCC_DT2FF 0x808
	29	#define RENESAS_SDHI_SCC_CKSEL 0x80c
	30	#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
	31	#define RENESAS_SDHI_SCC_RVSCNTL 0x810
	32	#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
	33	#define RENESAS_SDHI_SCC_RVSREQ 0x814
	34	#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
	35	#define RENESAS_SDHI_SCC_SMPCMP 0x818
	36	#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
	37
	38	#define RENESAS_SDHI_MAX_TAP 3
	39
cb0b6b03	40	static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
f63968ba MV	41	{
	42	u32 reg;
	43
	44	/* Initialize SCC */
cb0b6b03	45	tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
f63968ba	46
cb0b6b03 MV	47	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	48	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	49	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba MV	50
f63968ba MV	51	/* Set sampling clock selection range */
cb0b6b03	52	tmio_sd_writel(priv, 0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT,
f63968ba MV	53	RENESAS_SDHI_SCC_DTCNTL);
f63968ba MV	54
cb0b6b03	55	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL);
f63968ba	56	reg \|= RENESAS_SDHI_SCC_DTCNTL_TAPEN;
cb0b6b03	57	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_DTCNTL);
f63968ba	58
cb0b6b03	59	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
f63968ba	60	reg \|= RENESAS_SDHI_SCC_CKSEL_DTSEL;
cb0b6b03	61	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
f63968ba	62
cb0b6b03	63	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	64	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	65	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	66
cb0b6b03	67	tmio_sd_writel(priv, 0x300 /* scc_tappos */,
f63968ba MV	68	RENESAS_SDHI_SCC_DT2FF);
f63968ba MV	69
cb0b6b03 MV	70	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	71	reg \|= TMIO_SD_CLKCTL_SCLKEN;
	72	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba MV	73
f63968ba MV	74	/* Read TAPNUM */
cb0b6b03	75	return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
f63968ba MV	76	RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
	77	RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
	78	}
	79
cb0b6b03	80	static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
f63968ba MV	81	{
	82	u32 reg;
	83
	84	/* Reset SCC */
cb0b6b03 MV	85	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	86	reg &= ~TMIO_SD_CLKCTL_SCLKEN;
	87	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba	88
cb0b6b03	89	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
f63968ba	90	reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
cb0b6b03	91	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
f63968ba	92
cb0b6b03 MV	93	reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
	94	reg \|= TMIO_SD_CLKCTL_SCLKEN;
	95	tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
f63968ba	96
cb0b6b03	97	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	98	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	99	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	100
cb0b6b03	101	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	102	reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	103	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba MV	104	}
f63968ba MV	105
cb0b6b03	106	static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
f63968ba MV	107	unsigned long tap)
	108	{
	109	/* Set sampling clock position */
cb0b6b03	110	tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
f63968ba MV	111	}
f63968ba MV	112
cb0b6b03	113	static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
f63968ba MV	114	{
f63968ba MV	115	/* Get comparison of sampling data */
cb0b6b03	116	return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
f63968ba MV	117	}
f63968ba MV	118
cb0b6b03	119	static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
f63968ba MV	120	unsigned int tap_num, unsigned int taps,
	121	unsigned int smpcmp)
	122	{
	123	unsigned long tap_cnt; /* counter of tuning success */
	124	unsigned long tap_set; /* tap position */
	125	unsigned long tap_start;/* start position of tuning success */
	126	unsigned long tap_end; /* end position of tuning success */
	127	unsigned long ntap; /* temporary counter of tuning success */
	128	unsigned long match_cnt;/* counter of matching data */
	129	unsigned long i;
	130	bool select = false;
	131	u32 reg;
	132
	133	/* Clear SCC_RVSREQ */
cb0b6b03	134	tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
f63968ba MV	135
	136	/* Merge the results */
	137	for (i = 0; i < tap_num * 2; i++) {
	138	if (!(taps & BIT(i))) {
	139	taps &= ~BIT(i % tap_num);
	140	taps &= ~BIT((i % tap_num) + tap_num);
	141	}
	142	if (!(smpcmp & BIT(i))) {
	143	smpcmp &= ~BIT(i % tap_num);
	144	smpcmp &= ~BIT((i % tap_num) + tap_num);
	145	}
	146	}
	147
	148	/*
	149	* Find the longest consecutive run of successful probes. If that
	150	* is more than RENESAS_SDHI_MAX_TAP probes long then use the
	151	* center index as the tap.
	152	*/
	153	tap_cnt = 0;
	154	ntap = 0;
	155	tap_start = 0;
	156	tap_end = 0;
	157	for (i = 0; i < tap_num * 2; i++) {
	158	if (taps & BIT(i))
	159	ntap++;
	160	else {
	161	if (ntap > tap_cnt) {
	162	tap_start = i - ntap;
	163	tap_end = i - 1;
	164	tap_cnt = ntap;
	165	}
	166	ntap = 0;
	167	}
	168	}
	169
	170	if (ntap > tap_cnt) {
	171	tap_start = i - ntap;
	172	tap_end = i - 1;
	173	tap_cnt = ntap;
	174	}
	175
	176	/*
	177	* If all of the TAP is OK, the sampling clock position is selected by
	178	* identifying the change point of data.
	179	*/
	180	if (tap_cnt == tap_num * 2) {
	181	match_cnt = 0;
	182	ntap = 0;
	183	tap_start = 0;
	184	tap_end = 0;
	185	for (i = 0; i < tap_num * 2; i++) {
	186	if (smpcmp & BIT(i))
	187	ntap++;
	188	else {
	189	if (ntap > match_cnt) {
	190	tap_start = i - ntap;
	191	tap_end = i - 1;
	192	match_cnt = ntap;
	193	}
	194	ntap = 0;
	195	}
	196	}
	197	if (ntap > match_cnt) {
	198	tap_start = i - ntap;
199	tap_end = i - 1;
200	match_cnt = ntap;
201	}
202	if (match_cnt)
203	select = true;
204	} else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
205	select = true;
206
207	if (select)
208	tap_set = ((tap_start + tap_end) / 2) % tap_num;
209	else
210	return -EIO;
211
212	/* Set SCC */
cb0b6b03	213	tmio_sd_writel(priv, tap_set, RENESAS_SDHI_SCC_TAPSET);
f63968ba MV	214
f63968ba MV	215	/* Enable auto re-tuning */
cb0b6b03	216	reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba	217	reg \|= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
cb0b6b03	218	tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
f63968ba MV	219
	220	return 0;
	221	}
	222
	223	int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
	224	{
cb0b6b03	225	struct tmio_sd_priv *priv = dev_get_priv(dev);
f63968ba MV	226	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	227	struct mmc *mmc = upriv->mmc;
	228	unsigned int tap_num;
	229	unsigned int taps = 0, smpcmp = 0;
	230	int i, ret = 0;
	231	u32 caps;
	232
	233	/* Only supported on Renesas RCar */
cb0b6b03	234	if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
f63968ba MV	235	return -EINVAL;
	236
	237	/* clock tuning is not needed for upto 52MHz */
	238	if (!((mmc->selected_mode == MMC_HS_200) \|\|
	239	(mmc->selected_mode == UHS_SDR104) \|\|
	240	(mmc->selected_mode == UHS_SDR50)))
	241	return 0;
	242
	243	tap_num = renesas_sdhi_init_tuning(priv);
	244	if (!tap_num)
	245	/* Tuning is not supported */
	246	goto out;
	247
	248	if (tap_num * 2 >= sizeof(taps) * 8) {
	249	dev_err(dev,
	250	"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
	251	goto out;
	252	}
	253
	254	/* Issue CMD19 twice for each tap */
	255	for (i = 0; i < 2 * tap_num; i++) {
	256	renesas_sdhi_prepare_tuning(priv, i % tap_num);
	257
	258	/* Force PIO for the tuning */
	259	caps = priv->caps;
cb0b6b03	260	priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
f63968ba MV	261
	262	ret = mmc_send_tuning(mmc, opcode, NULL);
	263
	264	priv->caps = caps;
	265
	266	if (ret == 0)
	267	taps \|= BIT(i);
	268
	269	ret = renesas_sdhi_compare_scc_data(priv);
	270	if (ret == 0)
	271	smpcmp \|= BIT(i);
	272
	273	mdelay(1);
	274	}
	275
	276	ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
	277
	278	out:
	279	if (ret < 0) {
	280	dev_warn(dev, "Tuning procedure failed\n");
	281	renesas_sdhi_reset_tuning(priv);
	282	}
	283
	284	return ret;
	285	}
	286	#endif
	287
	288	static int renesas_sdhi_set_ios(struct udevice *dev)
	289	{
cb0b6b03	290	int ret = tmio_sd_set_ios(dev);
cf39f3f3 MV	291
	292	mdelay(10);
	293
f63968ba	294	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
cb0b6b03	295	struct tmio_sd_priv *priv = dev_get_priv(dev);
f63968ba MV	296
	297	renesas_sdhi_reset_tuning(priv);
	298	#endif
	299
	300	return ret;
	301	}
	302
e94cad93	303	static const struct dm_mmc_ops renesas_sdhi_ops = {
cb0b6b03	304	.send_cmd = tmio_sd_send_cmd,
f63968ba	305	.set_ios = renesas_sdhi_set_ios,
cb0b6b03	306	.get_cd = tmio_sd_get_cd,
f63968ba MV	307	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	308	.execute_tuning = renesas_sdhi_execute_tuning,
	309	#endif
e94cad93 MV	310	};
e94cad93 MV	311
cb0b6b03	312	#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
f98833db	313	#define RENESAS_GEN3_QUIRKS \
cb0b6b03	314	TMIO_SD_CAP_64BIT \| TMIO_SD_CAP_RCAR_GEN3 \| TMIO_SD_CAP_RCAR_UHS
f98833db	315
e94cad93	316	static const struct udevice_id renesas_sdhi_match[] = {
f98833db MV	317	{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
	318	{ .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
	319	{ .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
	320	{ .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
	321	{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
	322	{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
	323	{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
	324	{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
	325	{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
	326	{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
e94cad93 MV	327	{ /* sentinel */ }
	328	};
	329
c769e609 MV	330	static int renesas_sdhi_probe(struct udevice *dev)
c769e609 MV	331	{
30b5d9aa	332	struct tmio_sd_priv *priv = dev_get_priv(dev);
c769e609	333	u32 quirks = dev_get_driver_data(dev);
7cf7ef81	334	struct fdt_resource reg_res;
30b5d9aa	335	struct clk clk;
7cf7ef81 MV	336	DECLARE_GLOBAL_DATA_PTR;
	337	int ret;
	338
f98833db MV	339	if (quirks == RENESAS_GEN2_QUIRKS) {
	340	ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
	341	"reg", 0, &reg_res);
	342	if (ret < 0) {
	343	dev_err(dev, "\"reg\" resource not found, ret=%i\n",
	344	ret);
	345	return ret;
	346	}
7cf7ef81	347
f98833db	348	if (fdt_resource_size(&reg_res) == 0x100)
cb0b6b03	349	quirks \|= TMIO_SD_CAP_16BIT;
f98833db	350	}
c769e609	351
30b5d9aa MY	352	ret = clk_get_by_index(dev, 0, &clk);
	353	if (ret < 0) {
	354	dev_err(dev, "failed to get host clock\n");
	355	return ret;
	356	}
	357
	358	/* set to max rate */
	359	priv->mclk = clk_set_rate(&clk, ULONG_MAX);
	360	if (IS_ERR_VALUE(priv->mclk)) {
	361	dev_err(dev, "failed to set rate for host clock\n");
	362	clk_free(&clk);
	363	return priv->mclk;
	364	}
	365
	366	ret = clk_enable(&clk);
	367	clk_free(&clk);
	368	if (ret) {
	369	dev_err(dev, "failed to enable host clock\n");
	370	return ret;
	371	}
	372
cb0b6b03	373	ret = tmio_sd_probe(dev, quirks);
f63968ba MV	374	#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
	375	if (!ret)
	376	renesas_sdhi_reset_tuning(dev_get_priv(dev));
	377	#endif
	378	return ret;
c769e609 MV	379	}
c769e609 MV	380
e94cad93 MV	381	U_BOOT_DRIVER(renesas_sdhi) = {
	382	.name = "renesas-sdhi",
	383	.id = UCLASS_MMC,
	384	.of_match = renesas_sdhi_match,
cb0b6b03	385	.bind = tmio_sd_bind,
c769e609	386	.probe = renesas_sdhi_probe,
cb0b6b03 MV	387	.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
cb0b6b03 MV	388	.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
e94cad93 MV	389	.ops = &renesas_sdhi_ops,
e94cad93 MV	390	};