projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5c952cf0 WD |
1 | /* |
| 2 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> | |
| 3 | * Scott McNutt <[email protected]> | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __NIOS2_H__ | |
| 25 | #define __NIOS2_H__ | |
| 26 | ||
| 27 | /*------------------------------------------------------------------------ | |
| 28 | * Control registers -- use with wrctl() & rdctl() | |
| 29 | *----------------------------------------------------------------------*/ | |
| 30 | #define CTL_STATUS 0 /* Processor status reg */ | |
| 31 | #define CTL_ESTATUS 1 /* Exception status reg */ | |
| 32 | #define CTL_BSTATUS 2 /* Break status reg */ | |
| 33 | #define CTL_IENABLE 3 /* Interrut enable reg */ | |
| 34 | #define CTL_IPENDING 4 /* Interrut pending reg */ | |
| 35 | ||
| 36 | /*------------------------------------------------------------------------ | |
| 37 | * Access to control regs | |
| 38 | *----------------------------------------------------------------------*/ | |
| 5c952cf0 | 39 | |
| 4f63bfb6 TC |
40 | #define rdctl(reg) __builtin_rdctl(reg) |
| 41 | #define wrctl(reg, val) __builtin_wrctl(reg, val) | |
| 5c952cf0 WD |
42 | |
| 43 | /*------------------------------------------------------------------------ | |
| 44 | * Control reg bit masks | |
| 45 | *----------------------------------------------------------------------*/ | |
| 46 | #define STATUS_IE (1<<0) /* Interrupt enable */ | |
| 47 | #define STATUS_U (1<<1) /* User-mode */ | |
| 48 | ||
| 49 | /*------------------------------------------------------------------------ | |
| 50 | * Bit-31 Cache bypass -- only valid for data access. When data cache | |
| 51 | * is not implemented, bit 31 is ignored for compatibility. | |
| 52 | *----------------------------------------------------------------------*/ | |
| 53 | #define CACHE_BYPASS(a) ((a) | 0x80000000) | |
| 54 | #define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) | |
| 55 | ||
| 56 | #endif /* __NIOS2_H__ */ |