]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c35d7cf0 FK |
2 | /* |
3 | * (C) Copyright 2006-2008 | |
4 | * Texas Instruments. | |
5 | * Richard Woodruff <[email protected]> | |
6 | * Syed Mohammed Khasim <[email protected]> | |
7 | * | |
8 | * (C) Copyright 2009 | |
9 | * Frederik Kriewitz <[email protected]> | |
10 | * | |
11 | * Configuration settings for the DevKit8000 board. | |
c35d7cf0 FK |
12 | */ |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
c35d7cf0 FK |
16 | |
17 | /* High Level Configuration Options */ | |
308252ad | 18 | |
5183b7ec SS |
19 | /* |
20 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
21 | * 64 bytes before this address should be set aside for u-boot.img's | |
22 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
23 | * other needs. | |
24 | */ | |
66fca016 | 25 | |
875e4154 | 26 | /* Physical Memory Map */ |
875e4154 | 27 | |
a91ef4ad | 28 | #include <configs/ti_omap3_common.h> |
875e4154 | 29 | |
c35d7cf0 | 30 | /* Hardware drivers */ |
c35d7cf0 | 31 | /* DM9000 */ |
c35d7cf0 FK |
32 | #define CONFIG_DM9000_BASE 0x2c000000 |
33 | #define DM9000_IO CONFIG_DM9000_BASE | |
34 | #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) | |
35 | #define CONFIG_DM9000_USE_16BIT 1 | |
36 | #define CONFIG_DM9000_NO_SROM 1 | |
37 | #undef CONFIG_DM9000_DEBUG | |
38 | ||
c35d7cf0 | 39 | /* TWL4030 */ |
c35d7cf0 | 40 | |
c35d7cf0 | 41 | /* BOOTP/DHCP options */ |
c35d7cf0 FK |
42 | |
43 | /* Environment information */ | |
c35d7cf0 FK |
44 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
45 | "loadaddr=0x82000000\0" \ | |
2d76da24 | 46 | "console=ttyO2,115200n8\0" \ |
f408501d | 47 | "mmcdev=0\0" \ |
c35d7cf0 FK |
48 | "vram=12M\0" \ |
49 | "dvimode=1024x768MR-16@60\0" \ | |
50 | "defaultdisplay=dvi\0" \ | |
51 | "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ | |
52 | "kernelopts=rw\0" \ | |
53 | "commonargs=" \ | |
54 | "setenv bootargs console=${console} " \ | |
55 | "vram=${vram} " \ | |
56 | "omapfb.mode=dvi:${dvimode} " \ | |
57 | "omapdss.def_disp=${defaultdisplay}\0" \ | |
58 | "mmcargs=" \ | |
59 | "run commonargs; " \ | |
60 | "setenv bootargs ${bootargs} " \ | |
61 | "root=/dev/mmcblk0p2 " \ | |
b72db208 | 62 | "rootwait " \ |
c35d7cf0 FK |
63 | "${kernelopts}\0" \ |
64 | "nandargs=" \ | |
65 | "run commonargs; " \ | |
66 | "setenv bootargs ${bootargs} " \ | |
67 | "omapfb.mode=dvi:${dvimode} " \ | |
68 | "omapdss.def_disp=${defaultdisplay} " \ | |
69 | "root=/dev/mtdblock4 " \ | |
70 | "rootfstype=jffs2 " \ | |
71 | "${kernelopts}\0" \ | |
72 | "netargs=" \ | |
73 | "run commonargs; " \ | |
74 | "setenv bootargs ${bootargs} " \ | |
75 | "root=/dev/nfs " \ | |
76 | "nfsroot=${serverip}:${rootpath},${nfsopts} " \ | |
77 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ | |
78 | "${kernelopts} " \ | |
79 | "dnsip1=${dnsip} " \ | |
80 | "dnsip2=${dnsip2}\0" \ | |
f408501d | 81 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
c35d7cf0 FK |
82 | "bootscript=echo Running bootscript from mmc ...; " \ |
83 | "source ${loadaddr}\0" \ | |
f408501d | 84 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
c35d7cf0 FK |
85 | "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ |
86 | "mmcboot=echo Booting from mmc ...; " \ | |
87 | "run mmcargs; " \ | |
88 | "bootm ${loadaddr}\0" \ | |
89 | "nandboot=echo Booting from nand ...; " \ | |
90 | "run nandargs; " \ | |
91 | "nand read ${loadaddr} 280000 400000; " \ | |
92 | "bootm ${loadaddr}\0" \ | |
93 | "netboot=echo Booting from network ...; " \ | |
94 | "dhcp ${loadaddr}; " \ | |
95 | "run netargs; " \ | |
96 | "bootm ${loadaddr}\0" \ | |
66968110 | 97 | "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ |
c35d7cf0 FK |
98 | "if run loadbootscript; then " \ |
99 | "run bootscript; " \ | |
100 | "else " \ | |
101 | "if run loaduimage; then " \ | |
102 | "run mmcboot; " \ | |
103 | "else run nandboot; " \ | |
104 | "fi; " \ | |
105 | "fi; " \ | |
106 | "else run nandboot; fi\0" | |
107 | ||
3f6a4922 | 108 | /* Defines for SPL */ |
3f6a4922 | 109 | |
3f6a4922 | 110 | /* NAND boot config */ |
3f6a4922 SS |
111 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ |
112 | 10, 11, 12, 13} | |
113 | ||
114 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
115 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
116 | ||
3f6a4922 SS |
117 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 |
118 | ||
875e4154 AB |
119 | #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR |
120 | #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS | |
b6144dfc TR |
121 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ |
122 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ | |
123 | ||
c35d7cf0 | 124 | #endif /* __CONFIG_H */ |