[J-u-boot.git] / drivers / rtc / m41t62.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2018
 * Lukasz Majewski, DENX Software Engineering, [email protected].
 *
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, [email protected].
 *
 * based on a the Linux rtc-m41t80.c driver which is:
 *   Alexander Bigga <[email protected]>, 2006 (c) mycable GmbH
 */

/*
 * Date & Time support for STMicroelectronics M41T62
 */

/* #define	DEBUG	*/

#include <common.h>
#include <command.h>
#include <dm.h>
#include <log.h>
#include <rtc.h>
#include <i2c.h>
#include <linux/log2.h>
#include <linux/delay.h>

#define M41T62_REG_SSEC	0
#define M41T62_REG_SEC	1
#define M41T62_REG_MIN	2
#define M41T62_REG_HOUR	3
#define M41T62_REG_WDAY	4
#define M41T62_REG_DAY	5
#define M41T62_REG_MON	6
#define M41T62_REG_YEAR	7
#define M41T62_REG_ALARM_MON	0xa
#define M41T62_REG_ALARM_DAY	0xb
#define M41T62_REG_ALARM_HOUR	0xc
#define M41T62_REG_ALARM_MIN	0xd
#define M41T62_REG_ALARM_SEC	0xe
#define M41T62_REG_FLAGS	0xf

#define M41T62_DATETIME_REG_SIZE	(M41T62_REG_YEAR + 1)
#define M41T62_ALARM_REG_SIZE	\
	(M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)

#define M41T62_SEC_ST		(1 << 7)	/* ST: Stop Bit */
#define M41T62_ALMON_AFE	(1 << 7)	/* AFE: AF Enable Bit */
#define M41T62_ALMON_SQWE	(1 << 6)	/* SQWE: SQW Enable Bit */
#define M41T62_ALHOUR_HT	(1 << 6)	/* HT: Halt Update Bit */
#define M41T62_FLAGS_AF		(1 << 6)	/* AF: Alarm Flag Bit */
#define M41T62_FLAGS_OF		(1 << 2)	/* OF: Oscillator Flag Bit */
#define M41T62_FLAGS_BATT_LOW	(1 << 4)	/* BL: Battery Low Bit */

#define M41T62_WDAY_SQW_FREQ_MASK	0xf0
#define M41T62_WDAY_SQW_FREQ_SHIFT	4

#define M41T62_SQW_MAX_FREQ	32768

#define M41T62_FEATURE_HT	(1 << 0)
#define M41T62_FEATURE_BL	(1 << 1)

#define M41T80_ALHOUR_HT	(1 << 6)	/* HT: Halt Update Bit */

static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf)
{
	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	      "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
	      __FUNCTION__,
	      buf[0], buf[1], buf[2], buf[3],
	      buf[4], buf[5], buf[6], buf[7]);

	tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
	tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
	tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
	tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
	tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
	tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);

	/* assume 20YY not 19YY, and ignore the Century Bit */
	/* U-Boot needs to add 1900 here */
	tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;

	debug("%s: tm is secs=%d, mins=%d, hours=%d, "
	      "mday=%d, mon=%d, year=%d, wday=%d\n",
	      __FUNCTION__,
	      tm->tm_sec, tm->tm_min, tm->tm_hour,
	      tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
}

static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf)
{
	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	      tm->tm_hour, tm->tm_min, tm->tm_sec);

	/* Merge time-data and register flags into buf[0..7] */
	buf[M41T62_REG_SSEC] = 0;
	buf[M41T62_REG_SEC] =
		bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f);
	buf[M41T62_REG_MIN] =
		bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f);
	buf[M41T62_REG_HOUR] =
		bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ;
	buf[M41T62_REG_WDAY] =
		(tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07);
	buf[M41T62_REG_DAY] =
		bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
	buf[M41T62_REG_MON] =
		bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
	/* assume 20YY not 19YY */
	buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
}

#ifdef CONFIG_DM_RTC
static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm)
{
	u8 buf[M41T62_DATETIME_REG_SIZE];
	int ret;

	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
	if (ret)
		return ret;

	m41t62_update_rtc_time(tm, buf);

	return 0;
}

static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm)
{
	u8 buf[M41T62_DATETIME_REG_SIZE];
	int ret;

	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
	if (ret)
		return ret;

	m41t62_set_rtc_buf(tm, buf);

	ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
	if (ret) {
		printf("I2C write failed in %s()\n", __func__);
		return ret;
	}

	return 0;
}

static int m41t62_sqw_enable(struct udevice *dev, bool enable)
{
	u8 val;
	int ret;

	ret = dm_i2c_read(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
	if (ret)
		return ret;

	if (enable)
		val |= M41T62_ALMON_SQWE;
	else
		val &= ~M41T62_ALMON_SQWE;

	return dm_i2c_write(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
}

static int m41t62_sqw_set_rate(struct udevice *dev, unsigned int rate)
{
	u8 val, newval, sqwrateval;
	int ret;

	if (rate >= M41T62_SQW_MAX_FREQ)
		sqwrateval = 1;
	else if (rate >= M41T62_SQW_MAX_FREQ / 4)
		sqwrateval = 2;
	else if (rate)
		sqwrateval = 15 - ilog2(rate);

	ret = dm_i2c_read(dev, M41T62_REG_WDAY, &val, sizeof(val));
	if (ret)
		return ret;

	newval = val;
	newval &= ~M41T62_WDAY_SQW_FREQ_MASK;
	newval |= (sqwrateval << M41T62_WDAY_SQW_FREQ_SHIFT);

	/*
	 * Try to avoid writing unchanged values. Writing to this register
	 * will reset the internal counter pipeline and thus affect system
	 * time.
	 */
	if (newval == val)
		return 0;

	return dm_i2c_write(dev, M41T62_REG_WDAY, &newval, sizeof(newval));
}

static int m41t62_rtc_restart_osc(struct udevice *dev)
{
	u8 val;
	int ret;

	/* 0. check if oscillator failure happened */
	ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
	if (ret)
		return ret;
	if (!(val & M41T62_FLAGS_OF))
		return 0;

	ret = dm_i2c_read(dev, M41T62_REG_SEC, &val, sizeof(val));
	if (ret)
		return ret;

	/* 1. Set stop bit */
	val |= M41T62_SEC_ST;
	ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
	if (ret)
		return ret;

	/* 2. Clear stop bit */
	val &= ~M41T62_SEC_ST;
	ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
	if (ret)
		return ret;

	/* 3. wait 4 seconds */
	mdelay(4000);

	ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
	if (ret)
		return ret;

	/* 4. clear M41T62_FLAGS_OF bit */
	val &= ~M41T62_FLAGS_OF;
	ret = dm_i2c_write(dev, M41T62_REG_FLAGS, &val, sizeof(val));
	if (ret)
		return ret;

	return 0;
}

static int m41t62_rtc_clear_ht(struct udevice *dev)
{
	u8 val;
	int ret;

	/*
	 * M41T82: Make sure HT (Halt Update) bit is cleared.
	 * This bit is 0 in M41T62 so its save to clear it always.
	 */

	ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
	if (ret)
		return ret;
	val &= ~M41T80_ALHOUR_HT;
	ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
	if (ret)
		return ret;

	return 0;
}

static int m41t62_rtc_reset(struct udevice *dev)
{
	int ret;

	ret = m41t62_rtc_restart_osc(dev);
	if (ret)
		return ret;

	ret = m41t62_rtc_clear_ht(dev);
	if (ret)
		return ret;

	/*
	 * Some boards feed the square wave as clock input into
	 * the SoC. This enables a 32.768kHz square wave, which is
	 * also the hardware default after power-loss.
	 */
	ret = m41t62_sqw_set_rate(dev, 32768);
	if (ret)
		return ret;
	return m41t62_sqw_enable(dev, true);
}

/*
 * Make sure HT bit is cleared. This bit is set on entering battery backup
 * mode, so do this before the first read access.
 */
static int m41t62_rtc_probe(struct udevice *dev)
{
	return m41t62_rtc_clear_ht(dev);
}

static const struct rtc_ops m41t62_rtc_ops = {
	.get = m41t62_rtc_get,
	.set = m41t62_rtc_set,
	.reset = m41t62_rtc_reset,
};

static const struct udevice_id m41t62_rtc_ids[] = {
	{ .compatible = "st,m41t62" },
	{ .compatible = "st,m41t82" },
	{ .compatible = "st,m41st87" },
	{ .compatible = "microcrystal,rv4162" },
	{ }
};

U_BOOT_DRIVER(rtc_m41t62) = {
	.name	= "rtc-m41t62",
	.id	= UCLASS_RTC,
	.of_match = m41t62_rtc_ids,
	.ops	= &m41t62_rtc_ops,
	.probe  = &m41t62_rtc_probe,
};

#else /* NON DM RTC code - will be removed */
int rtc_get(struct rtc_time *tm)
{
	u8 buf[M41T62_DATETIME_REG_SIZE];

	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
	m41t62_update_rtc_time(tm, buf);

	return 0;
}

int rtc_set(struct rtc_time *tm)
{
	u8 buf[M41T62_DATETIME_REG_SIZE];

	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
	m41t62_set_rtc_buf(tm, buf);

	if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
		      M41T62_DATETIME_REG_SIZE)) {
		printf("I2C write failed in %s()\n", __func__);
		return -1;
	}

	return 0;
}

void rtc_reset(void)
{
	u8 val;

	/*
	 * M41T82: Make sure HT (Halt Update) bit is cleared.
	 * This bit is 0 in M41T62 so its save to clear it always.
	 */
	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
	val &= ~M41T80_ALHOUR_HT;
	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
}
#endif /* CONFIG_DM_RTC */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
88aff62d	2	/*
c8c0242f LM	3	* (C) Copyright 2018
	4	* Lukasz Majewski, DENX Software Engineering, [email protected].
	5	*
88aff62d SR	6	* (C) Copyright 2008
	7	* Stefan Roese, DENX Software Engineering, [email protected].
	8	*
	9	* based on a the Linux rtc-m41t80.c driver which is:
	10	* Alexander Bigga <[email protected]>, 2006 (c) mycable GmbH
88aff62d SR	11	*/
	12
	13	/*
	14	* Date & Time support for STMicroelectronics M41T62
	15	*/
	16
	17	/* #define DEBUG */
	18
	19	#include <common.h>
	20	#include <command.h>
c8c0242f	21	#include <dm.h>
f7ae49fc	22	#include <log.h>
88aff62d SR	23	#include <rtc.h>
88aff62d SR	24	#include <i2c.h>
8691198d	25	#include <linux/log2.h>
9bbe2105	26	#include <linux/delay.h>
88aff62d	27
88aff62d SR	28	#define M41T62_REG_SSEC 0
	29	#define M41T62_REG_SEC 1
	30	#define M41T62_REG_MIN 2
	31	#define M41T62_REG_HOUR 3
	32	#define M41T62_REG_WDAY 4
	33	#define M41T62_REG_DAY 5
	34	#define M41T62_REG_MON 6
	35	#define M41T62_REG_YEAR 7
	36	#define M41T62_REG_ALARM_MON 0xa
	37	#define M41T62_REG_ALARM_DAY 0xb
	38	#define M41T62_REG_ALARM_HOUR 0xc
	39	#define M41T62_REG_ALARM_MIN 0xd
	40	#define M41T62_REG_ALARM_SEC 0xe
	41	#define M41T62_REG_FLAGS 0xf
	42
	43	#define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1)
	44	#define M41T62_ALARM_REG_SIZE \
	45	(M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)
	46
	47	#define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */
	48	#define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */
	49	#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */
	50	#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
	51	#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */
9bbe2105	52	#define M41T62_FLAGS_OF (1 << 2) /* OF: Oscillator Flag Bit */
88aff62d SR	53	#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */
88aff62d SR	54
8691198d SR	55	#define M41T62_WDAY_SQW_FREQ_MASK 0xf0
	56	#define M41T62_WDAY_SQW_FREQ_SHIFT 4
	57
	58	#define M41T62_SQW_MAX_FREQ 32768
	59
88aff62d SR	60	#define M41T62_FEATURE_HT (1 << 0)
	61	#define M41T62_FEATURE_BL (1 << 1)
	62
038f3c54 SR	63	#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
038f3c54 SR	64
7afc4155	65	static void m41t62_update_rtc_time(struct rtc_time tm, u8 buf)
88aff62d	66	{
88aff62d SR	67	debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	68	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
	69	__FUNCTION__,
	70	buf[0], buf[1], buf[2], buf[3],
	71	buf[4], buf[5], buf[6], buf[7]);
	72
e84aba13 AT	73	tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
	74	tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
	75	tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
	76	tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
88aff62d	77	tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
e84aba13	78	tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);
88aff62d SR	79
	80	/* assume 20YY not 19YY, and ignore the Century Bit */
	81	/* U-Boot needs to add 1900 here */
e84aba13	82	tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;
88aff62d SR	83
	84	debug("%s: tm is secs=%d, mins=%d, hours=%d, "
	85	"mday=%d, mon=%d, year=%d, wday=%d\n",
	86	__FUNCTION__,
	87	tm->tm_sec, tm->tm_min, tm->tm_hour,
	88	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	89	}
	90
7afc4155	91	static void m41t62_set_rtc_buf(const struct rtc_time tm, u8 buf)
88aff62d	92	{
88aff62d SR	93	debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	94	tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
	95	tm->tm_hour, tm->tm_min, tm->tm_sec);
	96
88aff62d SR	97	/* Merge time-data and register flags into buf[0..7] */
	98	buf[M41T62_REG_SSEC] = 0;
	99	buf[M41T62_REG_SEC] =
e84aba13	100	bin2bcd(tm->tm_sec) \| (buf[M41T62_REG_SEC] & ~0x7f);
88aff62d	101	buf[M41T62_REG_MIN] =
e84aba13	102	bin2bcd(tm->tm_min) \| (buf[M41T62_REG_MIN] & ~0x7f);
88aff62d	103	buf[M41T62_REG_HOUR] =
e84aba13	104	bin2bcd(tm->tm_hour) \| (buf[M41T62_REG_HOUR] & ~0x3f) ;
88aff62d SR	105	buf[M41T62_REG_WDAY] =
	106	(tm->tm_wday & 0x07) \| (buf[M41T62_REG_WDAY] & ~0x07);
	107	buf[M41T62_REG_DAY] =
e84aba13	108	bin2bcd(tm->tm_mday) \| (buf[M41T62_REG_DAY] & ~0x3f);
88aff62d	109	buf[M41T62_REG_MON] =
e84aba13	110	bin2bcd(tm->tm_mon) \| (buf[M41T62_REG_MON] & ~0x1f);
88aff62d	111	/* assume 20YY not 19YY */
e84aba13	112	buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
7afc4155 LM	113	}
7afc4155 LM	114
c8c0242f LM	115	#ifdef CONFIG_DM_RTC
	116	static int m41t62_rtc_get(struct udevice dev, struct rtc_time tm)
	117	{
	118	u8 buf[M41T62_DATETIME_REG_SIZE];
	119	int ret;
	120
	121	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
	122	if (ret)
	123	return ret;
	124
	125	m41t62_update_rtc_time(tm, buf);
	126
	127	return 0;
	128	}
	129
	130	static int m41t62_rtc_set(struct udevice dev, const struct rtc_time tm)
	131	{
	132	u8 buf[M41T62_DATETIME_REG_SIZE];
	133	int ret;
	134
	135	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
	136	if (ret)
	137	return ret;
	138
	139	m41t62_set_rtc_buf(tm, buf);
	140
	141	ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
	142	if (ret) {
	143	printf("I2C write failed in %s()\n", __func__);
	144	return ret;
	145	}
	146
	147	return 0;
	148	}
	149
8691198d SR	150	static int m41t62_sqw_enable(struct udevice *dev, bool enable)
	151	{
	152	u8 val;
	153	int ret;
	154
	155	ret = dm_i2c_read(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
	156	if (ret)
	157	return ret;
	158
	159	if (enable)
	160	val \|= M41T62_ALMON_SQWE;
	161	else
	162	val &= ~M41T62_ALMON_SQWE;
	163
	164	return dm_i2c_write(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
	165	}
	166
	167	static int m41t62_sqw_set_rate(struct udevice *dev, unsigned int rate)
	168	{
	169	u8 val, newval, sqwrateval;
	170	int ret;
	171
	172	if (rate >= M41T62_SQW_MAX_FREQ)
	173	sqwrateval = 1;
	174	else if (rate >= M41T62_SQW_MAX_FREQ / 4)
	175	sqwrateval = 2;
	176	else if (rate)
	177	sqwrateval = 15 - ilog2(rate);
	178
	179	ret = dm_i2c_read(dev, M41T62_REG_WDAY, &val, sizeof(val));
	180	if (ret)
	181	return ret;
	182
	183	newval = val;
	184	newval &= ~M41T62_WDAY_SQW_FREQ_MASK;
	185	newval \|= (sqwrateval << M41T62_WDAY_SQW_FREQ_SHIFT);
	186
	187	/*
	188	* Try to avoid writing unchanged values. Writing to this register
	189	* will reset the internal counter pipeline and thus affect system
	190	* time.
	191	*/
	192	if (newval == val)
	193	return 0;
	194
	195	return dm_i2c_write(dev, M41T62_REG_WDAY, &newval, sizeof(newval));
	196	}
	197
9bbe2105 SR	198	static int m41t62_rtc_restart_osc(struct udevice *dev)
	199	{
	200	u8 val;
	201	int ret;
	202
	203	/* 0. check if oscillator failure happened */
	204	ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
	205	if (ret)
	206	return ret;
	207	if (!(val & M41T62_FLAGS_OF))
	208	return 0;
	209
	210	ret = dm_i2c_read(dev, M41T62_REG_SEC, &val, sizeof(val));
	211	if (ret)
	212	return ret;
	213
	214	/* 1. Set stop bit */
	215	val \|= M41T62_SEC_ST;
92cf458f	216	ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
9bbe2105 SR	217	if (ret)
	218	return ret;
	219
	220	/* 2. Clear stop bit */
	221	val &= ~M41T62_SEC_ST;
92cf458f	222	ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
9bbe2105 SR	223	if (ret)
	224	return ret;
	225
	226	/* 3. wait 4 seconds */
	227	mdelay(4000);
	228
	229	ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
	230	if (ret)
	231	return ret;
	232
	233	/* 4. clear M41T62_FLAGS_OF bit */
	234	val &= ~M41T62_FLAGS_OF;
	235	ret = dm_i2c_write(dev, M41T62_REG_FLAGS, &val, sizeof(val));
	236	if (ret)
	237	return ret;
	238
	239	return 0;
	240	}
	241
8691198d	242	static int m41t62_rtc_clear_ht(struct udevice *dev)
c8c0242f LM	243	{
c8c0242f LM	244	u8 val;
8691198d	245	int ret;
c8c0242f LM	246
	247	/*
	248	* M41T82: Make sure HT (Halt Update) bit is cleared.
	249	* This bit is 0 in M41T62 so its save to clear it always.
	250	*/
	251
8691198d SR	252	ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
	253	if (ret)
	254	return ret;
c8c0242f	255	val &= ~M41T80_ALHOUR_HT;
8691198d SR	256	ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
	257	if (ret)
	258	return ret;
	259
	260	return 0;
	261	}
c8c0242f	262
8691198d SR	263	static int m41t62_rtc_reset(struct udevice *dev)
	264	{
	265	int ret;
	266
9bbe2105 SR	267	ret = m41t62_rtc_restart_osc(dev);
	268	if (ret)
	269	return ret;
	270
8691198d SR	271	ret = m41t62_rtc_clear_ht(dev);
	272	if (ret)
	273	return ret;
	274
	275	/*
	276	* Some boards feed the square wave as clock input into
	277	* the SoC. This enables a 32.768kHz square wave, which is
	278	* also the hardware default after power-loss.
	279	*/
	280	ret = m41t62_sqw_set_rate(dev, 32768);
	281	if (ret)
	282	return ret;
	283	return m41t62_sqw_enable(dev, true);
c8c0242f LM	284	}
c8c0242f LM	285
4e829e98 SG	286	/*
	287	* Make sure HT bit is cleared. This bit is set on entering battery backup
	288	* mode, so do this before the first read access.
	289	*/
	290	static int m41t62_rtc_probe(struct udevice *dev)
	291	{
8691198d	292	return m41t62_rtc_clear_ht(dev);
4e829e98 SG	293	}
4e829e98 SG	294
c8c0242f LM	295	static const struct rtc_ops m41t62_rtc_ops = {
	296	.get = m41t62_rtc_get,
	297	.set = m41t62_rtc_set,
	298	.reset = m41t62_rtc_reset,
	299	};
	300
	301	static const struct udevice_id m41t62_rtc_ids[] = {
	302	{ .compatible = "st,m41t62" },
4e829e98	303	{ .compatible = "st,m41t82" },
b371accc	304	{ .compatible = "st,m41st87" },
c8c0242f LM	305	{ .compatible = "microcrystal,rv4162" },
	306	{ }
	307	};
	308
	309	U_BOOT_DRIVER(rtc_m41t62) = {
	310	.name = "rtc-m41t62",
	311	.id = UCLASS_RTC,
	312	.of_match = m41t62_rtc_ids,
	313	.ops = &m41t62_rtc_ops,
4e829e98	314	.probe = &m41t62_rtc_probe,
c8c0242f LM	315	};
	316
	317	#else /* NON DM RTC code - will be removed */
7afc4155 LM	318	int rtc_get(struct rtc_time *tm)
	319	{
	320	u8 buf[M41T62_DATETIME_REG_SIZE];
	321
	322	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
	323	m41t62_update_rtc_time(tm, buf);
	324
	325	return 0;
	326	}
	327
	328	int rtc_set(struct rtc_time *tm)
	329	{
	330	u8 buf[M41T62_DATETIME_REG_SIZE];
	331
	332	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
	333	m41t62_set_rtc_buf(tm, buf);
88aff62d	334
4d3df956 LM	335	if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
4d3df956 LM	336	M41T62_DATETIME_REG_SIZE)) {
88aff62d	337	printf("I2C write failed in %s()\n", __func__);
d1e23194 JCPV	338	return -1;
	339	}
	340
	341	return 0;
88aff62d SR	342	}
	343
	344	void rtc_reset(void)
	345	{
038f3c54 SR	346	u8 val;
038f3c54 SR	347
88aff62d	348	/*
038f3c54 SR	349	* M41T82: Make sure HT (Halt Update) bit is cleared.
038f3c54 SR	350	* This bit is 0 in M41T62 so its save to clear it always.
88aff62d	351	*/
038f3c54 SR	352	i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
	353	val &= ~M41T80_ALHOUR_HT;
	354	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
88aff62d	355	}
c8c0242f	356	#endif /* CONFIG_DM_RTC */