[J-u-boot.git] / drivers / reset / stm32-reset.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Patrice Chotard, <[email protected]> for STMicroelectronics.
 */

#define LOG_CATEGORY UCLASS_RESET

#include <dm.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <reset-uclass.h>
#include <stm32_rcc.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>

/* offset of register without set/clear management */
#define RCC_MP_GCR_OFFSET 0x10C

/* reset clear offset for STM32MP RCC */
#define RCC_CL 0x4

struct stm32_reset_priv {
	fdt_addr_t base;
};

static int stm32_reset_assert(struct reset_ctl *reset_ctl)
{
	struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
	int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
	int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);

	dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
		reset_ctl->id, bank, offset);

	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
		if (bank != RCC_MP_GCR_OFFSET)
			/* reset assert is done in rcc set register */
			writel(BIT(offset), priv->base + bank);
		else
			clrbits_le32(priv->base + bank, BIT(offset));
	else
		setbits_le32(priv->base + bank, BIT(offset));

	return 0;
}

static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
{
	struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
	int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
	int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);

	dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
		reset_ctl->id, bank, offset);

	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
		if (bank != RCC_MP_GCR_OFFSET)
			/* reset deassert is done in rcc clr register */
			writel(BIT(offset), priv->base + bank + RCC_CL);
		else
			setbits_le32(priv->base + bank, BIT(offset));
	else
		clrbits_le32(priv->base + bank, BIT(offset));

	return 0;
}

static const struct reset_ops stm32_reset_ops = {
	.rst_assert	= stm32_reset_assert,
	.rst_deassert	= stm32_reset_deassert,
};

static int stm32_reset_probe(struct udevice *dev)
{
	struct stm32_reset_priv *priv = dev_get_priv(dev);

	priv->base = dev_read_addr(dev);
	if (priv->base == FDT_ADDR_T_NONE) {
		/* for MFD, get address of parent */
		priv->base = dev_read_addr(dev->parent);
		if (priv->base == FDT_ADDR_T_NONE)
			return -EINVAL;
	}

	return 0;
}

U_BOOT_DRIVER(stm32_rcc_reset) = {
	.name			= "stm32_rcc_reset",
	.id			= UCLASS_RESET,
	.probe			= stm32_reset_probe,
	.priv_auto	= sizeof(struct stm32_reset_priv),
	.ops			= &stm32_reset_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
23a06416	2	/*
3bc599c9	3	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
0f8106f8	4	* Author(s): Patrice Chotard, <[email protected]> for STMicroelectronics.
23a06416 PC	5	*/
23a06416 PC	6
829c92b1 PD	7	#define LOG_CATEGORY UCLASS_RESET
829c92b1 PD	8
23a06416 PC	9	#include <dm.h>
23a06416 PC	10	#include <errno.h>
f7ae49fc	11	#include <log.h>
336d4615	12	#include <malloc.h>
23a06416	13	#include <reset-uclass.h>
d090cbab	14	#include <stm32_rcc.h>
23a06416	15	#include <asm/io.h>
829c92b1	16	#include <dm/device_compat.h>
cd93d625	17	#include <linux/bitops.h>
23a06416	18
d8d29a44 PD	19	/* offset of register without set/clear management */
	20	#define RCC_MP_GCR_OFFSET 0x10C
	21
a7519b33 PD	22	/* reset clear offset for STM32MP RCC */
	23	#define RCC_CL 0x4
	24
23a06416 PC	25	struct stm32_reset_priv {
	26	fdt_addr_t base;
	27	};
	28
23a06416 PC	29	static int stm32_reset_assert(struct reset_ctl *reset_ctl)
	30	{
	31	struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
6d734be9 PC	32	int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
6d734be9 PC	33	int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
829c92b1 PD	34
	35	dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
	36	reset_ctl->id, bank, offset);
23a06416	37
d090cbab	38	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
d8d29a44 PD	39	if (bank != RCC_MP_GCR_OFFSET)
	40	/* reset assert is done in rcc set register */
	41	writel(BIT(offset), priv->base + bank);
	42	else
	43	clrbits_le32(priv->base + bank, BIT(offset));
a7519b33 PD	44	else
a7519b33 PD	45	setbits_le32(priv->base + bank, BIT(offset));
23a06416 PC	46
	47	return 0;
	48	}
	49
	50	static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
	51	{
	52	struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
6d734be9 PC	53	int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
6d734be9 PC	54	int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
829c92b1 PD	55
	56	dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
	57	reset_ctl->id, bank, offset);
23a06416	58
d090cbab	59	if (dev_get_driver_data(reset_ctl->dev) == STM32MP1)
d8d29a44 PD	60	if (bank != RCC_MP_GCR_OFFSET)
	61	/* reset deassert is done in rcc clr register */
	62	writel(BIT(offset), priv->base + bank + RCC_CL);
	63	else
	64	setbits_le32(priv->base + bank, BIT(offset));
a7519b33 PD	65	else
a7519b33 PD	66	clrbits_le32(priv->base + bank, BIT(offset));
23a06416 PC	67
	68	return 0;
	69	}
	70
	71	static const struct reset_ops stm32_reset_ops = {
23a06416 PC	72	.rst_assert = stm32_reset_assert,
	73	.rst_deassert = stm32_reset_deassert,
	74	};
	75
	76	static int stm32_reset_probe(struct udevice *dev)
	77	{
	78	struct stm32_reset_priv *priv = dev_get_priv(dev);
	79
a7519b33 PD	80	priv->base = dev_read_addr(dev);
	81	if (priv->base == FDT_ADDR_T_NONE) {
	82	/* for MFD, get address of parent */
	83	priv->base = dev_read_addr(dev->parent);
	84	if (priv->base == FDT_ADDR_T_NONE)
	85	return -EINVAL;
	86	}
23a06416 PC	87
	88	return 0;
	89	}
	90
	91	U_BOOT_DRIVER(stm32_rcc_reset) = {
	92	.name = "stm32_rcc_reset",
	93	.id = UCLASS_RESET,
	94	.probe = stm32_reset_probe,
41575d8e	95	.priv_auto = sizeof(struct stm32_reset_priv),
23a06416 PC	96	.ops = &stm32_reset_ops,
23a06416 PC	97	};