projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| bb52f1c6 EH |
1 | // SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | /* | |
| 3 | * Copyright (c) 2021 Rockchip Electronics Co., Ltd. | |
| 4 | * Copyright (c) 2022 Collabora Ltd. | |
| 5 | * Author: Sebastian Reichel <[email protected]> | |
| 6 | */ | |
| 7 | ||
| bb52f1c6 EH |
8 | #include <dm.h> |
| 9 | #include <asm/arch-rockchip/clock.h> | |
| 10 | #include <dt-bindings/reset/rockchip,rk3588-cru.h> | |
| 11 | ||
| 12 | /* 0xFD7C0000 + 0x0A00 */ | |
| 13 | #define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) | |
| 14 | ||
| 15 | /* 0xFD7C8000 + 0x0A00 */ | |
| 16 | #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) | |
| 17 | ||
| 18 | /* 0xFD7D0000 + 0x0A00 */ | |
| 19 | #define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) | |
| 20 | ||
| 21 | /* 0xFD7F0000 + 0x0A00 */ | |
| 22 | #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) | |
| 23 | ||
| 24 | /* mapping table for reset ID to register offset */ | |
| 25 | static const int rk3588_register_offset[] = { | |
| 26 | /* SOFTRST_CON01 */ | |
| 27 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), | |
| 28 | RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4), | |
| 29 | RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6), | |
| 30 | RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM | |
| 31 | RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8), | |
| 32 | RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM | |
| 33 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15), | |
| 34 | ||
| 35 | /* SOFTRST_CON02 */ | |
| 36 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0), | |
| 37 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1), | |
| 38 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2), | |
| 39 | RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3), | |
| 40 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8), | |
| 41 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9), | |
| 42 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10), | |
| 43 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11), | |
| 44 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15), | |
| 45 | ||
| 46 | /* SOFTRST_CON03 */ | |
| 47 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0), | |
| 48 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1), | |
| 49 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2), | |
| 50 | RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM | |
| 51 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14), | |
| 52 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15), | |
| 53 | ||
| 54 | /* SOFTRST_CON04 */ | |
| 55 | RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM | |
| 56 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3), | |
| 57 | RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4), | |
| 58 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5), | |
| 59 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6), | |
| 60 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7), | |
| 61 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8), | |
| 62 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9), | |
| 63 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10), | |
| 64 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11), | |
| 65 | ||
| 66 | /* SOFTRST_CON05 */ | |
| 67 | RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0), | |
| 68 | RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7), | |
| 69 | RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8), | |
| 70 | RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14), | |
| 71 | RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15), | |
| 72 | ||
| 73 | /* SOFTRST_CON06 */ | |
| 74 | RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0), | |
| 75 | RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1), | |
| 76 | ||
| 77 | /* SOFTRST_CON07 */ | |
| 78 | RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), | |
| 79 | RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3), | |
| 80 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4), | |
| 81 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7), | |
| 82 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10), | |
| 83 | RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11), | |
| 84 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12), | |
| 85 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13), | |
| 86 | ||
| 87 | /* SOFTRST_CON08 */ | |
| 88 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0), | |
| 89 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3), | |
| 90 | RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4), | |
| 91 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14), | |
| 92 | ||
| 93 | /* SOFTRST_CON09 */ | |
| 94 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1), | |
| 95 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2), | |
| 96 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5), | |
| 97 | RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6), | |
| 98 | RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7), | |
| 99 | ||
| 100 | /* SOFTRST_CON10 */ | |
| 101 | RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1), | |
| 102 | RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2), | |
| 103 | RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3), | |
| 104 | RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4), | |
| 105 | RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5), | |
| 106 | RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6), | |
| 107 | RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7), | |
| 108 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8), | |
| 109 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9), | |
| 110 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10), | |
| 111 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11), | |
| 112 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12), | |
| 113 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13), | |
| 114 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14), | |
| 115 | RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15), | |
| 116 | ||
| 117 | /* SOFTRST_CON11 */ | |
| 118 | RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0), | |
| 119 | RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1), | |
| 120 | RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2), | |
| 121 | RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3), | |
| 122 | RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4), | |
| 123 | RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5), | |
| 124 | RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6), | |
| 125 | RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7), | |
| 126 | RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8), | |
| 127 | RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9), | |
| 128 | RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10), | |
| 129 | RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11), | |
| 130 | RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12), | |
| 131 | RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13), | |
| 132 | RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14), | |
| 133 | ||
| 134 | /* SOFTRST_CON12 */ | |
| 135 | RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0), | |
| 136 | RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1), | |
| 137 | RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2), | |
| 138 | RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3), | |
| 139 | RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4), | |
| 140 | RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5), | |
| 141 | RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6), | |
| 142 | RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7), | |
| 143 | RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8), | |
| 144 | RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9), | |
| 145 | RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10), | |
| 146 | RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13), | |
| 147 | ||
| 148 | /* SOFTRST_CON13 */ | |
| 149 | RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0), | |
| 150 | RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3), | |
| 151 | RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6), | |
| 152 | RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9), | |
| 153 | RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12), | |
| 154 | RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15), | |
| 155 | ||
| 156 | /* SOFTRST_CON14 */ | |
| 157 | RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2), | |
| 158 | RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5), | |
| 159 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6), | |
| 160 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7), | |
| 161 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8), | |
| 162 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9), | |
| 163 | RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10), | |
| 164 | RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11), | |
| 165 | RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12), | |
| 166 | RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13), | |
| 167 | RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14), | |
| 168 | RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15), | |
| 169 | ||
| 170 | /* SOFTRST_CON15 */ | |
| 171 | RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0), | |
| 172 | RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1), | |
| 173 | RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2), | |
| 174 | RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3), | |
| 175 | RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4), | |
| 176 | RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6), | |
| 177 | RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7), | |
| 178 | RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9), | |
| 179 | RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10), | |
| 180 | RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12), | |
| 181 | RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13), | |
| 182 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15), | |
| 183 | ||
| 184 | /* SOFTRST_CON16 */ | |
| 185 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0), | |
| 186 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1), | |
| 187 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2), | |
| 188 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3), | |
| 189 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4), | |
| 190 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5), | |
| 191 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6), | |
| 192 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7), | |
| 193 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8), | |
| 194 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9), | |
| 195 | RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10), | |
| 196 | RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11), | |
| 197 | RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12), | |
| 198 | RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13), | |
| 199 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14), | |
| 200 | RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15), | |
| 201 | ||
| 202 | /* SOFTRST_CON17 */ | |
| 203 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0), | |
| 204 | RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1), | |
| 205 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2), | |
| 206 | RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3), | |
| 207 | RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4), | |
| 208 | RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5), | |
| 209 | RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6), | |
| 210 | RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7), | |
| 211 | RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8), | |
| 212 | RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9), | |
| 213 | RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11), | |
| 214 | RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12), | |
| 215 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13), | |
| 216 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14), | |
| 217 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15), | |
| 218 | ||
| 219 | /* SOFTRST_CON18 */ | |
| 220 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0), | |
| 221 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1), | |
| 222 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2), | |
| 223 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3), | |
| 224 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4), | |
| 225 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5), | |
| 226 | RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6), | |
| 227 | RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9), | |
| 228 | RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10), | |
| 229 | RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11), | |
| 230 | ||
| 231 | /* SOFTRST_CON19 */ | |
| 232 | RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0), | |
| 233 | RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4), | |
| 234 | RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5), | |
| 235 | ||
| 236 | /* SOFTRST_CON20 */ | |
| 237 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0), | |
| 238 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1), | |
| 239 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2), | |
| 240 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3), | |
| 241 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4), | |
| 242 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5), | |
| 243 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6), | |
| 244 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7), | |
| 245 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8), | |
| 246 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9), | |
| 247 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10), | |
| 248 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11), | |
| 249 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12), | |
| 250 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13), | |
| 251 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14), | |
| 252 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15), | |
| 253 | ||
| 254 | /* SOFTRST_CON21 */ | |
| 255 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0), | |
| 256 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1), | |
| 257 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2), | |
| 258 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3), | |
| 259 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4), | |
| 260 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5), | |
| 261 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6), | |
| 262 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7), | |
| 263 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8), | |
| 264 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13), | |
| 265 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14), | |
| 266 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15), | |
| 267 | ||
| 268 | /* SOFTRST_CON22 */ | |
| 269 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0), | |
| 270 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1), | |
| 271 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2), | |
| 272 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3), | |
| 273 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4), | |
| 274 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5), | |
| 275 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6), | |
| 276 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7), | |
| 277 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8), | |
| 278 | ||
| 279 | /* SOFTRST_CON23 */ | |
| 280 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0), | |
| 281 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1), | |
| 282 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2), | |
| 283 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3), | |
| 284 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4), | |
| 285 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5), | |
| 286 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6), | |
| 287 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7), | |
| 288 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8), | |
| 289 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9), | |
| 290 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10), | |
| 291 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11), | |
| 292 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12), | |
| 293 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13), | |
| 294 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14), | |
| 295 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15), | |
| 296 | ||
| 297 | /* SOFTRST_CON24 */ | |
| 298 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0), | |
| 299 | RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1), | |
| 300 | RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2), | |
| 301 | RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3), | |
| 302 | RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4), | |
| 303 | RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5), | |
| 304 | RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6), | |
| 305 | RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7), | |
| 306 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8), | |
| 307 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13), | |
| 308 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14), | |
| 309 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15), | |
| 310 | ||
| 311 | /* SOFTRST_CON25 */ | |
| 312 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0), | |
| 313 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1), | |
| 314 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2), | |
| 315 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3), | |
| 316 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4), | |
| 317 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5), | |
| 318 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6), | |
| 319 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7), | |
| 320 | RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8), | |
| 321 | ||
| 322 | /* SOFTRST_CON26 */ | |
| 323 | RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3), | |
| 324 | RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4), | |
| 325 | RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6), | |
| 326 | RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8), | |
| 327 | ||
| 328 | /* SOFTRST_CON27 */ | |
| 329 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0), | |
| 330 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1), | |
| 331 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2), | |
| 332 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3), | |
| 333 | ||
| 334 | /* SOFTRST_CON28 */ | |
| 335 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0), | |
| 336 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1), | |
| 337 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2), | |
| 338 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3), | |
| 339 | ||
| 340 | /* SOFTRST_CON29 */ | |
| 341 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3), | |
| 342 | RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5), | |
| 343 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6), | |
| 344 | RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8), | |
| 345 | RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9), | |
| 346 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10), | |
| 347 | RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11), | |
| 348 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12), | |
| 349 | RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13), | |
| 350 | RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14), | |
| 351 | ||
| 352 | /* SOFTRST_CON30 */ | |
| 353 | RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0), | |
| 354 | RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2), | |
| 355 | RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3), | |
| 356 | RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4), | |
| 357 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6), | |
| 358 | RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7), | |
| 359 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8), | |
| 360 | RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9), | |
| 361 | ||
| 362 | /* SOFTRST_CON31 */ | |
| 363 | RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2), | |
| 364 | RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3), | |
| 365 | RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4), | |
| 366 | RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5), | |
| 367 | RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6), | |
| 368 | RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7), | |
| 369 | RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8), | |
| 370 | RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9), | |
| 371 | RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10), | |
| 372 | RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11), | |
| 373 | ||
| 374 | /* SOFTRST_CON32 */ | |
| 375 | RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1), | |
| 376 | RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2), | |
| 377 | RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5), | |
| 378 | RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8), | |
| 379 | RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9), | |
| 380 | RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10), | |
| 381 | RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11), | |
| 382 | RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12), | |
| 383 | RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13), | |
| 384 | RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14), | |
| 385 | RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15), | |
| 386 | ||
| 387 | /* SOFTRST_CON33 */ | |
| 388 | RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0), | |
| 389 | RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1), | |
| 390 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12), | |
| 391 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13), | |
| 392 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14), | |
| 393 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15), | |
| 394 | ||
| 395 | /* SOFTRST_CON34 */ | |
| 396 | RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0), | |
| 397 | RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6), | |
| 398 | RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7), | |
| 399 | RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8), | |
| 400 | RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9), | |
| 401 | ||
| 402 | /* SOFTRST_CON35 */ | |
| 403 | RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7), | |
| 404 | ||
| 405 | /* SOFTRST_CON37 */ | |
| 406 | RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4), | |
| 407 | RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5), | |
| 408 | RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6), | |
| 409 | RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7), | |
| 410 | RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8), | |
| 411 | RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9), | |
| 412 | RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10), | |
| 413 | RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11), | |
| 414 | RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12), | |
| 415 | RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13), | |
| 416 | RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14), | |
| 417 | RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15), | |
| 418 | ||
| 419 | /* SOFTRST_CON40 */ | |
| 420 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2), | |
| 421 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3), | |
| 422 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4), | |
| 423 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5), | |
| 424 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6), | |
| 425 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7), | |
| 426 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8), | |
| 427 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9), | |
| 428 | ||
| 429 | /* SOFTRST_CON41 */ | |
| 430 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2), | |
| 431 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3), | |
| 432 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4), | |
| 433 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5), | |
| 434 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6), | |
| 435 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7), | |
| 436 | RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8), | |
| 437 | ||
| 438 | /* SOFTRST_CON42 */ | |
| 439 | RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2), | |
| 440 | RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3), | |
| 441 | RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4), | |
| 442 | RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7), | |
| 443 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10), | |
| 444 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11), | |
| 445 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12), | |
| 446 | RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13), | |
| 447 | RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14), | |
| 448 | RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15), | |
| 449 | ||
| 450 | /* SOFTRST_CON43 */ | |
| 451 | RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0), | |
| 452 | RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1), | |
| 453 | RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2), | |
| 454 | ||
| 455 | /* SOFTRST_CON44 */ | |
| 456 | RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4), | |
| 457 | RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5), | |
| 458 | RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6), | |
| 459 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7), | |
| 460 | RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8), | |
| 461 | RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9), | |
| 462 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10), | |
| 463 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11), | |
| 464 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12), | |
| 465 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13), | |
| 466 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14), | |
| 467 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15), | |
| 468 | ||
| 469 | /* SOFTRST_CON45 */ | |
| 470 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0), | |
| 471 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1), | |
| 472 | RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2), | |
| 473 | RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3), | |
| 474 | RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4), | |
| 475 | RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5), | |
| 476 | RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6), | |
| 477 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7), | |
| 478 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8), | |
| 479 | RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9), | |
| 480 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10), | |
| 481 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11), | |
| 482 | RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12), | |
| 483 | ||
| 484 | /* SOFTRST_CON47 */ | |
| 485 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2), | |
| 486 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3), | |
| 487 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4), | |
| 488 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5), | |
| 489 | RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6), | |
| 490 | ||
| 491 | /* SOFTRST_CON48 */ | |
| 492 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2), | |
| 493 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3), | |
| 494 | RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4), | |
| 495 | RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5), | |
| 496 | RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6), | |
| 497 | ||
| 498 | /* SOFTRST_CON49 */ | |
| 499 | RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3), | |
| 500 | RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4), | |
| 501 | RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5), | |
| 502 | RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6), | |
| 503 | RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7), | |
| 504 | RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8), | |
| 505 | RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10), | |
| 506 | RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11), | |
| 507 | ||
| 508 | /* SOFTRST_CON50 */ | |
| 509 | RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0), | |
| 510 | RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3), | |
| 511 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4), | |
| 512 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5), | |
| 513 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6), | |
| 514 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7), | |
| 515 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8), | |
| 516 | RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9), | |
| 517 | ||
| 518 | /* SOFTRST_CON51 */ | |
| 519 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4), | |
| 520 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5), | |
| 521 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6), | |
| 522 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7), | |
| 523 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8), | |
| 524 | RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9), | |
| 525 | RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13), | |
| 526 | ||
| 527 | /* SOFTRST_CON52 */ | |
| 528 | RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4), | |
| 529 | RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5), | |
| 530 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6), | |
| 531 | RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7), | |
| 532 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8), | |
| 533 | RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9), | |
| 534 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13), | |
| 535 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14), | |
| 536 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15), | |
| 537 | ||
| 538 | /* SOFTRST_CON53 */ | |
| 539 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0), | |
| 540 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1), | |
| 541 | RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2), | |
| 542 | RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3), | |
| 543 | RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4), | |
| 544 | RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5), | |
| 545 | RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6), | |
| 546 | RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7), | |
| 547 | RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8), | |
| 548 | RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9), | |
| 549 | ||
| 550 | /* SOFTRST_CON55 */ | |
| 551 | RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5), | |
| 552 | RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6), | |
| 553 | RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7), | |
| 554 | RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8), | |
| 555 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9), | |
| 556 | RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10), | |
| 557 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11), | |
| 558 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12), | |
| 559 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13), | |
| 560 | RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15), | |
| 561 | ||
| 562 | /* SOFTRST_CON56 */ | |
| 563 | RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1), | |
| 564 | RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8), | |
| 565 | RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9), | |
| 566 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10), | |
| 567 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13), | |
| 568 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14), | |
| 569 | ||
| 570 | /* SOFTRST_CON57 */ | |
| 571 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1), | |
| 572 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2), | |
| 573 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6), | |
| 574 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7), | |
| 575 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11), | |
| 576 | ||
| 577 | /* SOFTRST_CON59 */ | |
| 578 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6), | |
| 579 | RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8), | |
| 580 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9), | |
| 581 | RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10), | |
| 582 | RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11), | |
| 583 | RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12), | |
| 584 | RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13), | |
| 585 | ||
| 586 | /* SOFTRST_CON60 */ | |
| 587 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0), | |
| 588 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3), | |
| 589 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4), | |
| 590 | RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5), | |
| 591 | RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6), | |
| 592 | RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8), | |
| 593 | RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10), | |
| 594 | RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11), | |
| 595 | ||
| 596 | /* SOFTRST_CON61 */ | |
| 597 | RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0), | |
| 598 | RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2), | |
| 599 | RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7), | |
| 600 | RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9), | |
| 601 | RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10), | |
| 602 | RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11), | |
| 603 | ||
| 604 | /* SOFTRST_CON62 */ | |
| 605 | RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0), | |
| 606 | RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1), | |
| 607 | RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3), | |
| 608 | RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4), | |
| 609 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8), | |
| 610 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12), | |
| 611 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15), | |
| 612 | ||
| 613 | /* SOFTRST_CON63 */ | |
| 614 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2), | |
| 615 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3), | |
| 616 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4), | |
| 617 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7), | |
| 618 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8), | |
| 619 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11), | |
| 620 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12), | |
| 621 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13), | |
| 622 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14), | |
| 623 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15), | |
| 624 | ||
| 625 | /* SOFTRST_CON64 */ | |
| 626 | RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0), | |
| 627 | RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1), | |
| 628 | RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12), | |
| 629 | RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13), | |
| 630 | RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14), | |
| 631 | RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15), | |
| 632 | ||
| 633 | /* SOFTRST_CON65 */ | |
| 634 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0), | |
| 635 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3), | |
| 636 | RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4), | |
| 637 | RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7), | |
| 638 | RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8), | |
| 639 | ||
| 640 | /* SOFTRST_CON66 */ | |
| 641 | RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4), | |
| 642 | RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5), | |
| 643 | RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8), | |
| 644 | RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9), | |
| 645 | RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10), | |
| 646 | RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11), | |
| 647 | RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12), | |
| 648 | RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14), | |
| 649 | RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15), | |
| 650 | ||
| 651 | /* SOFTRST_CON67 */ | |
| 652 | RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0), | |
| 653 | RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2), | |
| 654 | RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3), | |
| 655 | RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4), | |
| 656 | ||
| 657 | /* SOFTRST_CON68 */ | |
| 658 | RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1), | |
| 659 | RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2), | |
| 660 | RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4), | |
| 661 | RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5), | |
| 662 | ||
| 663 | /* SOFTRST_CON69 */ | |
| 664 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4), | |
| 665 | RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5), | |
| 666 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6), | |
| 667 | RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7), | |
| 668 | RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10), | |
| 669 | RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11), | |
| 670 | RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12), | |
| 671 | RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13), | |
| 672 | RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14), | |
| 673 | ||
| 674 | /* SOFTRST_CON70 */ | |
| 675 | RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0), | |
| 676 | RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1), | |
| 677 | RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2), | |
| 678 | RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3), | |
| 679 | RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5), | |
| 680 | RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6), | |
| 681 | RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7), | |
| 682 | RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8), | |
| 683 | RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9), | |
| 684 | RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10), | |
| 685 | RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11), | |
| 686 | RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12), | |
| 687 | ||
| 688 | /* SOFTRST_CON72 */ | |
| 689 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1), | |
| 690 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2), | |
| 691 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3), | |
| 692 | RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4), | |
| 693 | RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5), | |
| 694 | RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6), | |
| 695 | RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7), | |
| 696 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8), | |
| 697 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9), | |
| 698 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10), | |
| 699 | RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11), | |
| 700 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM | |
| 701 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM | |
| 702 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM | |
| 703 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM | |
| 704 | ||
| 705 | /* SOFTRST_CON73 */ | |
| 706 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM | |
| 707 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM | |
| 708 | RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM | |
| 709 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM | |
| 710 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM | |
| 711 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM | |
| 712 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM | |
| 713 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM | |
| 714 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM | |
| 715 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM | |
| 716 | RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM | |
| 717 | RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12), | |
| 718 | RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13), | |
| 719 | ||
| 720 | /* SOFTRST_CON74 */ | |
| 721 | RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1), | |
| 722 | RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3), | |
| 723 | ||
| 724 | /* SOFTRST_CON75 */ | |
| 725 | RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1), | |
| 726 | RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2), | |
| 727 | RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3), | |
| 728 | ||
| 729 | /* SOFTRST_CON76 */ | |
| 730 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2), | |
| 731 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3), | |
| 732 | RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4), | |
| 733 | RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5), | |
| 734 | RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6), | |
| 735 | ||
| 736 | /* SOFTRST_CON77 */ | |
| 737 | RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6), | |
| 738 | RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7), | |
| 739 | RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8), | |
| 740 | ||
| 741 | /* PHPTOPCRU_SOFTRST_CON00 */ | |
| 742 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1), | |
| 743 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2), | |
| 744 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3), | |
| 745 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4), | |
| 746 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5), | |
| 747 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6), | |
| 748 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7), | |
| 749 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8), | |
| 750 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9), | |
| 751 | RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10), | |
| 752 | ||
| 753 | /* PMU1CRU_SOFTRST_CON00 */ | |
| 754 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10), | |
| 755 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11), | |
| 756 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12), | |
| 757 | RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13), | |
| 758 | RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14), | |
| 759 | ||
| 760 | /* PMU1CRU_SOFTRST_CON01 */ | |
| 761 | RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1), | |
| 762 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2), | |
| 763 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4), | |
| 764 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5), | |
| 765 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6), | |
| 766 | RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7), | |
| 767 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8), | |
| 768 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10), | |
| 769 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11), | |
| 770 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12), | |
| 771 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13), | |
| 772 | ||
| 773 | /* PMU1CRU_SOFTRST_CON02 */ | |
| 774 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1), | |
| 775 | RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2), | |
| 776 | RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5), | |
| 777 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6), | |
| 778 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7), | |
| 779 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10), | |
| 780 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13), | |
| 781 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14), | |
| 782 | RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15), | |
| 783 | ||
| 784 | /* PMU1CRU_SOFTRST_CON03 */ | |
| 785 | RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0), | |
| 786 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11), | |
| 787 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12), | |
| 788 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13), | |
| 789 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15), | |
| 790 | ||
| 791 | /* PMU1CRU_SOFTRST_CON04 */ | |
| 792 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0), | |
| 793 | RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1), | |
| 794 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3), | |
| 795 | RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4), | |
| 796 | RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5), | |
| 797 | RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6), | |
| 798 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7), | |
| 799 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8), | |
| 800 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9), | |
| 801 | RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10), | |
| 802 | ||
| 803 | /* PMU1CRU_SOFTRST_CON05 */ | |
| 804 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3), | |
| 805 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4), | |
| 806 | RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5), | |
| 807 | RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6), | |
| 808 | ||
| 809 | /* SECURECRU_SOFTRST_CON00 */ | |
| 810 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10), | |
| 811 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11), | |
| 812 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12), | |
| 813 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13), | |
| 814 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14), | |
| 815 | RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15), | |
| 816 | ||
| 817 | /* SECURECRU_SOFTRST_CON01 */ | |
| 818 | RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0), | |
| 819 | RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1), | |
| 820 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2), | |
| 821 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3), | |
| 822 | RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9), | |
| 823 | RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10), | |
| 824 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11), | |
| 825 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12), | |
| 826 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13), | |
| 827 | RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14), | |
| 828 | RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15), | |
| 829 | ||
| 830 | /* SECURECRU_SOFTRST_CON02 */ | |
| 831 | RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0), | |
| 832 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1), | |
| 833 | RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2), | |
| 834 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3), | |
| 835 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5), | |
| 836 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14), | |
| 837 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15), | |
| 838 | ||
| 839 | /* SECURECRU_SOFTRST_CON03 */ | |
| 840 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0), | |
| 841 | RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1), | |
| 842 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2), | |
| 843 | RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3), | |
| 844 | RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4), | |
| 845 | RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5), | |
| 846 | RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6), | |
| 847 | }; | |
| 848 | ||
| 849 | int rk3588_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number) | |
| 850 | { | |
| 851 | return rockchip_reset_bind_lut(pdev, rk3588_register_offset, | |
| 852 | reg_offset, reg_number); | |
| 853 | } |