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Commit | Line | Data |
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3a581af2 TR |
1 | config FSL_TRUST_ARCH_v1 |
2 | bool | |
3 | ||
540b73a7 TR |
4 | config NXP_ESBC |
5 | bool "NXP ESBC (secure boot) functionality" | |
3a581af2 TR |
6 | select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \ |
7 | ARCH_P5040 || ARCH_P2041 | |
540b73a7 TR |
8 | help |
9 | Enable Freescale Secure Boot feature. Normally selected by defconfig. | |
10 | If unsure, do not change. | |
11 | ||
12 | menu "Chain of trust / secure boot options" | |
5536c3c9 | 13 | depends on !FIT_SIGNATURE && NXP_ESBC |
540b73a7 TR |
14 | |
15 | config CHAIN_OF_TRUST | |
28522678 | 16 | select FSL_CAAM |
66e54716 | 17 | select ARCH_MISC_INIT |
3a581af2 | 18 | select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT |
c9f85187 | 19 | select FSL_SEC_MON |
0680f1b1 | 20 | select SPL_BOARD_INIT if (ARM && SPL) |
07212096 | 21 | select SPL_HASH if (ARM && SPL) |
089df18b TR |
22 | select SHA_HW_ACCEL |
23 | select SHA_PROG_HW_ACCEL | |
2be29653 | 24 | select ENV_IS_NOWHERE |
f6c1f917 | 25 | select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT |
86c773fe SG |
26 | select CMD_EXT4 if ARM |
27 | select CMD_EXT4_WRITE if ARM | |
540b73a7 TR |
28 | imply CMD_BLOB |
29 | imply CMD_HASH if ARM | |
30 | def_bool y | |
ea7971f7 SG |
31 | |
32 | config CMD_ESBC_VALIDATE | |
33 | bool "Enable the 'esbc_validate' and 'esbc_halt' commands" | |
93145335 | 34 | default y |
ea7971f7 SG |
35 | help |
36 | This option enables two commands used for secure booting: | |
37 | ||
38 | esbc_validate - validate signature using RSA verification | |
39 | esbc_halt - put the core in spin loop (Secure Boot Only) | |
6f2d0a50 | 40 | |
2b2817b5 TR |
41 | config ESBC_HDR_LS |
42 | bool | |
43 | ||
44 | config ESBC_ADDR_64BIT | |
45 | def_bool y | |
46 | depends on ESBC_HDR_LS && FSL_LAYERSCAPE | |
47 | help | |
48 | For Layerscape based platforms, ESBC image Address in Header is 64bit. | |
49 | ||
3a581af2 TR |
50 | config FSL_ISBC_KEY_EXT |
51 | bool | |
52 | help | |
53 | The key used for verification of next level images is picked up from | |
54 | an Extension Table which has been verified by the ISBC (Internal | |
55 | Secure boot Code) in boot ROM of the SoC. The feature is only | |
56 | applicable in case of NOR boot and is not applicable in case of | |
57 | RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available | |
58 | for all device if IE Table is copied to XIP memory Also, for | |
59 | Layerscape, ISBC doesn't verify this table. | |
60 | ||
601483ff TR |
61 | config SYS_FSL_SFP_BE |
62 | def_bool y | |
540b73a7 | 63 | depends on PPC || FSL_LSCH2 || ARCH_LS1021A |
601483ff TR |
64 | |
65 | config SYS_FSL_SFP_LE | |
66 | def_bool y | |
540b73a7 | 67 | depends on !SYS_FSL_SFP_BE |
601483ff TR |
68 | |
69 | choice | |
70 | prompt "SFP IP revision" | |
601483ff TR |
71 | default SYS_FSL_SFP_VER_3_0 if PPC |
72 | default SYS_FSL_SFP_VER_3_4 | |
73 | ||
74 | config SYS_FSL_SFP_VER_3_0 | |
75 | bool "SFP version 3.0" | |
76 | ||
77 | config SYS_FSL_SFP_VER_3_2 | |
78 | bool "SFP version 3.2" | |
79 | ||
80 | config SYS_FSL_SFP_VER_3_4 | |
81 | bool "SFP version 3.4" | |
82 | ||
83 | endchoice | |
84 | ||
5aad0a14 TR |
85 | config SPL_UBOOT_KEY_HASH |
86 | string "Non-SRK key hash for U-Boot public/private key pair" | |
87 | depends on SPL | |
88 | default "" | |
89 | help | |
90 | Set the key hash for U-Boot here if public/private key pair used to | |
91 | sign U-boot are different from the SRK hash put in the fuse. Example | |
92 | of a key hash is | |
93 | 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. | |
94 | Otherwise leave this empty. | |
95 | ||
f4cd75e9 TR |
96 | if PPC |
97 | ||
98 | config BOOTSCRIPT_COPY_RAM | |
99 | bool "Secure boot copies boot script to RAM" | |
100 | help | |
101 | On systems that support chain of trust booting, a number of addresses | |
102 | are required to set variables that are used in the copying and then | |
103 | verification of different parts of the system. If enabled, the subsequent | |
104 | options are for what location to use in each step. | |
105 | ||
106 | config BS_ADDR_DEVICE | |
107 | hex "Address in RAM for bs_device" | |
108 | depends on BOOTSCRIPT_COPY_RAM | |
109 | ||
110 | config BS_SIZE | |
111 | hex "The size of bs_size which is the amount read from bs_device" | |
112 | depends on BOOTSCRIPT_COPY_RAM | |
113 | ||
114 | config BS_ADDR_RAM | |
115 | hex "Address in RAM for bs_ram" | |
116 | depends on BOOTSCRIPT_COPY_RAM | |
117 | ||
118 | config BS_HDR_ADDR_DEVICE | |
119 | hex "Address in RAM for bs_hdr_device" | |
120 | depends on BOOTSCRIPT_COPY_RAM | |
121 | ||
122 | config BS_HDR_SIZE | |
123 | hex "The size of bs_hdr_size which is the amount read from bs_hdr_device" | |
124 | depends on BOOTSCRIPT_COPY_RAM | |
125 | ||
126 | config BS_HDR_ADDR_RAM | |
127 | hex "Address in RAM for bs_hdr_ram" | |
128 | depends on BOOTSCRIPT_COPY_RAM | |
129 | ||
130 | config BOOTSCRIPT_HDR_ADDR | |
131 | hex "CONFIG_BOOTSCRIPT_HDR_ADDR" | |
132 | default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM | |
133 | ||
134 | endif | |
135 | ||
601483ff TR |
136 | config SYS_FSL_SRK_LE |
137 | def_bool y | |
540b73a7 | 138 | depends on ARM |
601483ff TR |
139 | |
140 | config KEY_REVOCATION | |
141 | def_bool y | |
540b73a7 TR |
142 | |
143 | endmenu | |
144 | ||
145 | comment "Other functionality shared between NXP SoCs" | |
601483ff | 146 | |
28f9c312 TR |
147 | config DEEP_SLEEP |
148 | bool "Enable SoC deep sleep feature" | |
93145335 TR |
149 | depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A |
150 | default y | |
28f9c312 TR |
151 | help |
152 | Indicates this SoC supports deep sleep feature. If deep sleep is | |
153 | supported, core will start to execute uboot when wakes up. | |
154 | ||
a552ffc9 TR |
155 | config LAYERSCAPE_NS_ACCESS |
156 | bool "Layerscape non-secure access support" | |
157 | depends on ARCH_LS1021A || FSL_LSCH2 | |
158 | ||
3dc2987f TR |
159 | config PCIE1 |
160 | bool "PCIe controller #1" | |
161 | depends on LAYERSCAPE_NS_ACCESS || PPC | |
162 | ||
163 | config PCIE2 | |
164 | bool "PCIe controller #2" | |
165 | depends on LAYERSCAPE_NS_ACCESS || PPC | |
166 | ||
167 | config PCIE3 | |
168 | bool "PCIe controller #3" | |
169 | depends on LAYERSCAPE_NS_ACCESS || PPC | |
170 | ||
171 | config PCIE4 | |
172 | bool "PCIe controller #4" | |
173 | depends on LAYERSCAPE_NS_ACCESS || PPC | |
174 | ||
15347d2d SC |
175 | config FSL_USE_PCA9547_MUX |
176 | bool "Enable PCA9547 I2C Mux on Freescale boards" | |
93145335 | 177 | depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 |
15347d2d SC |
178 | help |
179 | This option enables the PCA9547 I2C mux on Freescale boards. | |
180 | ||
b5ee48c0 | 181 | config VID |
b5ee48c0 | 182 | bool "Enable Freescale VID" |
93145335 | 183 | depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C) |
b5ee48c0 SC |
184 | help |
185 | This option enables setting core voltage based on individual | |
186 | values saved in SoC fuses. | |
187 | ||
d06e4b7e TR |
188 | config SPL_VID |
189 | bool "Enable Freescale VID in SPL" | |
93145335 | 190 | depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C) |
d06e4b7e TR |
191 | help |
192 | This option enables setting core voltage based on individual | |
193 | values saved in SoC fuses, in SPL. | |
194 | ||
195 | if VID || SPL_VID | |
196 | ||
197 | config VID_FLS_ENV | |
198 | string "Environment variable for overriding VDD" | |
199 | help | |
200 | This option allows for specifying the environment variable | |
201 | to check to override VDD information. | |
202 | ||
203 | config VOL_MONITOR_INA220 | |
204 | bool "Enable the INA220 voltage monitor read" | |
205 | help | |
206 | This option enables INA220 voltage monitor read | |
207 | functionality. It is used by the common VID driver. | |
208 | ||
209 | config VOL_MONITOR_IR36021_READ | |
210 | bool "Enable the IR36021 voltage monitor read" | |
211 | help | |
212 | This option enables IR36021 voltage monitor read | |
213 | functionality. It is used by the common VID driver. | |
214 | ||
215 | config VOL_MONITOR_IR36021_SET | |
216 | bool "Enable the IR36021 voltage monitor set" | |
217 | help | |
218 | This option enables IR36021 voltage monitor set | |
219 | functionality. It is used by the common VID driver. | |
220 | ||
6f2d0a50 | 221 | config VOL_MONITOR_LTC3882_READ |
6f2d0a50 | 222 | bool "Enable the LTC3882 voltage monitor read" |
6f2d0a50 RB |
223 | help |
224 | This option enables LTC3882 voltage monitor read | |
b5ee48c0 | 225 | functionality. It is used by the common VID driver. |
6f2d0a50 RB |
226 | |
227 | config VOL_MONITOR_LTC3882_SET | |
6f2d0a50 | 228 | bool "Enable the LTC3882 voltage monitor set" |
6f2d0a50 RB |
229 | help |
230 | This option enables LTC3882 voltage monitor set | |
b5ee48c0 SC |
231 | functionality. It is used by the common VID driver. |
232 | ||
233 | config VOL_MONITOR_ISL68233_READ | |
b5ee48c0 SC |
234 | bool "Enable the ISL68233 voltage monitor read" |
235 | help | |
236 | This option enables ISL68233 voltage monitor read | |
237 | functionality. It is used by the common VID driver. | |
238 | ||
239 | config VOL_MONITOR_ISL68233_SET | |
b5ee48c0 SC |
240 | bool "Enable the ISL68233 voltage monitor set" |
241 | help | |
242 | This option enables ISL68233 voltage monitor set | |
243 | functionality. It is used by the common VID driver. | |
d06e4b7e TR |
244 | |
245 | endif | |
d43cd486 | 246 | |
1de46d91 TR |
247 | config SYS_FSL_NUM_CC_PLLS |
248 | int "Number of clock control PLLs" | |
249 | depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A | |
250 | default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2 | |
251 | default 6 if FSL_LSCH3 || MPC85xx | |
252 | ||
923a8555 TR |
253 | config SYS_FSL_ESDHC_BE |
254 | bool | |
255 | ||
256 | config SYS_FSL_IFC_BE | |
257 | bool | |
258 | ||
d43cd486 TR |
259 | config FSL_QIXIS |
260 | bool "Enable QIXIS support" | |
93145335 | 261 | depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 |
d43cd486 TR |
262 | |
263 | config QIXIS_I2C_ACCESS | |
264 | bool "Access to QIXIS is over i2c" | |
265 | depends on FSL_QIXIS | |
266 | default y | |
5cc1d921 TR |
267 | |
268 | config HAS_FSL_DR_USB | |
269 | def_bool y | |
270 | depends on USB_EHCI_HCD && PPC | |
2db82bf2 TR |
271 | |
272 | config SYS_DPAA_FMAN | |
273 | bool |