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c7de829c WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * | |
26 | * Configuration settings for the AmigaOneG3SE board. | |
27 | * | |
28 | */ | |
29 | ||
30 | /* ------------------------------------------------------------------------- */ | |
31 | ||
32 | /* | |
33 | * board/config.h - configuration options, board specific | |
34 | */ | |
35 | ||
36 | #ifndef __CONFIG_H | |
37 | #define __CONFIG_H | |
38 | ||
39 | /* | |
40 | * High Level Configuration Options | |
41 | * (easy to change) | |
42 | */ | |
43 | ||
44 | #define CONFIG_AMIGAONEG3SE 1 | |
45 | ||
c837dcb1 | 46 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
c7de829c WD |
47 | #define CONFIG_MISC_INIT_R 1 |
48 | ||
49 | #define CONFIG_VERY_BIG_RAM 1 | |
50 | ||
51 | #define CONFIG_CONS_INDEX 1 | |
52 | #define CONFIG_BAUDRATE 9600 | |
53 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
54 | ||
55 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks passed to Linux in Hz */ | |
56 | ||
57 | #define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096" | |
58 | ||
5d2ebe1b JL |
59 | /* |
60 | * BOOTP options | |
61 | */ | |
62 | #define CONFIG_BOOTP_SUBNETMASK | |
63 | #define CONFIG_BOOTP_GATEWAY | |
64 | #define CONFIG_BOOTP_HOSTNAME | |
65 | #define CONFIG_BOOTP_BOOTPATH | |
66 | #define CONFIG_BOOTP_BOOTFILESIZE | |
67 | ||
c7de829c WD |
68 | |
69 | #define CONFIG_MAC_PARTITION | |
70 | #define CONFIG_DOS_PARTITION | |
71 | #define CONFIG_AMIGA_PARTITION | |
72 | ||
498ff9a2 JL |
73 | |
74 | /* | |
75 | * Command line configuration. | |
76 | */ | |
77 | #include <config_cmd_default.h> | |
78 | ||
79 | #define CONFIG_CMD_ASKENV | |
80 | #define CONFIG_CMD_BSP | |
81 | #define CONFIG_CMD_DATE | |
82 | #define CONFIG_CMD_DHCP | |
83 | #define CONFIG_CMD_ELF | |
84 | #define CONFIG_CMD_NET | |
85 | #define CONFIG_CMD_IDE | |
86 | #define CONFIG_CMD_FDC | |
87 | #define CONFIG_CMD_CACHE | |
88 | #define CONFIG_CMD_CONSOLE| | |
89 | #define CONFIG_CMD_USB | |
90 | #define CONFIG_CMD_BSP | |
91 | #define CONFIG_CMD_PCI | |
92 | ||
c7de829c WD |
93 | |
94 | #define CONFIG_PCI 1 | |
95 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ | |
96 | #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ | |
97 | ||
c7de829c WD |
98 | /* |
99 | * Miscellaneous configurable options | |
100 | */ | |
101 | #define CFG_LONGHELP /* undef to save memory */ | |
7c7a23bd | 102 | #define CFG_PROMPT "] " /* Monitor Command Prompt */ |
c7de829c WD |
103 | |
104 | #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ | |
105 | /* #undef CFG_HUSH_PARSER */ | |
106 | #ifdef CFG_HUSH_PARSER | |
107 | #define CFG_PROMPT_HUSH_PS2 "> " | |
108 | #endif | |
109 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
110 | ||
111 | /* Print Buffer Size | |
112 | */ | |
113 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
114 | ||
115 | #define CFG_MAXARGS 64 /* max number of command args */ | |
116 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
117 | #define CFG_LOAD_ADDR 0x00500000 /* Default load address */ | |
118 | ||
119 | /*----------------------------------------------------------------------- | |
120 | * Start addresses for the final memory configuration | |
121 | * (Set up by the startup code) | |
122 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
123 | */ | |
124 | #define CFG_SDRAM_BASE 0x00000000 | |
125 | #define CFG_FLASH_BASE 0xFFF00000 | |
126 | #define CFG_FLASH_MAX_SIZE 0x00080000 | |
127 | /* Maximum amount of RAM. | |
128 | */ | |
129 | #define CFG_MAX_RAM_SIZE 0x80000000 /* 2G */ | |
130 | ||
131 | #define CFG_RESET_ADDRESS 0xFFF00100 | |
132 | ||
133 | #define CFG_MONITOR_BASE TEXT_BASE | |
134 | ||
135 | #define CFG_MONITOR_LEN (768 << 10) /* Reserve 512 kB for Monitor */ | |
136 | #define CFG_MALLOC_LEN (2500 << 10) /* Reserve 128 kB for malloc() */ | |
137 | ||
138 | #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \ | |
139 | CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE | |
140 | #define CFG_RAMBOOT | |
141 | #else | |
142 | #undef CFG_RAMBOOT | |
143 | #endif | |
144 | ||
145 | #define CFG_MEMTEST_START 0x00004000 /* memtest works on */ | |
146 | #define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ | |
147 | ||
148 | /*----------------------------------------------------------------------- | |
149 | * Definitions for initial stack pointer and data area | |
150 | */ | |
151 | ||
152 | /* Size in bytes reserved for initial data | |
153 | */ | |
7c7a23bd | 154 | /* HJF: used to be 0x400000 */ |
8bde7f77 | 155 | #define CFG_INIT_RAM_ADDR 0x40000000 |
c7de829c WD |
156 | #define CFG_INIT_RAM_END 0x8000 |
157 | #define CFG_GBL_DATA_SIZE 128 | |
158 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
159 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
160 | ||
161 | #define CFG_INIT_RAM_LOCK | |
162 | ||
163 | /* | |
164 | * Temporary buffer for serial data until the real serial driver | |
165 | * is initialised (memtest will destroy this buffer) | |
166 | */ | |
167 | #define CFG_SCONSOLE_ADDR CFG_INIT_RAM_ADDR | |
168 | #define CFG_SCONSOLE_SIZE 0x0002000 | |
169 | ||
170 | /* SDRAM 0 - 256MB | |
171 | */ | |
172 | ||
7c7a23bd | 173 | /*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
c7de829c WD |
174 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP) |
175 | #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
7c7a23bd | 176 | #define CFG_DBAT0U CFG_IBAT0U*/ |
c7de829c | 177 | |
7c7a23bd WD |
178 | #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
179 | #define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
180 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
181 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
182 | /* PCI Range | |
c7de829c | 183 | */ |
7c7a23bd WD |
184 | #define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
185 | #define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
186 | #define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT) | |
187 | #define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
188 | /* HJF: | |
8bde7f77 | 189 | #define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) |
c7de829c | 190 | #define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP) |
8bde7f77 | 191 | #define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) |
c7de829c | 192 | #define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP) |
7c7a23bd | 193 | */ |
c7de829c WD |
194 | |
195 | /* Init RAM in the CPU DCache (no backing memory) | |
196 | */ | |
197 | #define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
198 | #define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
7c7a23bd | 199 | /* This used to be commented out */ |
8bde7f77 | 200 | #define CFG_IBAT2L CFG_DBAT2L |
7c7a23bd | 201 | /* This here too */ |
8bde7f77 | 202 | #define CFG_IBAT2U CFG_DBAT2U |
7c7a23bd | 203 | |
c7de829c WD |
204 | |
205 | /* I/O and PCI memory at 0xf0000000 | |
206 | */ | |
207 | #define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
208 | #define CFG_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
209 | ||
210 | #define CFG_IBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT) | |
211 | #define CFG_IBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
212 | ||
213 | /* | |
214 | * Low Level Configuration Settings | |
215 | * (address mappings, register initial values, etc.) | |
216 | */ | |
217 | #define CFG_HZ 1000 | |
218 | #define CFG_BUS_HZ 133000000 /* bus speed - 100 mhz */ | |
219 | #define CFG_CPU_CLK 133000000 | |
220 | #define CFG_BUS_CLK 133000000 | |
221 | ||
222 | /* | |
223 | * For booting Linux, the board info and command line data | |
224 | * have to be in the first 8 MB of memory, since this is | |
225 | * the maximum mapped by the Linux kernel during initialization. | |
226 | */ | |
227 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
228 | ||
229 | /*----------------------------------------------------------------------- | |
230 | * FLASH organization | |
231 | */ | |
232 | #define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */ | |
233 | #define CFG_MAX_FLASH_SECT 8 /* Max number of sectors in one bank */ | |
234 | ||
235 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
236 | #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ | |
237 | ||
238 | /* | |
239 | * Environment is stored in NVRAM. | |
240 | */ | |
241 | #define CFG_ENV_IS_IN_NVRAM 1 | |
242 | #define CFG_ENV_ADDR 0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to | |
243 | * protect softex's settings for now. | |
244 | * Original 768 bytes where not enough. | |
245 | */ | |
246 | #define CFG_ENV_SIZE 0x8000 /* Size of the Environment. See comment above */ | |
247 | ||
248 | #define CFG_CONSOLE_IS_IN_ENV 1 /* stdin/stdout/stderr are in environment */ | |
249 | #define CFG_CONSOLE_OVERWRITE_ROUTINE 1 | |
250 | #define CONFIG_ENV_OVERWRITE 1 | |
251 | ||
252 | /*----------------------------------------------------------------------- | |
253 | * Cache Configuration | |
254 | */ | |
255 | #define CFG_CACHELINE_SIZE 32 | |
498ff9a2 | 256 | #if defined(CONFIG_CMD_KGDB) |
c7de829c WD |
257 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
258 | #endif | |
259 | ||
260 | /* | |
261 | * L2 cache | |
262 | */ | |
263 | #define CFG_L2 | |
264 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ | |
265 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) | |
266 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
267 | ||
268 | /* | |
269 | * Internal Definitions | |
270 | * | |
271 | * Boot Flags | |
272 | */ | |
273 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
274 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
275 | ||
276 | ||
277 | /*----------------------------------------------------------------------- | |
278 | * IDE ATAPI Configuration | |
279 | */ | |
280 | ||
281 | #define CONFIG_ATAPI 1 | |
282 | #define CFG_IDE_MAXBUS 2 | |
283 | #define CFG_IDE_MAXDEVICE 4 | |
284 | #define CONFIG_ISO_PARTITION 1 | |
285 | ||
286 | #define CFG_ATA_BASE_ADDR 0xFE000000 /* was: via_get_base_addr() */ | |
287 | #define CFG_ATA_IDE0_OFFSET 0x1F0 | |
288 | #define CFG_ATA_IDE1_OFFSET 0x170 | |
289 | ||
290 | #define CFG_ATA_REG_OFFSET 0 | |
291 | #define CFG_ATA_DATA_OFFSET 0 | |
292 | #define CFG_ATA_ALT_OFFSET 0x0200 | |
293 | ||
294 | /*----------------------------------------------------------------------- | |
295 | * Disk-On-Chip configuration | |
296 | */ | |
297 | ||
298 | #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
299 | ||
300 | #define CFG_DOC_SUPPORT_2000 | |
301 | #undef CFG_DOC_SUPPORT_MILLENNIUM | |
302 | ||
303 | /*----------------------------------------------------------------------- | |
304 | RTC | |
305 | */ | |
306 | #define CONFIG_RTC_MC146818 | |
307 | ||
308 | /*----------------------------------------------------------------------- | |
309 | * NS16550 Configuration | |
310 | */ | |
311 | ||
312 | #define CFG_NS16550 | |
313 | ||
314 | #define CFG_NS16550_COM1 0xFE0003F8 | |
315 | #define CFG_NS16550_COM2 0xFE0002F8 | |
316 | ||
317 | #define CFG_NS16550_REG_SIZE 1 | |
318 | ||
319 | /* base address for ISA I/O | |
320 | */ | |
321 | #define CFG_ISA_IO_BASE_ADDRESS 0xFE000000 | |
322 | ||
323 | /* ISA Interrupt stuff (taken from JWL) */ | |
324 | ||
325 | #define ISA_INT1_OCW1 0x21 | |
326 | #define ISA_INT2_OCW1 0xA1 | |
327 | #define ISA_INT1_OCW2 0x20 | |
328 | #define ISA_INT2_OCW2 0xA0 | |
329 | #define ISA_INT1_OCW3 0x20 | |
330 | #define ISA_INT2_OCW3 0xA0 | |
331 | ||
332 | #define ISA_INT1_ICW1 0x20 | |
333 | #define ISA_INT2_ICW1 0xA0 | |
334 | #define ISA_INT1_ICW2 0x21 | |
335 | #define ISA_INT2_ICW2 0xA1 | |
336 | #define ISA_INT1_ICW3 0x21 | |
337 | #define ISA_INT2_ICW3 0xA1 | |
338 | #define ISA_INT1_ICW4 0x21 | |
339 | #define ISA_INT2_ICW4 0xA1 | |
340 | ||
341 | ||
342 | /* | |
343 | * misc | |
344 | */ | |
345 | ||
346 | #define CONFIG_NET_MULTI | |
347 | #define CFG_BOARD_ASM_INIT | |
348 | #define CONFIG_LAST_STAGE_INIT | |
349 | ||
350 | /* #define CONFIG_ETHADDR 00:09:D2:10:00:76 */ | |
351 | /* #define CONFIG_IPADDR 192.168.0.2 */ | |
352 | /* #define CONFIG_NETMASK 255.255.255.240 */ | |
353 | /* #define CONFIG_GATEWAYIP 192.168.0.3 */ | |
354 | ||
355 | #define CONFIG_3COM | |
356 | /* #define CONFIG_BOOTP_RANDOM_DELAY */ | |
c7de829c WD |
357 | |
358 | /* | |
359 | * USB configuration | |
360 | */ | |
361 | #define CONFIG_USB_UHCI 1 | |
362 | #define CONFIG_USB_STORAGE 1 | |
363 | #define CONFIG_USB_KEYBOARD 1 | |
364 | #define CFG_DEVICE_DEREGISTER 1 /* needed by CONFIG_USB_KEYBOARD */ | |
365 | ||
366 | /* | |
367 | * Autoboot stuff | |
368 | */ | |
369 | #define CONFIG_BOOTDELAY 5 /* Boot automatically after five seconds */ | |
370 | #define CONFIG_PREBOOT "" | |
371 | #define CONFIG_BOOTCOMMAND "fdcboot; diskboot" | |
372 | #define CONFIG_MENUPROMPT "Press any key to interrupt autoboot: %2d " | |
373 | #define CONFIG_MENUKEY ' ' | |
374 | #define CONFIG_MENUCOMMAND "menu" | |
375 | /* #define CONFIG_AUTOBOOT_KEYED */ | |
376 | ||
377 | /* | |
378 | * Extra ENV stuff | |
379 | */ | |
380 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
381 | "stdout=vga\0" \ | |
382 | "stdin=ps2kbd\0" \ | |
383 | "ide_doreset=on\0" \ | |
384 | "ide_maxbus=2\0" \ | |
385 | "ide_cd_timeout=30\0" \ | |
386 | "menucmd=menu\0" \ | |
387 | "pci_irqa=9\0" \ | |
388 | "pci_irqa_select=edge\0" \ | |
389 | "pci_irqb=10\0" \ | |
390 | "pci_irqb_select=edge\0" \ | |
391 | "pci_irqc=11\0" \ | |
392 | "pci_irqc_select=edge\0" \ | |
7c7a23bd | 393 | "pci_irqd=7\0" \ |
c7de829c WD |
394 | "pci_irqd_select=edge\0" |
395 | ||
396 | ||
397 | /* #define CONFIG_MII 1 */ | |
398 | /* #define CONFIG_BITBANGMII 1 */ | |
399 | ||
400 | ||
401 | #endif /* __CONFIG_H */ |