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* Patch by Dave Ellis, 22 May 2003:
[J-u-boot.git] / board / fads / fads.c
CommitLineData
fe8c2806
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <config.h>
26#include <mpc8xx.h>
27#include "fads.h"
28
29/* ------------------------------------------------------------------------- */
30
31#define _NOT_USED_ 0xFFFFFFFF
32
33#if defined(CONFIG_DRAM_50MHZ)
34/* 50MHz tables */
35const uint dram_60ns[] =
36{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
37 0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff,
38 0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
39 0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
40 0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
41 0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff,
42 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
43 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
44 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
45 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
46 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
47 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
48 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
49 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
50 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
51 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
52
53const uint dram_70ns[] =
54{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
55 0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff,
56 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
57 0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
58 0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
59 0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff,
60 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
61 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
62 0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
63 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
64 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
65 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
66 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
67 0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff,
68 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
69 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
70
71const uint edo_60ns[] =
72{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
73 0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff,
74 0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
75 0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
76 0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
77 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
78 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
79 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
80 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
81 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
82 0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
83 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
84 0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
85 0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
86 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
87 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
88
89const uint edo_70ns[] =
90{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
91 0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff,
92 0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
93 0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
94 0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
95 0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
96 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
97 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
98 0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
99 0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
100 0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff,
101 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
102 0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
103 0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff,
104 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
105 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
106
107#elif defined(CONFIG_DRAM_25MHZ)
108
109/* 25MHz tables */
110
111const uint dram_60ns[] =
112{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff,
113 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
114 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
115 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
116 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
117 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
118 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
119 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
120 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
121 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
122 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
123 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
124 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
125 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
126 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
127 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
128
129const uint dram_70ns[] =
130{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
131 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
132 0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
133 0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
134 0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
135 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
136 0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
137 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
138 0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
139 0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
140 0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
141 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
142 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
143 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
144 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
145 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
146
147const uint edo_60ns[] =
148{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
149 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
150 0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
151 0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff,
152 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
153 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
154 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
155 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
156 0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
157 0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff,
158 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
159 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
160 0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
161 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
162 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
163 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
164
165const uint edo_70ns[] =
166{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
167 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
168 0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
169 0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
170 0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
171 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
172 0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
173 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
174 0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
175 0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
176 0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff,
177 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
178 0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
179 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
180 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
181 0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
182
183
184#else
185#error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
186#endif
187
188/* ------------------------------------------------------------------------- */
189
190
191/*
192 * Check Board Identity:
193 */
194
195int checkboard (void)
196{
197 uint k;
198
199 puts ("Board: ");
200
201#ifdef CONFIG_FADS
202 k = (*((uint *)BCSR3) >> 24) & 0x3f;
203
204 switch(k) {
205 case 0x03 :
206 case 0x20 :
207 case 0x21 :
208 case 0x22 :
209 case 0x23 :
210 case 0x24 :
5d232d0e 211 case 0x2a :
fe8c2806
WD		 212 case 0x3f :
213 puts ("FADS");
214 break;
215
216 default :
217 printf("unknown board (0x%02x)\n", k);
218 return -1;
219 }
220
221 printf(" with db ");
222
223 switch(k) {
224 case 0x03 :
225 puts ("MPC823");
226 break;
227 case 0x20 :
228 puts ("MPC801");
229 break;
230 case 0x21 :
231 puts ("MPC850");
232 break;
233 case 0x22 :
234 puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
235 break;
236 case 0x23 :
237 puts ("MPC860SAR");
238 break;
239 case 0x24 :
240 puts ("MPC860T");
241 break;
242 case 0x3f :
243 puts ("MPC850SAR");
244 break;
245 }
246
247 printf(" rev ");
248
249 k = (((*((uint *)BCSR3) >> 23) & 1) << 3)
250 | (((*((uint *)BCSR3) >> 19) & 1) << 2)
251 | (((*((uint *)BCSR3) >> 16) & 3));
252
253 switch(k) {
254 case 0x01 :
255 puts ("ENG or PILOT\n");
256 break;
257
258 default:
259 printf("unknown (0x%x)\n", k);
260 return -1;
261 }
262
263 return 0;
264#endif /* CONFIG_FADS */
265
266#ifdef CONFIG_ADS
267 printf("ADS rev ");
268
269 k = (((*((uint *)BCSR3) >> 23) & 1) << 3)
270 | (((*((uint *)BCSR3) >> 19) & 1) << 2)
271 | (((*((uint *)BCSR3) >> 16) & 3));
272
273 switch(k) {
274 case 0x00 : puts ("ENG - this board sucks, check the errata, not supported\n");
275 return -1;
276 case 0x01 : puts ("PILOT - warning, read errata \n"); break;
277 case 0x02 : puts ("A - warning, read errata \n"); break;
278 case 0x03 : puts ("B \n"); break;
279 default : printf ("unknown revision (0x%x)\n", k); return -1;
280 }
281
282 return 0;
283#endif /* CONFIG_ADS */
284
285}
286
287/* ------------------------------------------------------------------------- */
288int _draminit(uint base, uint noMbytes, uint edo, uint delay)
289{
290 volatile immap_t *immap = (immap_t *)CFG_IMMR;
291 volatile memctl8xx_t *memctl = &immap->im_memctl;
292
293 /* init upm */
294
295 switch(delay)
296 {
297 case 70:
298 {
299 if(edo)
300 {
301 upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint));
302 }
303 else
304 {
305 upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint));
306 }
307
308 break;
309 }
310
311 case 60:
312 {
313 if(edo)
314 {
315 upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
316 }
317 else
318 {
319 upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint));
320 }
321
322 break;
323 }
324
325 default :
326 return -1;
327 }
328
329 memctl->memc_mptpr = 0x0400; /* divide by 16 */
330
331 switch(noMbytes)
332 {
333
334 case 8: /* 8 Mbyte uses both CS3 and CS2 */
335 {
336 memctl->memc_mamr = 0x13a01114;
337 memctl->memc_or3 = 0xffc00800;
338 memctl->memc_br3 = 0x00400081 + base;
339 memctl->memc_or2 = 0xffc00800;
340 break;
341 }
342
343 case 4: /* 4 Mbyte uses only CS2 */
344 {
345 memctl->memc_mamr = 0x13a01114;
346 memctl->memc_or2 = 0xffc00800;
347 break;
348 }
349
350 case 32: /* 32 Mbyte uses both CS3 and CS2 */
351 {
352 memctl->memc_mamr = 0x13b01114;
353 memctl->memc_or3 = 0xff000800;
354 memctl->memc_br3 = 0x01000081 + base;
355 memctl->memc_or2 = 0xff000800;
356 break;
357 }
358
359 case 16: /* 16 Mbyte uses only CS2 */
360 {
361#ifdef CONFIG_ADS
362 memctl->memc_mamr = 0x60b21114;
363#else
364 memctl->memc_mamr = 0x13b01114;
365#endif
366 memctl->memc_or2 = 0xff000800;
367 break;
368 }
369
370 default:
371 return -1;
372 }
373
374 memctl->memc_br2 = 0x81 + base; /* use upma */
375 return 0;
376}
377
378/* ------------------------------------------------------------------------- */
379
380void _dramdisable(void)
381{
382 volatile immap_t *immap = (immap_t *)CFG_IMMR;
383 volatile memctl8xx_t *memctl = &immap->im_memctl;
384
385 memctl->memc_br2 = 0x00000000;
386 memctl->memc_br3 = 0x00000000;
387
388 /* maybe we should turn off upma here or something */
389}
390
391#if defined(CONFIG_SDRAM_100MHZ)
392
393/* ------------------------------------------------------------------------- */
394/* sdram table by Dan Malek */
395
396/* This has the stretched early timing so the 50 MHz
397 * processor can make the 100 MHz timing. This will
398 * work at all processor speeds.
399 */
400
401#define SDRAM_MPTPRVALUE 0x0400
402
403#define SDRAM_MBMRVALUE0 0xc3802114 /* (16-14) 50 MHz */
404#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
405
406#define SDRAM_OR4VALUE 0xffc00a00
407#define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */
408
409#define SDRAM_MARVALUE 0x88
410
411#define SDRAM_MCRVALUE0 0x80808111 /* run pattern 0x11 */
412#define SDRAM_MCRVALUE1 SDRAM_MCRVALUE0
413
414
415const uint sdram_table[] =
416{
417 /* single read. (offset 0 in upm RAM) */
418 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
419 0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff,
420
421 /* burst read. (offset 8 in upm RAM) */
422 0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
423 0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
424 0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
425 0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
426
427 /* single write. (offset 18 in upm RAM) */
428 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
429 0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff,
430
431 /* burst write. (offset 20 in upm RAM) */
432 0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
433 0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
434 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
435 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
436
437 /* refresh. (offset 30 in upm RAM) */
438 0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
439 0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
440 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
441
442 /* exception. (offset 3c in upm RAM) */
443 0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff };
444
445#elif defined(CONFIG_SDRAM_50MHZ)
446
447/* ------------------------------------------------------------------------- */
448/* sdram table stolen from the fads manual */
449/* for chip MB811171622A-100 */
450
451/* this table is for 32-50MHz operation */
452
453#define _not_used_ 0xffffffff
454
455#define SDRAM_MPTPRVALUE 0x0400
456
457#define SDRAM_MBMRVALUE0 0x80802114 /* refresh at 32MHz */
458#define SDRAM_MBMRVALUE1 0x80802118
459
460#define SDRAM_OR4VALUE 0xffc00a00
461#define SDRAM_BR4VALUE 0x000000c1 /* base address will be or:ed on */
462
463#define SDRAM_MARVALUE 0x88
464
465#define SDRAM_MCRVALUE0 0x80808105
466#define SDRAM_MCRVALUE1 0x80808130
467
468const uint sdram_table[] =
469{
470 /* single read. (offset 0 in upm RAM) */
471 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
472 0x1ff77c47,
473
474 /* MRS initialization (offset 5) */
475
476 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
477
478 /* burst read. (offset 8 in upm RAM) */
479 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
480 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
481 _not_used_, _not_used_, _not_used_, _not_used_,
482 _not_used_, _not_used_, _not_used_, _not_used_,
483
484 /* single write. (offset 18 in upm RAM) */
485 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
486 _not_used_, _not_used_, _not_used_, _not_used_,
487
488 /* burst write. (offset 20 in upm RAM) */
489 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
490 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
491 _not_used_, _not_used_, _not_used_, _not_used_,
492 _not_used_, _not_used_, _not_used_, _not_used_,
493
494 /* refresh. (offset 30 in upm RAM) */
495 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
496 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
497 _not_used_, _not_used_, _not_used_, _not_used_,
498
499 /* exception. (offset 3c in upm RAM) */
500 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
501
502/* ------------------------------------------------------------------------- */
503#else
504#error SDRAM not correctly configured
505#endif
506
507int _initsdram(uint base, uint noMbytes)
508{
509 volatile immap_t *immap = (immap_t *)CFG_IMMR;
510 volatile memctl8xx_t *memctl = &immap->im_memctl;
511
512 if(noMbytes != 4)
513 {
514 return -1;
515 }
516
517 upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
518
519 memctl->memc_mptpr = SDRAM_MPTPRVALUE;
520
521 /* Configure the refresh (mostly). This needs to be
522 * based upon processor clock speed and optimized to provide
523 * the highest level of performance. For multiple banks,
524 * this time has to be divided by the number of banks.
525 * Although it is not clear anywhere, it appears the
526 * refresh steps through the chip selects for this UPM
527 * on each refresh cycle.
528 * We have to be careful changing
529 * UPM registers after we ask it to run these commands.
530 */
531
532 memctl->memc_mbmr = SDRAM_MBMRVALUE0;
533 memctl->memc_mar = SDRAM_MARVALUE; /* MRS code */
534
535 udelay(200);
536
537 /* Now run the precharge/nop/mrs commands.
538 */
539
540 memctl->memc_mcr = 0x80808111; /* run pattern 0x11 */
541
542 udelay(200);
543
544 /* Run 8 refresh cycles */
545
546 memctl->memc_mcr = SDRAM_MCRVALUE0;
547
548 udelay(200);
549
550 memctl->memc_mbmr = SDRAM_MBMRVALUE1;
551 memctl->memc_mcr = SDRAM_MCRVALUE1;
552
553 udelay(200);
554
555 memctl->memc_mbmr = SDRAM_MBMRVALUE0;
556
557 memctl->memc_or4 = SDRAM_OR4VALUE;
558 memctl->memc_br4 = SDRAM_BR4VALUE | base;
559
560 return 0;
561}
562
563/* ------------------------------------------------------------------------- */
564
565void _sdramdisable(void)
566{
567 volatile immap_t *immap = (immap_t *)CFG_IMMR;
568 volatile memctl8xx_t *memctl = &immap->im_memctl;
569
570 memctl->memc_br4 = 0x00000000;
571
572 /* maybe we should turn off upmb here or something */
573}
574
575/* ------------------------------------------------------------------------- */
576
577int initsdram(uint base, uint *noMbytes)
578{
579 uint m = 4;
580
581 *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
582 /* _fads_sdraminit needs access to sdram */
583 *noMbytes = m;
584
585 if(!_initsdram(base, m))
586 {
587
588 return 0;
589 }
590 else
591 {
592 *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
593
594 _sdramdisable();
595
596 return -1;
597 }
598}
599
600long int initdram (int board_type)
601{
602#ifdef CONFIG_ADS
603 /* ADS: has no SDRAM, so start DRAM at 0 */
604 uint base = (unsigned long)0x0;
605#else
606 /* FADS: has 4MB SDRAM, put DRAM above it */
607 uint base = (unsigned long)0x00400000;
608#endif
609 uint k, m, s;
610
611 k = (*((uint *)BCSR2) >> 23) & 0x0f;
612
613 m = 0;
614
615 switch(k & 0x3)
616 {
617 /* "MCM36100 / MT8D132X" */
618 case 0x00 :
619 m = 4;
620 break;
621
622 /* "MCM36800 / MT16D832X" */
623 case 0x01 :
624 m = 32;
625 break;
626 /* "MCM36400 / MT8D432X" */
627 case 0x02 :
628 m = 16;
629 break;
630 /* "MCM36200 / MT16D832X ?" */
631 case 0x03 :
632 m = 8;
633 break;
634
635 }
636
637 switch(k >> 2)
638 {
639 case 0x02 :
640 k = 70;
641 break;
642
643 case 0x03 :
644 k = 60;
645 break;
646
647 default :
648 printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
649 k = 70;
650 }
651
652#ifdef CONFIG_FADS
653 /* the FADS is missing this bit, all rams treated as non-edo */
654 s = 0;
655#else
656 s = (*((uint *)BCSR2) >> 27) & 0x01;
657#endif
658
659 if(!_draminit(base, m, s, k))
660 {
661#ifdef CONFIG_FADS
662 uint sdramsz;
663#endif
664 *((uint *)BCSR1) &= ~BCSR1_DRAM_EN; /* enable dram */
665
666#ifdef CONFIG_FADS
667 if (!initsdram(0x00000000, &sdramsz)) {
668 m += sdramsz;
669 printf("(%u MB SDRAM) ", sdramsz);
670 } else {
671 _dramdisable();
672
673 /********************************
674 *DRAM ERROR, HALT PROCESSOR
675 *********************************/
676 while(1);
677
678 return -1;
679 }
680#endif
681
682 return (m << 20);
683 }
684 else
685 {
686 _dramdisable();
687
688 /********************************
689 *DRAM ERROR, HALT PROCESSOR
690 *********************************/
691 while(1);
692
693 return -1;
694 }
695}
696
697/* ------------------------------------------------------------------------- */
698
699int testdram (void)
700{
701 /* TODO: XXX XXX XXX */
702 printf ("test: 16 MB - ok\n");
703
704 return (0);
705}
706
707
708#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
709
710#ifdef CFG_PCMCIA_MEM_ADDR
711volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
712#endif
713
714int pcmcia_init(void)
715{
716 volatile pcmconf8xx_t *pcmp;
717 uint v, slota, slotb;
718
719 /*
720 ** Enable the PCMCIA for a Flash card.
721 */
722 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
723
724#if 0
725 pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
726 pcmp->pcmc_por0 = 0xc00ff05d;
727#endif
728
729 /* Set all slots to zero by default. */
730 pcmp->pcmc_pgcra = 0;
731 pcmp->pcmc_pgcrb = 0;
732#ifdef PCMCIA_SLOT_A
733 pcmp->pcmc_pgcra = 0x40;
734#endif
735#ifdef PCMCIA_SLOT_B
736 pcmp->pcmc_pgcrb = 0x40;
737#endif
738
739 /* enable PCMCIA buffers */
740 *((uint *)BCSR1) &= ~BCSR1_PCCEN;
741
742 /* Check if any PCMCIA card is plugged in. */
743
744 slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
745 slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
746
747 if (!(slota || slotb))
748 {
749 printf("No card present\n");
750#ifdef PCMCIA_SLOT_A
751 pcmp->pcmc_pgcra = 0;
752#endif
753#ifdef PCMCIA_SLOT_B
754 pcmp->pcmc_pgcrb = 0;
755#endif
756 return -1;
757 }
758 else
759 printf("Card present (");
760
761 v = 0;
762
763 /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
764 **
765 ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
766 ** my FADS... :-)
767 */
768
769#if defined(CONFIG_MPC860)
770 switch( (pcmp->pcmc_pipr >> 30) & 3 )
771#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
772 switch( (pcmp->pcmc_pipr >> 14) & 3 )
773#endif
774 {
775 case 0x00 :
776 printf("5V");
777 v = 5;
778 break;
779 case 0x01 :
780 printf("5V and 3V");
781#ifdef CONFIG_FADS
782 v = 3; /* User lower voltage if supported! */
783#else
784 v = 5;
785#endif
786 break;
787 case 0x03 :
788 printf("5V, 3V and x.xV");
789#ifdef CONFIG_FADS
790 v = 3; /* User lower voltage if supported! */
791#else
792 v = 5;
793#endif
794 break;
795 }
796
797 switch(v){
798#ifdef CONFIG_FADS
799 case 3:
800 printf("; using 3V");
801 /*
802 ** Enable 3 volt Vcc.
803 */
804 *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
805 *((uint *)BCSR1) |= BCSR1_PCCVCC0;
806 break;
807#endif
808 case 5:
809 printf("; using 5V");
810#ifdef CONFIG_ADS
811 /*
812 ** Enable 5 volt Vcc.
813 */
814 *((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
815#endif
816#ifdef CONFIG_FADS
817 /*
818 ** Enable 5 volt Vcc.
819 */
820 *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
821 *((uint *)BCSR1) |= BCSR1_PCCVCC1;
822#endif
823 break;
824
825 default:
826 *((uint *)BCSR1) |= BCSR1_PCCEN; /* disable pcmcia */
827
828 printf("; unknown voltage");
829 return -1;
830 }
831 printf(")\n");
832 /* disable pcmcia reset after a while */
833
834 udelay(20);
835
836#ifdef MPC860
837 pcmp->pcmc_pgcra = 0;
838#elif MPC823
839 pcmp->pcmc_pgcrb = 0;
840#endif
841
842 /* If you using a real hd you should give a short
843 * spin-up time. */
844#ifdef CONFIG_DISK_SPINUP_TIME
845 udelay(CONFIG_DISK_SPINUP_TIME);
846#endif
847
848 return 0;
849}
850
851#endif /* CFG_CMD_PCMCIA */
852
853/* ------------------------------------------------------------------------- */
854
855#ifdef CFG_PC_IDE_RESET
856
857void ide_set_reset(int on)
858{
859 volatile immap_t *immr = (immap_t *)CFG_IMMR;
860
861 /*
862 * Configure PC for IDE Reset Pin
863 */
864 if (on) { /* assert RESET */
865 immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
866 } else { /* release RESET */
867 immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
868 }
869
870 /* program port pin as GPIO output */
871 immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
872 immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
873 immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
874}
875
876#endif /* CFG_PC_IDE_RESET */
877/* ------------------------------------------------------------------------- */
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