[J-u-boot.git] / include / configs / at91sam9261ek.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9261EK board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */

#ifdef CONFIG_AT91SAM9G10
#define CONFIG_AT91SAM9G10EK		/* It's an Atmel AT91SAM9G10 EK*/
#else
#define CONFIG_AT91SAM9261EK		/* It's an Atmel AT91SAM9261 EK*/
#endif

#include <asm/hardware.h>

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_ATMEL_LEGACY
#define CONFIG_SYS_TEXT_BASE		0x21f00000

/*
 * Hardware drivers
 */

/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_ATMEL_LCD
#ifdef CONFIG_AT91SAM9261EK
#define CONFIG_ATMEL_LCD_BGR555
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x04000000
#define CONFIG_SYS_INIT_SP_ADDR \
	(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15

#endif

/* Ethernet */
#define CONFIG_DRIVER_DM9000
#define CONFIG_DM9000_BASE		0x30000000
#define DM9000_IO			CONFIG_DM9000_BASE
#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT
#define CONFIG_DM9000_NO_SROM
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
#ifdef CONFIG_AT91SAM9G10EK
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g10"
#else
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#ifdef CONFIG_SYS_USE_DATAFLASH_CS0

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	15000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"

#elif CONFIG_SYS_USE_DATAFLASH_CS3

/* bootstrap + u-boot + env + linux in dataflash on CS3 */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	15000000
#define CONFIG_BOOTCOMMAND	"sf probe 0:3; " \
				"sf read 0x22000000 0x84000 0x294000; " \
				"bootm 0x22000000"

#else /* CONFIG_SYS_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET		0x120000
#define CONFIG_ENV_OFFSET_REDUND	0x100000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
#endif

#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)

#endif
Commit	Line	Data
d99a8ff6 SP	1	/*
d99a8ff6 SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <[email protected]>
d99a8ff6 SP	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Configuation settings for the AT91SAM9261EK board.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
d99a8ff6 SP	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/* ARM asynchronous clock */
f7aea46d	15	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
7c966a8b	16	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
d99a8ff6	17
f7aea46d XH	18	#ifdef CONFIG_AT91SAM9G10
f7aea46d XH	19	#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/
5ccc2d99	20	#else
f7aea46d	21	#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/
5ccc2d99	22	#endif
f7aea46d XH	23
	24	#include <asm/hardware.h>
	25
f7aea46d XH	26	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	27	#define CONFIG_SETUP_MEMORY_TAGS
	28	#define CONFIG_INITRD_TAG
d99a8ff6 SP	29
d99a8ff6 SP	30	#define CONFIG_SKIP_LOWLEVEL_INIT
d99a8ff6	31
f7aea46d XH	32	#define CONFIG_ATMEL_LEGACY
	33	#define CONFIG_SYS_TEXT_BASE 0x21f00000
	34
d99a8ff6 SP	35	/*
	36	* Hardware drivers
	37	*/
f7aea46d	38
820f2a95	39	/* LCD */
820f2a95	40	#define LCD_BPP LCD_COLOR8
f7aea46d	41	#define CONFIG_LCD_LOGO
820f2a95	42	#undef LCD_TEST_PATTERN
f7aea46d XH	43	#define CONFIG_LCD_INFO
f7aea46d XH	44	#define CONFIG_LCD_INFO_BELOW_LOGO
f7aea46d	45	#define CONFIG_ATMEL_LCD
5ccc2d99	46	#ifdef CONFIG_AT91SAM9261EK
f7aea46d	47	#define CONFIG_ATMEL_LCD_BGR555
5ccc2d99	48	#endif
f7aea46d	49
d99a8ff6 SP	50	/*
	51	* BOOTP options
	52	*/
f7aea46d XH	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54	#define CONFIG_BOOTP_BOOTPATH
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
d99a8ff6	57
d99a8ff6 SP	58	/* SDRAM */
d99a8ff6 SP	59	#define CONFIG_NR_DRAM_BANKS 1
f7aea46d XH	60	#define CONFIG_SYS_SDRAM_BASE 0x20000000
	61	#define CONFIG_SYS_SDRAM_SIZE 0x04000000
	62	#define CONFIG_SYS_INIT_SP_ADDR \
324873e7	63	(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
d99a8ff6 SP	64
d99a8ff6 SP	65	/* NAND flash */
74c076d6 JCPV	66	#ifdef CONFIG_CMD_NAND
74c076d6 JCPV	67	#define CONFIG_NAND_ATMEL
6d0f6bcf JCPV	68	#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf JCPV	69	#define CONFIG_SYS_NAND_BASE 0x40000000
f7aea46d	70	#define CONFIG_SYS_NAND_DBW_8
74c076d6 JCPV	71	/* our ALE is AD22 */
	72	#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
	73	/* our CLE is AD21 */
	74	#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
	75	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	76	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
2eb99ca8	77
74c076d6	78	#endif
d99a8ff6	79
d99a8ff6	80	/* Ethernet */
f7aea46d	81	#define CONFIG_DRIVER_DM9000
d99a8ff6 SP	82	#define CONFIG_DM9000_BASE 0x30000000
	83	#define DM9000_IO CONFIG_DM9000_BASE
	84	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
f7aea46d XH	85	#define CONFIG_DM9000_USE_16BIT
f7aea46d XH	86	#define CONFIG_DM9000_NO_SROM
d99a8ff6	87	#define CONFIG_NET_RETRY_COUNT 20
f7aea46d	88	#define CONFIG_RESET_PHY_R
d99a8ff6 SP	89
d99a8ff6 SP	90	/* USB */
2b7178af	91	#define CONFIG_USB_ATMEL
dcd2f1a0	92	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
f7aea46d	93	#define CONFIG_USB_OHCI_NEW
f7aea46d	94	#define CONFIG_SYS_USB_OHCI_CPU_INIT
6d0f6bcf	95	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
5ccc2d99 SG	96	#ifdef CONFIG_AT91SAM9G10EK
	97	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10"
	98	#else
6d0f6bcf	99	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
5ccc2d99	100	#endif
6d0f6bcf	101	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
d99a8ff6	102
6d0f6bcf	103	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
d99a8ff6	104
f7aea46d	105	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
6d0f6bcf	106	#define CONFIG_SYS_MEMTEST_END 0x23e00000
d99a8ff6	107
6d0f6bcf	108	#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
d99a8ff6 SP	109
d99a8ff6 SP	110	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
89a7a87f	111	#define CONFIG_ENV_OFFSET 0x4200
0e8d1586	112	#define CONFIG_ENV_SIZE 0x4200
324873e7 WY	113	#define CONFIG_ENV_SECT_SIZE 0x210
	114	#define CONFIG_ENV_SPI_MAX_HZ 15000000
	115	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	116	"sf read 0x22000000 0x84000 0x294000; " \
	117	"bootm 0x22000000"
d99a8ff6	118
89a7a87f NF	119	#elif CONFIG_SYS_USE_DATAFLASH_CS3
	120
	121	/* bootstrap + u-boot + env + linux in dataflash on CS3 */
89a7a87f	122	#define CONFIG_ENV_OFFSET 0x4200
89a7a87f	123	#define CONFIG_ENV_SIZE 0x4200
324873e7 WY	124	#define CONFIG_ENV_SECT_SIZE 0x210
	125	#define CONFIG_ENV_SPI_MAX_HZ 15000000
	126	#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \
	127	"sf read 0x22000000 0x84000 0x294000; " \
	128	"bootm 0x22000000"
89a7a87f	129
6d0f6bcf	130	#else /* CONFIG_SYS_USE_NANDFLASH */
d99a8ff6 SP	131
d99a8ff6 SP	132	/* bootstrap + u-boot + env + linux in nandflash */
324873e7	133	#define CONFIG_ENV_OFFSET 0x120000
0c58cfa9	134	#define CONFIG_ENV_OFFSET_REDUND 0x100000
0e8d1586	135	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
0c58cfa9	136	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
d99a8ff6 SP	137	#endif
d99a8ff6 SP	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_CBSIZE 256
6d0f6bcf JCPV	140	#define CONFIG_SYS_MAXARGS 16
f7aea46d XH	141	#define CONFIG_SYS_LONGHELP
f7aea46d XH	142	#define CONFIG_CMDLINE_EDITING
e139cb31	143	#define CONFIG_AUTO_COMPLETE
d99a8ff6	144
d99a8ff6 SP	145	/*
	146	* Size of malloc() pool
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
d99a8ff6	149
d99a8ff6	150	#endif