[J-u-boot.git] / arch / riscv / cpu / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018, Bin Meng <[email protected]>
 */

#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <log.h>
#include <asm/csr.h>
#include <asm/encoding.h>
#include <dm/uclass-internal.h>

/*
 * The variables here must be stored in the data section since they are used
 * before the bss section is available.
 */
phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
u32 hart_lottery __attribute__((section(".data"))) = 0;

/*
 * The main hart running U-Boot has acquired available_harts_lock until it has
 * finished initialization of global data.
 */
u32 available_harts_lock = 1;

static inline bool supports_extension(char ext)
{
#ifdef CONFIG_CPU
	struct udevice *dev;
	char desc[32];

	uclass_find_first_device(UCLASS_CPU, &dev);
	if (!dev) {
		debug("unable to find the RISC-V cpu device\n");
		return false;
	}
	if (!cpu_get_desc(dev, desc, sizeof(desc))) {
		/* skip the first 4 characters (rv32|rv64) */
		if (strchr(desc + 4, ext))
			return true;
	}

	return false;
#else  /* !CONFIG_CPU */
#ifdef CONFIG_RISCV_MMODE
	return csr_read(misa) & (1 << (ext - 'a'));
#else  /* !CONFIG_RISCV_MMODE */
#warning "There is no way to determine the available extensions in S-mode."
#warning "Please convert your board to use the RISC-V CPU driver."
	return false;
#endif /* CONFIG_RISCV_MMODE */
#endif /* CONFIG_CPU */
}

static int riscv_cpu_probe(void)
{
#ifdef CONFIG_CPU
	int ret;

	/* probe cpus so that RISC-V timer can be bound */
	ret = cpu_probe_all();
	if (ret)
		return log_msg_ret("RISC-V cpus probe failed\n", ret);
#endif

	return 0;
}

int arch_cpu_init_dm(void)
{
	int ret;

	ret = riscv_cpu_probe();
	if (ret)
		return ret;

	/* Enable FPU */
	if (supports_extension('d') || supports_extension('f')) {
		csr_set(MODE_PREFIX(status), MSTATUS_FS);
		csr_write(fcsr, 0);
	}

	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
		/*
		 * Enable perf counters for cycle, time,
		 * and instret counters only
		 */
		csr_write(mcounteren, GENMASK(2, 0));

		/* Disable paging */
		if (supports_extension('s'))
			csr_write(satp, 0);
	}

	return 0;
}

int arch_early_init_r(void)
{
	return riscv_cpu_probe();
}
Commit	Line	Data
2fab2e9c BM	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018, Bin Meng <[email protected]>
	4	*/
	5
	6	#include <common.h>
39cad5bc	7	#include <cpu.h>
aef59e5c	8	#include <dm.h>
39cad5bc	9	#include <log.h>
2fab2e9c	10	#include <asm/csr.h>
485e8223	11	#include <asm/encoding.h>
aef59e5c	12	#include <dm/uclass-internal.h>
2fab2e9c	13
5d8b2e77	14	/*
3dea63c8	15	* The variables here must be stored in the data section since they are used
5d8b2e77 LA	16	* before the bss section is available.
	17	*/
	18	phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
3dea63c8 LA	19	u32 hart_lottery __attribute__((section(".data"))) = 0;
	20
	21	/*
	22	* The main hart running U-Boot has acquired available_harts_lock until it has
	23	* finished initialization of global data.
	24	*/
	25	u32 available_harts_lock = 1;
5d8b2e77	26
2fab2e9c BM	27	static inline bool supports_extension(char ext)
2fab2e9c BM	28	{
aef59e5c BM	29	#ifdef CONFIG_CPU
	30	struct udevice *dev;
	31	char desc[32];
	32
	33	uclass_find_first_device(UCLASS_CPU, &dev);
	34	if (!dev) {
	35	debug("unable to find the RISC-V cpu device\n");
	36	return false;
	37	}
	38	if (!cpu_get_desc(dev, desc, sizeof(desc))) {
	39	/* skip the first 4 characters (rv32\|rv64) */
	40	if (strchr(desc + 4, ext))
	41	return true;
	42	}
	43
	44	return false;
	45	#else /* !CONFIG_CPU */
	46	#ifdef CONFIG_RISCV_MMODE
2fab2e9c	47	return csr_read(misa) & (1 << (ext - 'a'));
aef59e5c BM	48	#else /* !CONFIG_RISCV_MMODE */
	49	#warning "There is no way to determine the available extensions in S-mode."
	50	#warning "Please convert your board to use the RISC-V CPU driver."
	51	return false;
	52	#endif /* CONFIG_RISCV_MMODE */
	53	#endif /* CONFIG_CPU */
2fab2e9c BM	54	}
2fab2e9c BM	55
39cad5bc BM	56	static int riscv_cpu_probe(void)
	57	{
	58	#ifdef CONFIG_CPU
	59	int ret;
	60
	61	/* probe cpus so that RISC-V timer can be bound */
	62	ret = cpu_probe_all();
	63	if (ret)
	64	return log_msg_ret("RISC-V cpus probe failed\n", ret);
	65	#endif
	66
	67	return 0;
	68	}
	69
	70	int arch_cpu_init_dm(void)
	71	{
485e8223 BM	72	int ret;
	73
	74	ret = riscv_cpu_probe();
	75	if (ret)
	76	return ret;
	77
	78	/* Enable FPU */
	79	if (supports_extension('d') \|\| supports_extension('f')) {
	80	csr_set(MODE_PREFIX(status), MSTATUS_FS);
	81	csr_write(fcsr, 0);
	82	}
	83
	84	if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
	85	/*
	86	* Enable perf counters for cycle, time,
	87	* and instret counters only
	88	*/
	89	csr_write(mcounteren, GENMASK(2, 0));
	90
	91	/* Disable paging */
	92	if (supports_extension('s'))
	93	csr_write(satp, 0);
	94	}
	95
	96	return 0;
39cad5bc BM	97	}
	98
	99	int arch_early_init_r(void)
	100	{
	101	return riscv_cpu_probe();
	102	}