projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4a442d31 TL |
1 | /* |
| 2 | * Configuation settings for the Freescale MCF5329 FireEngine board. | |
| 3 | * | |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
| 5 | * TsiChung Liew ([email protected]) | |
| 6 | * | |
| 7 | * See file CREDITS for list of people who contributed to this | |
| 8 | * project. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| 25 | ||
| 26 | /* | |
| 27 | * board/config.h - configuration options, board specific | |
| 28 | */ | |
| 29 | ||
| 30 | #ifndef _M5235EVB_H | |
| 31 | #define _M5235EVB_H | |
| 32 | ||
| 33 | /* | |
| 34 | * High Level Configuration Options | |
| 35 | * (easy to change) | |
| 36 | */ | |
| 37 | #define CONFIG_MCF523x /* define processor family */ | |
| 38 | #define CONFIG_M5235 /* define processor type */ | |
| 39 | ||
| 4a442d31 TL |
40 | #define CONFIG_MCFUART |
| 41 | #define CFG_UART_PORT (0) | |
| 42 | #define CONFIG_BAUDRATE 115200 | |
| 43 | #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
| 44 | ||
| 45 | #undef CONFIG_WATCHDOG | |
| 46 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ | |
| 47 | ||
| 48 | /* | |
| 49 | * BOOTP options | |
| 50 | */ | |
| 51 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 52 | #define CONFIG_BOOTP_BOOTPATH | |
| 53 | #define CONFIG_BOOTP_GATEWAY | |
| 54 | #define CONFIG_BOOTP_HOSTNAME | |
| 55 | ||
| 56 | /* Command line configuration */ | |
| 57 | #include <config_cmd_default.h> | |
| 58 | ||
| 59 | #define CONFIG_CMD_BOOTD | |
| 60 | #define CONFIG_CMD_CACHE | |
| 61 | #define CONFIG_CMD_DHCP | |
| 62 | #define CONFIG_CMD_ELF | |
| 63 | #define CONFIG_CMD_FLASH | |
| 64 | #define CONFIG_CMD_I2C | |
| 65 | #define CONFIG_CMD_MEMORY | |
| 66 | #define CONFIG_CMD_MISC | |
| 67 | #define CONFIG_CMD_MII | |
| 68 | #define CONFIG_CMD_NET | |
| 69 | #define CONFIG_CMD_PCI | |
| 70 | #define CONFIG_CMD_PING | |
| 71 | #define CONFIG_CMD_REGINFO | |
| 72 | ||
| 73 | #undef CONFIG_CMD_LOADB | |
| 74 | #undef CONFIG_CMD_LOADS | |
| 75 | ||
| 76 | #define CONFIG_MCFFEC | |
| 77 | #ifdef CONFIG_MCFFEC | |
| 78 | # define CONFIG_NET_MULTI 1 | |
| 79 | # define CONFIG_MII 1 | |
| 0f3ba7e9 | 80 | # define CONFIG_MII_INIT 1 |
| 4a442d31 TL |
81 | # define CFG_DISCOVER_PHY |
| 82 | # define CFG_RX_ETH_BUFFER 8 | |
| 83 | # define CFG_FAULT_ECHO_LINK_DOWN | |
| 84 | ||
| 85 | # define CFG_FEC0_PINMUX 0 | |
| 86 | # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE | |
| 53677ef1 | 87 | # define MCFFEC_TOUT_LOOP 50000 |
| 4a442d31 TL |
88 | /* If CFG_DISCOVER_PHY is not defined - hardcoded */ |
| 89 | # ifndef CFG_DISCOVER_PHY | |
| 90 | # define FECDUPLEX FULL | |
| 91 | # define FECSPEED _100BASET | |
| 92 | # else | |
| 93 | # ifndef CFG_FAULT_ECHO_LINK_DOWN | |
| 94 | # define CFG_FAULT_ECHO_LINK_DOWN | |
| 95 | # endif | |
| 96 | # endif /* CFG_DISCOVER_PHY */ | |
| 97 | #endif | |
| 98 | ||
| 99 | /* Timer */ | |
| 100 | #define CONFIG_MCFTMR | |
| 101 | #undef CONFIG_MCFPIT | |
| 102 | ||
| 103 | /* I2C */ | |
| 104 | #define CONFIG_FSL_I2C | |
| eec567a6 TL |
105 | #define CONFIG_HARD_I2C /* I2C with hw support */ |
| 106 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 4a442d31 TL |
107 | #define CFG_I2C_SPEED 80000 |
| 108 | #define CFG_I2C_SLAVE 0x7F | |
| 109 | #define CFG_I2C_OFFSET 0x00000300 | |
| 110 | #define CFG_IMMR CFG_MBAR | |
| eec567a6 TL |
111 | #define CFG_I2C_PINMUX_REG (gpio->par_qspi) |
| 112 | #define CFG_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) | |
| 113 | #define CFG_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) | |
| 4a442d31 TL |
114 | |
| 115 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
| 116 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
| 117 | #define CONFIG_BOOTFILE "u-boot.bin" | |
| 118 | #ifdef CONFIG_MCFFEC | |
| 119 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
| 120 | # define CONFIG_IPADDR 192.162.1.2 | |
| 121 | # define CONFIG_NETMASK 255.255.255.0 | |
| 122 | # define CONFIG_SERVERIP 192.162.1.1 | |
| 123 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
| 124 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
| 125 | #endif /* FEC_ENET */ | |
| 126 | ||
| 127 | #define CONFIG_HOSTNAME M5235EVB | |
| 128 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 129 | "netdev=eth0\0" \ | |
| 130 | "loadaddr=10000\0" \ | |
| 131 | "u-boot=u-boot.bin\0" \ | |
| 132 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
| 133 | "upd=run load; run prog\0" \ | |
| 134 | "prog=prot off ffe00000 ffe3ffff;" \ | |
| 135 | "era ffe00000 ffe3ffff;" \ | |
| 136 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
| 137 | "save\0" \ | |
| 138 | "" | |
| 139 | ||
| 140 | #define CONFIG_PRAM 512 /* 512 KB */ | |
| 141 | #define CFG_PROMPT "-> " | |
| 142 | #define CFG_LONGHELP /* undef to save memory */ | |
| 143 | ||
| 144 | #if defined(CONFIG_KGDB) | |
| 145 | # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 146 | #else | |
| 147 | # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 148 | #endif | |
| 149 | ||
| 150 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 151 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 152 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 153 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE+0x20000) | |
| 154 | ||
| 155 | #define CFG_HZ 1000 | |
| 156 | #define CFG_CLK 75000000 | |
| 157 | #define CFG_CPU_CLK CFG_CLK * 2 | |
| 158 | ||
| 159 | #define CFG_MBAR 0x40000000 | |
| 160 | ||
| 161 | /* | |
| 162 | * Low Level Configuration Settings | |
| 163 | * (address mappings, register initial values, etc.) | |
| 164 | * You should know what you are doing if you make changes here. | |
| 165 | */ | |
| 166 | /*----------------------------------------------------------------------- | |
| 167 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 168 | */ | |
| 169 | #define CFG_INIT_RAM_ADDR 0x20000000 | |
| 170 | #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ | |
| 171 | #define CFG_INIT_RAM_CTRL 0x21 | |
| 172 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
| 173 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE - 0x10) | |
| 174 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 175 | ||
| 176 | /*----------------------------------------------------------------------- | |
| 177 | * Start addresses for the final memory configuration | |
| 178 | * (Set up by the startup code) | |
| 179 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 180 | */ | |
| 181 | #define CFG_SDRAM_BASE 0x00000000 | |
| 182 | #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
| 183 | ||
| 184 | #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 | |
| 185 | #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) | |
| 186 | ||
| 187 | #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) | |
| 188 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 189 | ||
| 190 | #define CFG_BOOTPARAMS_LEN 64*1024 | |
| 191 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 192 | ||
| 193 | /* | |
| 194 | * For booting Linux, the board info and command line data | |
| 195 | * have to be in the first 8 MB of memory, since this is | |
| 196 | * the maximum mapped by the Linux kernel during initialization ?? | |
| 197 | */ | |
| 198 | /* Initial Memory map for Linux */ | |
| 199 | #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) | |
| 200 | ||
| 201 | /*----------------------------------------------------------------------- | |
| 202 | * FLASH organization | |
| 203 | */ | |
| 204 | #define CFG_FLASH_CFI | |
| 205 | #ifdef CFG_FLASH_CFI | |
| 00b1883a | 206 | # define CONFIG_FLASH_CFI_DRIVER 1 |
| 4a442d31 TL |
207 | # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
| 208 | #ifdef NORFLASH_PS32BIT | |
| 209 | # define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT | |
| 210 | #else | |
| 211 | # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
| 212 | #endif | |
| 213 | # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 214 | # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
| 215 | # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
| 216 | #endif | |
| 217 | ||
| 218 | #define CFG_FLASH_BASE (CFG_CS0_BASE << 16) | |
| 219 | ||
| 220 | /* Configuration for environment | |
| 221 | * Environment is embedded in u-boot in the second sector of the flash | |
| 222 | */ | |
| 5a1aceb0 | 223 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 4a442d31 TL |
224 | #define CFG_ENV_IS_EMBEDDED 1 |
| 225 | #ifdef NORFLASH_PS32BIT | |
| 226 | # define CFG_ENV_OFFSET (0x8000) | |
| 227 | # define CFG_ENV_SIZE 0x4000 | |
| 228 | # define CFG_ENV_SECT_SIZE 0x4000 | |
| 229 | #else | |
| 230 | # define CFG_ENV_OFFSET (0x4000) | |
| 231 | # define CFG_ENV_SIZE 0x2000 | |
| 232 | # define CFG_ENV_SECT_SIZE 0x2000 | |
| 233 | #endif | |
| 234 | ||
| 235 | /*----------------------------------------------------------------------- | |
| 236 | * Cache Configuration | |
| 237 | */ | |
| 238 | #define CFG_CACHELINE_SIZE 16 | |
| 239 | ||
| 240 | /*----------------------------------------------------------------------- | |
| 241 | * Chipselect bank definitions | |
| 242 | */ | |
| 243 | /* | |
| 244 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
| 245 | * CS1 - Available | |
| 246 | * CS2 - Available | |
| 247 | * CS3 - Available | |
| 248 | * CS4 - Available | |
| 249 | * CS5 - Available | |
| 250 | * CS6 - Available | |
| 251 | * CS7 - Available | |
| 252 | */ | |
| 253 | #ifdef NORFLASH_PS32BIT | |
| 254 | # define CFG_CS0_BASE 0xFFC0 | |
| 255 | # define CFG_CS0_MASK 0x003f0001 | |
| 256 | # define CFG_CS0_CTRL 0x1D00 | |
| 257 | #else | |
| 258 | # define CFG_CS0_BASE 0xFFE0 | |
| 259 | # define CFG_CS0_MASK 0x001f0001 | |
| 260 | # define CFG_CS0_CTRL 0x1D80 | |
| 261 | #endif | |
| 262 | ||
| 263 | #endif /* _M5329EVB_H */ |