FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

[J-u-boot.git] / cpu / mpc86xx / Makefile

#
# Copyright 2007 Freescale Semiconductor, Inc.
# (C) Copyright 2002,2003 Motorola Inc.
# Xianghua Xiao,[email protected]
#
# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port)
# Jeff Brown
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#

include $(TOPDIR)/config.mk

LIB	= $(obj)lib$(CPU).a

START	= start.o
SOBJS	= cache.o

COBJS-y	+= traps.o
COBJS-y	+= cpu.o
COBJS-y	+= cpu_init.o
COBJS-y	+= speed.o
COBJS-y	+= interrupts.o

COBJS-$(CONFIG_OF_LIBFDT) += fdt.o

ifneq ($(CONFIG_FSL_DDR2),y)
COBJS-y	+= spd_sdram.o
endif

SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
START	:= $(addprefix $(obj),$(START))

all:	$(obj).depend $(START) $(LIB)

$(LIB):	$(OBJS)
	$(AR) $(ARFLAGS) $@ $(ASOBJS) $(OBJS)

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# defines $(obj).depend target
include $(SRCTREE)/rules.mk

sinclude $(obj).depend

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