[J-u-boot.git] / drivers / usb / host / xhci-dwc3.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * DWC3 controller driver
 *
 * Author: Ramneek Mehresh<[email protected]>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <usb.h>

#include "xhci.h"
#include <asm/io.h>
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>

DECLARE_GLOBAL_DATA_PTR;

void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
	clrsetbits_le32(&dwc3_reg->g_ctl,
			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
			DWC3_GCTL_PRTCAPDIR(mode));
}

static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
{
	/* Assert USB3 PHY reset */
	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);

	/* Assert USB2 PHY reset */
	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);

	mdelay(100);

	/* Clear USB3 PHY reset */
	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);

	/* Clear USB2 PHY reset */
	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
}

void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
	/* Before Resetting PHY, put Core in Reset */
	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);

	/* reset USB3 phy - if required */
	dwc3_phy_reset(dwc3_reg);

	mdelay(100);

	/* After PHYs are stable we can take Core out of reset state */
	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}

int dwc3_core_init(struct dwc3 *dwc3_reg)
{
	u32 reg;
	u32 revision;
	unsigned int dwc3_hwparams1;

	revision = readl(&dwc3_reg->g_snpsid);
	/* This should read as U3 followed by revision number */
	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
		puts("this is not a DesignWare USB3 DRD Core\n");
		return -1;
	}

	dwc3_core_soft_reset(dwc3_reg);

	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);

	reg = readl(&dwc3_reg->g_ctl);
	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		debug("No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * where the device can fail to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter a Connect/Disconnect loop
	 */
	if ((revision & DWC3_REVISION_MASK) < 0x190a)
		reg |= DWC3_GCTL_U2RSTECN;

	writel(reg, &dwc3_reg->g_ctl);

	return 0;
}

void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
{
	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
			GFLADJ_30MHZ(val));
}

static int xhci_dwc3_probe(struct udevice *dev)
{
	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
	struct xhci_hcor *hcor;
	struct xhci_hccr *hccr;
	struct dwc3 *dwc3_reg;
	enum usb_dr_mode dr_mode;

	hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
	hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);

	dwc3_core_init(dwc3_reg);

	dr_mode = usb_get_dr_mode(dev_of_offset(dev));
	if (dr_mode == USB_DR_MODE_UNKNOWN)
		/* by default set dual role mode to HOST */
		dr_mode = USB_DR_MODE_HOST;

	dwc3_set_mode(dwc3_reg, dr_mode);

	return xhci_register(dev, hccr, hcor);
}

static int xhci_dwc3_remove(struct udevice *dev)
{
	return xhci_deregister(dev);
}

static const struct udevice_id xhci_dwc3_ids[] = {
	{ .compatible = "snps,dwc3" },
	{ }
};

U_BOOT_DRIVER(xhci_dwc3) = {
	.name = "xhci-dwc3",
	.id = UCLASS_USB,
	.of_match = xhci_dwc3_ids,
	.probe = xhci_dwc3_probe,
	.remove = xhci_dwc3_remove,
	.ops = &xhci_usb_ops,
	.priv_auto_alloc_size = sizeof(struct xhci_ctrl),
	.platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
dc9cdf85 RM	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* DWC3 controller driver
	5	*
	6	* Author: Ramneek Mehresh<[email protected]>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
b7c1c7d2 PC	12	#include <dm.h>
	13	#include <usb.h>
	14
	15	#include "xhci.h"
dc9cdf85 RM	16	#include <asm/io.h>
dc9cdf85 RM	17	#include <linux/usb/dwc3.h>
576e3cc7	18	#include <linux/usb/otg.h>
dc9cdf85	19
b7c1c7d2 PC	20	DECLARE_GLOBAL_DATA_PTR;
b7c1c7d2 PC	21
dc9cdf85 RM	22	void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
	23	{
	24	clrsetbits_le32(&dwc3_reg->g_ctl,
	25	DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
	26	DWC3_GCTL_PRTCAPDIR(mode));
	27	}
	28
121a4d13	29	static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
dc9cdf85 RM	30	{
	31	/* Assert USB3 PHY reset */
	32	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
	33
	34	/* Assert USB2 PHY reset */
	35	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
	36
	37	mdelay(100);
	38
	39	/* Clear USB3 PHY reset */
	40	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
	41
	42	/* Clear USB2 PHY reset */
	43	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
	44	}
	45
	46	void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
	47	{
	48	/* Before Resetting PHY, put Core in Reset */
	49	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
	50
	51	/* reset USB3 phy - if required */
	52	dwc3_phy_reset(dwc3_reg);
	53
5955bb93 RB	54	mdelay(100);
5955bb93 RB	55
dc9cdf85 RM	56	/* After PHYs are stable we can take Core out of reset state */
	57	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
	58	}
	59
	60	int dwc3_core_init(struct dwc3 *dwc3_reg)
	61	{
	62	u32 reg;
	63	u32 revision;
	64	unsigned int dwc3_hwparams1;
	65
	66	revision = readl(&dwc3_reg->g_snpsid);
	67	/* This should read as U3 followed by revision number */
	68	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
	69	puts("this is not a DesignWare USB3 DRD Core\n");
	70	return -1;
	71	}
	72
	73	dwc3_core_soft_reset(dwc3_reg);
	74
	75	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
	76
	77	reg = readl(&dwc3_reg->g_ctl);
	78	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	79	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	80	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
	81	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	82	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	83	break;
	84	default:
	85	debug("No power optimization available\n");
	86	}
	87
	88	/*
	89	* WORKAROUND: DWC3 revisions <1.90a have a bug
	90	* where the device can fail to connect at SuperSpeed
	91	* and falls back to high-speed mode which causes
	92	* the device to enter a Connect/Disconnect loop
	93	*/
	94	if ((revision & DWC3_REVISION_MASK) < 0x190a)
	95	reg \|= DWC3_GCTL_U2RSTECN;
	96
	97	writel(reg, &dwc3_reg->g_ctl);
	98
	99	return 0;
	100	}
667f4dd9 NB	101
	102	void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
	103	{
	104	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL \|
	105	GFLADJ_30MHZ(val));
	106	}
b7c1c7d2 PC	107
	108	static int xhci_dwc3_probe(struct udevice *dev)
	109	{
	110	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
	111	struct xhci_hcor *hcor;
	112	struct xhci_hccr *hccr;
	113	struct dwc3 *dwc3_reg;
576e3cc7	114	enum usb_dr_mode dr_mode;
b7c1c7d2 PC	115
	116	hccr = (struct xhci_hccr *)devfdt_get_addr(dev);
	117	hcor = (struct xhci_hcor *)((phys_addr_t)hccr +
	118	HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
	119
	120	dwc3_reg = (struct dwc3 )((char )(hccr) + DWC3_REG_OFFSET);
	121
	122	dwc3_core_init(dwc3_reg);
	123
576e3cc7 PC	124	dr_mode = usb_get_dr_mode(dev_of_offset(dev));
	125	if (dr_mode == USB_DR_MODE_UNKNOWN)
	126	/* by default set dual role mode to HOST */
	127	dr_mode = USB_DR_MODE_HOST;
	128
	129	dwc3_set_mode(dwc3_reg, dr_mode);
	130
b7c1c7d2 PC	131	return xhci_register(dev, hccr, hcor);
	132	}
	133
	134	static int xhci_dwc3_remove(struct udevice *dev)
	135	{
	136	return xhci_deregister(dev);
	137	}
	138
	139	static const struct udevice_id xhci_dwc3_ids[] = {
	140	{ .compatible = "snps,dwc3" },
	141	{ }
	142	};
	143
	144	U_BOOT_DRIVER(xhci_dwc3) = {
	145	.name = "xhci-dwc3",
	146	.id = UCLASS_USB,
	147	.of_match = xhci_dwc3_ids,
	148	.probe = xhci_dwc3_probe,
	149	.remove = xhci_dwc3_remove,
	150	.ops = &xhci_usb_ops,
	151	.priv_auto_alloc_size = sizeof(struct xhci_ctrl),
	152	.platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
	153	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	154	};