projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 7dd6545d FE |
2 | /* |
| 3 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
| 4 | * | |
| 903e779c | 5 | * Configuration settings for the Freescale i.MX6Q SabreAuto board. |
| 7dd6545d FE |
6 | */ |
| 7 | ||
| d7c11502 VM |
8 | #ifndef __MX6SABREAUTO_CONFIG_H |
| 9 | #define __MX6SABREAUTO_CONFIG_H | |
| 7dd6545d | 10 | |
| 823dff9d VM |
11 | #ifdef CONFIG_SPL |
| 12 | #include "imx6_spl.h" | |
| 13 | #endif | |
| 14 | ||
| 7dd6545d FE |
15 | #define CONFIG_MACH_TYPE 3529 |
| 16 | #define CONFIG_MXC_UART_BASE UART4_BASE | |
| 12ca05a3 | 17 | #define CONSOLE_DEV "ttymxc3" |
| 7dd6545d | 18 | |
| 73448b1f | 19 | /* USB Configs */ |
| d1a52860 TK |
20 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 21 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | |
| 73448b1f KW |
22 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 23 | #define CONFIG_MXC_USB_FLAGS 0 | |
| 24 | ||
| 8fe280f3 YL |
25 | #define CONFIG_PCA953X |
| 26 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } | |
| 27 | ||
| c1747970 | 28 | #include "mx6sabre_common.h" |
| 51535d9f | 29 | |
| 07f6ddb6 DD |
30 | /* Falcon Mode */ |
| 31 | #ifdef CONFIG_SPL_OS_BOOT | |
| 32 | #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" | |
| 33 | #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" | |
| 07f6ddb6 | 34 | #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 |
| 07f6ddb6 DD |
35 | |
| 36 | /* Falcon Mode - MMC support: args@1MB kernel@2MB */ | |
| 37 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ | |
| 38 | #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) | |
| 39 | #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ | |
| 40 | #endif | |
| 41 | ||
| ca62e5d0 | 42 | #ifdef CONFIG_MTD_NOR_FLASH |
| cdbdde3f FE |
43 | #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR |
| 44 | #define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) | |
| 45 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 46 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
| cdbdde3f | 47 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 565cfcf0 | 48 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| ca62e5d0 | 49 | #endif |
| cdbdde3f | 50 | |
| de7d02ae | 51 | #define CONFIG_SYS_FSL_USDHC_NUM 2 |
| de7d02ae | 52 | |
| 19578165 | 53 | /* I2C Configs */ |
| b089d039 | 54 | #define CONFIG_SYS_I2C_MXC |
| 03544c66 AA |
55 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
| 56 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
| f8cb101e | 57 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ |
| 19578165 RF |
58 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 59 | ||
| 83bb3215 | 60 | /* NAND stuff */ |
| 83bb3215 YL |
61 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 62 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
| 63 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
| 64 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
| 65 | ||
| 66 | /* DMA stuff, needed for GPMI/MXS NAND support */ | |
| 83bb3215 | 67 | |
| 593243d3 YL |
68 | /* PMIC */ |
| 69 | #define CONFIG_POWER | |
| 70 | #define CONFIG_POWER_I2C | |
| 71 | #define CONFIG_POWER_PFUZE100 | |
| 72 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
| 73 | ||
| d7c11502 | 74 | #endif /* __MX6SABREAUTO_CONFIG_H */ |