[J-u-boot.git] / include / configs / ls1021aqds.h

/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <config_cmd_default.h>

#define CONFIG_LS102XA

#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)

#define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE

/*
 * Generic Timer Definitions
 */
#define GENERIC_TIMER_CLK		12500000

#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_CLK_FREQ		100000000
#define CONFIG_DDR_CLK_FREQ		100000000
#define CONFIG_QIXIS_I2C_ACCESS
#else
#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
#endif

#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021aqds/ls102xa_pbi.cfg
#endif

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xe8
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x400

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif

#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE		0x40010000
#define CONFIG_SYS_NO_FLASH
#endif

#ifdef CONFIG_NAND_BOOT
#define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT

#define CONFIG_SPL_TEXT_BASE		0x10000000
#define CONFIG_SPL_MAX_SIZE		0x1a000
#define CONFIG_SPL_STACK		0x1001d000
#define CONFIG_SPL_PAD_TO		0x1c000
#define CONFIG_SYS_TEXT_BASE		0x82000000

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_MONITOR_LEN		0x80000
#endif

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x67f80000
#endif

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_DDR_SPD
#define SPD_EEPROM_ADDRESS		0x51
#define CONFIG_SYS_SPD_BUS_NUM		0

#define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3		/* Use DDR3 memory */
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	4

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DDR_ECC
#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#endif

#define CONFIG_SYS_HAS_SERDES

#define CONFIG_FSL_CAAM			/* Enable CAAM */

#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
	!defined(CONFIG_QSPI_BOOT)
#define CONFIG_U_QE
#endif

/*
 * IFC Definitions
 */
#ifndef CONFIG_QSPI_BOOT
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE		0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)

#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_TRHZ_80)
#define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
					FTIM0_NOR_TEADC(0x5) | \
					FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
					FTIM1_NOR_TRAD_NOR(0x1a) | \
					FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
					FTIM2_NOR_TCH(0x4) | \
					FTIM2_NOR_TWPH(0xe) | \
					FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3		0

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_WRITE_SWAPPED_DATA

#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}

/*
 * NAND Flash Definitions
 */
#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE		0x7e800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	\
				| CSPR_MSEL_NAND	\
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x7) | \
					FTIM0_NAND_TWH(0xa))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0xe)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
					FTIM2_NAND_TREH(0xa) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#endif

/*
 * QIXIS Definitions
 */
#define CONFIG_FSL_QIXIS

#ifdef CONFIG_FSL_QIXIS
#define QIXIS_BASE			0x7fb00000
#define QIXIS_BASE_PHYS			QIXIS_BASE
#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_RST_CTL_RESET		0x44
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
					CSPR_PORT_SIZE_8 | \
					CSPR_MSEL_GPCM | \
					CSPR_V)
#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
					CSOR_NOR_NOR_MODE_AVD_NOR | \
					CSOR_NOR_TRHZ_80)

/*
 * QIXIS Timing parameters for IFC GPCM
 */
#define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
					FTIM0_GPCM_TEADC(0xe) | \
					FTIM0_GPCM_TEAHC(0xe))
#define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
					FTIM2_GPCM_TCH(0xe) | \
					FTIM2_GPCM_TWP(0xf0))
#define CONFIG_SYS_FPGA_FTIM3		0x0
#endif

#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
#endif

/*
 * Serial Port
 */
#ifdef CONFIG_LPUART
#define CONFIG_FSL_LPUART
#define CONFIG_LPUART_32B_REG
#else
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
#endif

#define CONFIG_BAUDRATE			115200

/*
 * I2C
 */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH_CH7301		0xC

/*
 * MMC
 */
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC

#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION

/* QSPI */
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_FSL_QSPI
#define QSPI0_AMBA_BASE			0x40000000
#define FSL_QSPI_FLASH_SIZE		(1 << 24)
#define FSL_QSPI_FLASH_NUM		2

#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SPANSION
#endif

/*
 * USB
 */
#define CONFIG_HAS_FSL_DR_USB

#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI

#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
#endif
#endif

/*
 * Video
 */
#define CONFIG_FSL_DCU_FB

#ifdef CONFIG_FSL_DCU_FB
#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO

#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM	0
#define CONFIG_SYS_I2C_QIXIS_ADDR	0x66
#define CONFIG_SYS_I2C_DVI_ADDR		0x75
#endif

/*
 * eTSEC
 */
#define CONFIG_TSEC_ENET

#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII
#define CONFIG_MII_DEFAULT_TSEC		3
#define CONFIG_TSEC1			1
#define CONFIG_TSEC1_NAME		"eTSEC1"
#define CONFIG_TSEC2			1
#define CONFIG_TSEC2_NAME		"eTSEC2"
#define CONFIG_TSEC3			1
#define CONFIG_TSEC3_NAME		"eTSEC3"

#define TSEC1_PHY_ADDR			1
#define TSEC2_PHY_ADDR			2
#define TSEC3_PHY_ADDR			3

#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0
#define TSEC3_PHYIDX			0

#define CONFIG_ETHPRIME			"eTSEC1"

#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_REALTEK

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2

#define CONFIG_FSL_SGMII_RISER		1
#define SGMII_RISER_PHY_OFFSET		0x1b

#ifdef CONFIG_FSL_SGMII_RISER
#define CONFIG_SYS_TBIPA_VALUE		8
#endif

#endif

/* PCIe */
#define CONFIG_PCI		/* Enable PCI/PCIE */
#define CONFIG_PCIE1		/* PCIE controler 1 */
#define CONFIG_PCIE2		/* PCIE controler 2 */
#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET

#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING

#ifdef CONFIG_QSPI_BOOT
#undef CONFIG_CMD_IMLS
#else
#define CONFIG_CMD_IMLS
#endif

#define CONFIG_ARMV7_NONSEC
#define CONFIG_ARMV7_VIRT
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_LS102XA_NS_ACCESS
#define CONFIG_SMP_PEN_ADDR		0x01ee0200
#define CONFIG_TIMER_CLK_FREQ		12500000
#define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE		128

#define CONFIG_BOOTDELAY		3

#define CONFIG_SYS_QE_FW_ADDR     0x67f40000

#ifdef CONFIG_LPUART
#define CONFIG_EXTRA_ENV_SETTINGS       \
	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	"fdt_high=0xcfffffff\0"         \
	"initrd_high=0xcfffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	"fdt_high=0xcfffffff\0"		\
	"initrd_high=0xcfffffff\0"      \
	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		\
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_CMD_ENV_EXISTS
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x9fffffff

#define CONFIG_SYS_LOAD_ADDR		0x82000000

#define CONFIG_LS102XA_STREAM_ID

/*
 * Stack sizes
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE		(30 * 1024)

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
#endif

/*
 * Environment
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET		0x100000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			0x2000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE			0x2000          /* 8KB */
#define CONFIG_ENV_OFFSET		0x100000        /* 1MB */
#define CONFIG_ENV_SECT_SIZE		0x10000
#elif defined(CONFIG_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
#endif

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_CMD_BOOTZ

#define CONFIG_MISC_INIT_R

/* Hash command with SHA acceleration supported in hardware */
#define CONFIG_CMD_HASH
#define CONFIG_SHA_HW_ACCEL

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CMD_BLOB
#endif

#endif
Commit	Line	Data
550e3dc0 WH	1	/*
	2	* Copyright 2014 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
	10	#include <config_cmd_default.h>
	11
	12	#define CONFIG_LS102XA
	13
	14	#define CONFIG_SYS_GENERIC_BOARD
	15
	16	#define CONFIG_DISPLAY_CPUINFO
	17	#define CONFIG_DISPLAY_BOARDINFO
	18
	19	#define CONFIG_SKIP_LOWLEVEL_INIT
	20	#define CONFIG_BOARD_EARLY_INIT_F
	21
	22	/*
	23	* Size of malloc() pool
	24	*/
	25	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
	26
	27	#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
	28	#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
	29
	30	/*
	31	* Generic Timer Definitions
	32	*/
	33	#define GENERIC_TIMER_CLK 12500000
	34
	35	#ifndef __ASSEMBLY__
	36	unsigned long get_board_sys_clk(void);
	37	unsigned long get_board_ddr_clk(void);
	38	#endif
	39
d612f0ab AW	40	#ifdef CONFIG_QSPI_BOOT
	41	#define CONFIG_SYS_CLK_FREQ 100000000
	42	#define CONFIG_DDR_CLK_FREQ 100000000
	43	#define CONFIG_QIXIS_I2C_ACCESS
	44	#else
550e3dc0 WH	45	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
550e3dc0 WH	46	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
d612f0ab	47	#endif
550e3dc0	48
86949c2b AW	49	#ifdef CONFIG_RAMBOOT_PBL
	50	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
	51	#endif
	52
	53	#ifdef CONFIG_SD_BOOT
	54	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
	55	#define CONFIG_SPL_FRAMEWORK
	56	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
	57	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	58	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	59	#define CONFIG_SPL_ENV_SUPPORT
	60	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	61	#define CONFIG_SPL_I2C_SUPPORT
	62	#define CONFIG_SPL_WATCHDOG_SUPPORT
	63	#define CONFIG_SPL_SERIAL_SUPPORT
	64	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	65	#define CONFIG_SPL_MMC_SUPPORT
	66	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
	67	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
	68
	69	#define CONFIG_SPL_TEXT_BASE 0x10000000
	70	#define CONFIG_SPL_MAX_SIZE 0x1a000
	71	#define CONFIG_SPL_STACK 0x1001d000
	72	#define CONFIG_SPL_PAD_TO 0x1c000
	73	#define CONFIG_SYS_TEXT_BASE 0x82000000
	74
	75	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	76	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	77	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	78	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	79	#define CONFIG_SYS_MONITOR_LEN 0x80000
	80	#endif
	81
d612f0ab AW	82	#ifdef CONFIG_QSPI_BOOT
	83	#define CONFIG_SYS_TEXT_BASE 0x40010000
	84	#define CONFIG_SYS_NO_FLASH
	85	#endif
	86
8ab967b6 AW	87	#ifdef CONFIG_NAND_BOOT
	88	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
	89	#define CONFIG_SPL_FRAMEWORK
	90	#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
	91	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	92	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	93	#define CONFIG_SPL_ENV_SUPPORT
	94	#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	95	#define CONFIG_SPL_I2C_SUPPORT
	96	#define CONFIG_SPL_WATCHDOG_SUPPORT
	97	#define CONFIG_SPL_SERIAL_SUPPORT
	98	#define CONFIG_SPL_NAND_SUPPORT
	99	#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	100
	101	#define CONFIG_SPL_TEXT_BASE 0x10000000
	102	#define CONFIG_SPL_MAX_SIZE 0x1a000
	103	#define CONFIG_SPL_STACK 0x1001d000
	104	#define CONFIG_SPL_PAD_TO 0x1c000
	105	#define CONFIG_SYS_TEXT_BASE 0x82000000
	106
	107	#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
	108	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
	109	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	110	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
	111	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	112
	113	#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
	114	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	115	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	116	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	117	#define CONFIG_SYS_MONITOR_LEN 0x80000
	118	#endif
	119
550e3dc0 WH	120	#ifndef CONFIG_SYS_TEXT_BASE
	121	#define CONFIG_SYS_TEXT_BASE 0x67f80000
	122	#endif
	123
	124	#define CONFIG_NR_DRAM_BANKS 1
	125
	126	#define CONFIG_DDR_SPD
	127	#define SPD_EEPROM_ADDRESS 0x51
	128	#define CONFIG_SYS_SPD_BUS_NUM 0
550e3dc0 WH	129
550e3dc0 WH	130	#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
c7eae7fc	131	#ifndef CONFIG_SYS_FSL_DDR4
550e3dc0	132	#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
c7eae7fc YS	133	#define CONFIG_SYS_DDR_RAW_TIMING
c7eae7fc YS	134	#endif
550e3dc0 WH	135	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	136	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	137
	138	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
	139	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	140
	141	#define CONFIG_DDR_ECC
	142	#ifdef CONFIG_DDR_ECC
	143	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	144	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	145	#endif
	146
	147	#define CONFIG_SYS_HAS_SERDES
	148
4ba4a095	149	#define CONFIG_FSL_CAAM /* Enable CAAM */
63e75fd7	150
4c59ab9c AW	151	#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
4c59ab9c AW	152	!defined(CONFIG_QSPI_BOOT)
63e75fd7 ZQ	153	#define CONFIG_U_QE
	154	#endif
	155
550e3dc0 WH	156	/*
	157	* IFC Definitions
	158	*/
d612f0ab	159	#ifndef CONFIG_QSPI_BOOT
550e3dc0 WH	160	#define CONFIG_FSL_IFC
	161	#define CONFIG_SYS_FLASH_BASE 0x60000000
	162	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	163
	164	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	165	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	166	CSPR_PORT_SIZE_16 \| \
	167	CSPR_MSEL_NOR \| \
	168	CSPR_V)
	169	#define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
	170	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	171	+ 0x8000000) \| \
	172	CSPR_PORT_SIZE_16 \| \
	173	CSPR_MSEL_NOR \| \
	174	CSPR_V)
	175	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	176
	177	#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	178	CSOR_NOR_TRHZ_80)
	179	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	180	FTIM0_NOR_TEADC(0x5) \| \
	181	FTIM0_NOR_TEAHC(0x5))
	182	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	183	FTIM1_NOR_TRAD_NOR(0x1a) \| \
	184	FTIM1_NOR_TSEQRAD_NOR(0x13))
	185	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	186	FTIM2_NOR_TCH(0x4) \| \
	187	FTIM2_NOR_TWPH(0xe) \| \
	188	FTIM2_NOR_TWP(0x1c))
	189	#define CONFIG_SYS_NOR_FTIM3 0
	190
	191	#define CONFIG_FLASH_CFI_DRIVER
	192	#define CONFIG_SYS_FLASH_CFI
	193	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	194	#define CONFIG_SYS_FLASH_QUIET_TEST
	195	#define CONFIG_FLASH_SHOW_PROGRESS 45
	196	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
272c5265	197	#define CONFIG_SYS_WRITE_SWAPPED_DATA
550e3dc0 WH	198
	199	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	200	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	201	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	202	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	203
	204	#define CONFIG_SYS_FLASH_EMPTY_INFO
	205	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
	206	CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
	207
	208	/*
	209	* NAND Flash Definitions
	210	*/
	211	#define CONFIG_NAND_FSL_IFC
	212
	213	#define CONFIG_SYS_NAND_BASE 0x7e800000
	214	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	215
	216	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	217
	218	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	219	\| CSPR_PORT_SIZE_8 \
	220	\| CSPR_MSEL_NAND \
	221	\| CSPR_V)
	222	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	223	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	224	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	225	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	226	\| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
	227	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	228	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	229	\| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
	230
	231	#define CONFIG_SYS_NAND_ONFI_DETECTION
	232
	233	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) \| \
	234	FTIM0_NAND_TWP(0x18) \| \
	235	FTIM0_NAND_TWCHT(0x7) \| \
	236	FTIM0_NAND_TWH(0xa))
	237	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	238	FTIM1_NAND_TWBE(0x39) \| \
	239	FTIM1_NAND_TRR(0xe) \| \
	240	FTIM1_NAND_TRP(0x18))
	241	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) \| \
	242	FTIM2_NAND_TREH(0xa) \| \
	243	FTIM2_NAND_TWHRE(0x1e))
	244	#define CONFIG_SYS_NAND_FTIM3 0x0
	245
	246	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	247	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	248	#define CONFIG_MTD_NAND_VERIFY_WRITE
	249	#define CONFIG_CMD_NAND
	250
	251	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
d612f0ab	252	#endif
550e3dc0 WH	253
	254	/*
	255	* QIXIS Definitions
	256	*/
	257	#define CONFIG_FSL_QIXIS
	258
	259	#ifdef CONFIG_FSL_QIXIS
	260	#define QIXIS_BASE 0x7fb00000
	261	#define QIXIS_BASE_PHYS QIXIS_BASE
	262	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
	263	#define QIXIS_LBMAP_SWITCH 6
	264	#define QIXIS_LBMAP_MASK 0x0f
	265	#define QIXIS_LBMAP_SHIFT 0
	266	#define QIXIS_LBMAP_DFLTBANK 0x00
	267	#define QIXIS_LBMAP_ALTBANK 0x04
	268	#define QIXIS_RST_CTL_RESET 0x44
	269	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	270	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	271	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	272
	273	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	274	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \| \
	275	CSPR_PORT_SIZE_8 \| \
	276	CSPR_MSEL_GPCM \| \
	277	CSPR_V)
	278	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
	279	#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) \| \
	280	CSOR_NOR_NOR_MODE_AVD_NOR \| \
	281	CSOR_NOR_TRHZ_80)
	282
	283	/*
	284	* QIXIS Timing parameters for IFC GPCM
	285	*/
	286	#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) \| \
	287	FTIM0_GPCM_TEADC(0xe) \| \
	288	FTIM0_GPCM_TEAHC(0xe))
	289	#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) \| \
	290	FTIM1_GPCM_TRAD(0x1f))
	291	#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) \| \
	292	FTIM2_GPCM_TCH(0xe) \| \
	293	FTIM2_GPCM_TWP(0xf0))
	294	#define CONFIG_SYS_FPGA_FTIM3 0x0
	295	#endif
	296
8ab967b6 AW	297	#if defined(CONFIG_NAND_BOOT)
	298	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	299	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	300	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	301	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	302	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	303	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	304	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	305	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	306	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	307	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	308	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	309	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	310	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	311	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	312	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	313	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	314	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	315	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	316	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	317	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	318	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	319	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	320	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	321	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	322	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	323	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	324	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	325	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	326	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	327	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	328	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	329	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
	330	#else
550e3dc0 WH	331	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	332	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	333	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	334	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	335	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	336	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	337	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	338	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	339	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	340	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	341	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	342	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	343	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	344	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	345	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	346	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	347	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	348	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	349	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	350	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	351	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	352	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	353	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	354	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	355	#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
	356	#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
	357	#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
	358	#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
	359	#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
	360	#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
	361	#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
	362	#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
8ab967b6	363	#endif
550e3dc0 WH	364
	365	/*
	366	* Serial Port
	367	*/
8fc2121a AW	368	#ifdef CONFIG_LPUART
	369	#define CONFIG_FSL_LPUART
	370	#define CONFIG_LPUART_32B_REG
	371	#else
550e3dc0 WH	372	#define CONFIG_CONS_INDEX 1
	373	#define CONFIG_SYS_NS16550
	374	#define CONFIG_SYS_NS16550_SERIAL
	375	#define CONFIG_SYS_NS16550_REG_SIZE 1
	376	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
8fc2121a	377	#endif
550e3dc0 WH	378
	379	#define CONFIG_BAUDRATE 115200
	380
	381	/*
	382	* I2C
	383	*/
	384	#define CONFIG_CMD_I2C
	385	#define CONFIG_SYS_I2C
	386	#define CONFIG_SYS_I2C_MXC
	387
	388	/*
	389	* I2C bus multiplexer
	390	*/
	391	#define I2C_MUX_PCA_ADDR_PRI 0x77
	392	#define I2C_MUX_CH_DEFAULT 0x8
dd04832d	393	#define I2C_MUX_CH_CH7301 0xC
550e3dc0 WH	394
	395	/*
	396	* MMC
	397	*/
	398	#define CONFIG_MMC
	399	#define CONFIG_CMD_MMC
	400	#define CONFIG_FSL_ESDHC
	401	#define CONFIG_GENERIC_MMC
	402
8251ed23 AW	403	#define CONFIG_CMD_FAT
	404	#define CONFIG_DOS_PARTITION
	405
d612f0ab AW	406	/* QSPI */
	407	#ifdef CONFIG_QSPI_BOOT
	408	#define CONFIG_FSL_QSPI
	409	#define QSPI0_AMBA_BASE 0x40000000
	410	#define FSL_QSPI_FLASH_SIZE (1 << 24)
	411	#define FSL_QSPI_FLASH_NUM 2
	412
	413	#define CONFIG_CMD_SF
	414	#define CONFIG_SPI_FLASH
	415	#define CONFIG_SPI_FLASH_SPANSION
	416	#endif
	417
8776cb20 NB	418	/*
	419	* USB
	420	*/
	421	#define CONFIG_HAS_FSL_DR_USB
	422
	423	#ifdef CONFIG_HAS_FSL_DR_USB
	424	#define CONFIG_USB_EHCI
	425
	426	#ifdef CONFIG_USB_EHCI
	427	#define CONFIG_CMD_USB
	428	#define CONFIG_USB_STORAGE
	429	#define CONFIG_USB_EHCI_FSL
	430	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	431	#define CONFIG_CMD_EXT2
	432	#endif
	433	#endif
	434
dd04832d XL	435	/*
	436	* Video
	437	*/
	438	#define CONFIG_FSL_DCU_FB
	439
	440	#ifdef CONFIG_FSL_DCU_FB
	441	#define CONFIG_VIDEO
	442	#define CONFIG_CMD_BMP
	443	#define CONFIG_CFB_CONSOLE
	444	#define CONFIG_VGA_AS_SINGLE_DEVICE
	445	#define CONFIG_VIDEO_LOGO
	446	#define CONFIG_VIDEO_BMP_LOGO
	447
	448	#define CONFIG_FSL_DIU_CH7301
	449	#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
	450	#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
	451	#define CONFIG_SYS_I2C_DVI_ADDR 0x75
	452	#endif
	453
550e3dc0 WH	454	/*
	455	* eTSEC
	456	*/
	457	#define CONFIG_TSEC_ENET
	458
	459	#ifdef CONFIG_TSEC_ENET
	460	#define CONFIG_MII
	461	#define CONFIG_MII_DEFAULT_TSEC 3
	462	#define CONFIG_TSEC1 1
	463	#define CONFIG_TSEC1_NAME "eTSEC1"
	464	#define CONFIG_TSEC2 1
	465	#define CONFIG_TSEC2_NAME "eTSEC2"
	466	#define CONFIG_TSEC3 1
	467	#define CONFIG_TSEC3_NAME "eTSEC3"
	468
	469	#define TSEC1_PHY_ADDR 1
	470	#define TSEC2_PHY_ADDR 2
	471	#define TSEC3_PHY_ADDR 3
	472
	473	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	474	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	475	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	476
	477	#define TSEC1_PHYIDX 0
	478	#define TSEC2_PHYIDX 0
	479	#define TSEC3_PHYIDX 0
	480
	481	#define CONFIG_ETHPRIME "eTSEC1"
	482
	483	#define CONFIG_PHY_GIGE
	484	#define CONFIG_PHYLIB
	485	#define CONFIG_PHY_REALTEK
	486
	487	#define CONFIG_HAS_ETH0
	488	#define CONFIG_HAS_ETH1
	489	#define CONFIG_HAS_ETH2
	490
	491	#define CONFIG_FSL_SGMII_RISER 1
	492	#define SGMII_RISER_PHY_OFFSET 0x1b
	493
	494	#ifdef CONFIG_FSL_SGMII_RISER
	495	#define CONFIG_SYS_TBIPA_VALUE 8
	496	#endif
	497
	498	#endif
da419027 ML	499
	500	/* PCIe */
	501	#define CONFIG_PCI /* Enable PCI/PCIE */
	502	#define CONFIG_PCIE1 /* PCIE controler 1 */
	503	#define CONFIG_PCIE2 /* PCIE controler 2 */
	504	#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
	505	#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
	506
550e3dc0 WH	507	#define CONFIG_CMD_PING
	508	#define CONFIG_CMD_DHCP
	509	#define CONFIG_CMD_MII
	510	#define CONFIG_CMD_NET
	511
	512	#define CONFIG_CMDLINE_TAG
	513	#define CONFIG_CMDLINE_EDITING
86949c2b	514
d612f0ab AW	515	#ifdef CONFIG_QSPI_BOOT
	516	#undef CONFIG_CMD_IMLS
	517	#else
550e3dc0	518	#define CONFIG_CMD_IMLS
d612f0ab	519	#endif
550e3dc0	520
1a2826f6 XL	521	#define CONFIG_ARMV7_NONSEC
	522	#define CONFIG_ARMV7_VIRT
	523	#define CONFIG_PEN_ADDR_BIG_ENDIAN
e87f3b30	524	#define CONFIG_LS102XA_NS_ACCESS
1a2826f6 XL	525	#define CONFIG_SMP_PEN_ADDR 0x01ee0200
	526	#define CONFIG_TIMER_CLK_FREQ 12500000
	527	#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
	528
550e3dc0 WH	529	#define CONFIG_HWCONFIG
	530	#define HWCONFIG_BUFFER_SIZE 128
	531
	532	#define CONFIG_BOOTDELAY 3
	533
63e75fd7 ZQ	534	#define CONFIG_SYS_QE_FW_ADDR 0x67f40000
63e75fd7 ZQ	535
8fc2121a AW	536	#ifdef CONFIG_LPUART
	537	#define CONFIG_EXTRA_ENV_SETTINGS \
	538	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
	539	"fdt_high=0xcfffffff\0" \
	540	"initrd_high=0xcfffffff\0" \
	541	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
	542	#else
550e3dc0 WH	543	#define CONFIG_EXTRA_ENV_SETTINGS \
	544	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
	545	"fdt_high=0xcfffffff\0" \
	546	"initrd_high=0xcfffffff\0" \
	547	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
8fc2121a	548	#endif
550e3dc0 WH	549
	550	/*
	551	* Miscellaneous configurable options
	552	*/
	553	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	554	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	555	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
550e3dc0 WH	556	#define CONFIG_AUTO_COMPLETE
	557	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	558	#define CONFIG_SYS_PBSIZE \
	559	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	560	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	561	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	562
	563	#define CONFIG_CMD_ENV_EXISTS
	564	#define CONFIG_CMD_GREPENV
	565	#define CONFIG_CMD_MEMINFO
	566	#define CONFIG_CMD_MEMTEST
	567	#define CONFIG_SYS_MEMTEST_START 0x80000000
	568	#define CONFIG_SYS_MEMTEST_END 0x9fffffff
	569
	570	#define CONFIG_SYS_LOAD_ADDR 0x82000000
550e3dc0	571
660673af XL	572	#define CONFIG_LS102XA_STREAM_ID
660673af XL	573
550e3dc0 WH	574	/*
	575	* Stack sizes
	576	* The stack sizes are set up in start.S using the settings below
	577	*/
	578	#define CONFIG_STACKSIZE (30 * 1024)
	579
	580	#define CONFIG_SYS_INIT_SP_OFFSET \
	581	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	582	#define CONFIG_SYS_INIT_SP_ADDR \
	583	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	584
86949c2b AW	585	#ifdef CONFIG_SPL_BUILD
	586	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	587	#else
550e3dc0	588	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
86949c2b	589	#endif
550e3dc0 WH	590
	591	/*
	592	* Environment
	593	*/
	594	#define CONFIG_ENV_OVERWRITE
	595
86949c2b AW	596	#if defined(CONFIG_SD_BOOT)
	597	#define CONFIG_ENV_OFFSET 0x100000
	598	#define CONFIG_ENV_IS_IN_MMC
	599	#define CONFIG_SYS_MMC_ENV_DEV 0
	600	#define CONFIG_ENV_SIZE 0x2000
d612f0ab AW	601	#elif defined(CONFIG_QSPI_BOOT)
	602	#define CONFIG_ENV_IS_IN_SPI_FLASH
	603	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	604	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	605	#define CONFIG_ENV_SECT_SIZE 0x10000
8ab967b6 AW	606	#elif defined(CONFIG_NAND_BOOT)
	607	#define CONFIG_ENV_IS_IN_NAND
	608	#define CONFIG_ENV_SIZE 0x2000
	609	#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
86949c2b	610	#else
550e3dc0 WH	611	#define CONFIG_ENV_IS_IN_FLASH
	612	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	613	#define CONFIG_ENV_SIZE 0x2000
	614	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
86949c2b	615	#endif
550e3dc0 WH	616
	617	#define CONFIG_OF_LIBFDT
	618	#define CONFIG_OF_BOARD_SETUP
	619	#define CONFIG_CMD_BOOTZ
	620
4ba4a095 RG	621	#define CONFIG_MISC_INIT_R
	622
	623	/* Hash command with SHA acceleration supported in hardware */
	624	#define CONFIG_CMD_HASH
	625	#define CONFIG_SHA_HW_ACCEL
	626
ba474020 RG	627	#ifdef CONFIG_SECURE_BOOT
	628	#define CONFIG_CMD_BLOB
	629	#endif
	630
550e3dc0	631	#endif