[J-u-boot.git] / include / configs / hermes.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
#define CONFIG_HERMES		1	/* ...on a HERMES-PRO board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/

#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/
/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000	/* Non-Standard value!	*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#ifdef	DEBUG
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x4000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 * +0x0004
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * +0x0000 => 0x000000C0
 */
#define CONFIG_SYS_SIUMCR	0

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 * +0x0200 => 0x00C2
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 * +0x0240 => 0x0082
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* +0x0286 => 0x00B0D0C0 */
#define CONFIG_SYS_PLPRCR							\
		(	(11 << PLPRCR_MF_SHIFT) |			\
			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* +0x0282 => 0x03800000 */
#define CONFIG_SYS_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* +0x0220 => 0x00C3 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
/* +0x09C4 => TIMEP=1 */
#define CONFIG_SYS_RCCR 0x0100

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RMDS 0

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/

/* used to re-map FLASH
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* allow for max 4 MB of Flash */
#define CONFIG_SYS_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0	*/
#define CONFIG_SYS_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
				 OR_SCY_5_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
/* 8 bit, bank valid */
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR1/OR1 - SDRAM
 *
 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 */
#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define CONFIG_SYS_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
 */
#define HPRO2_BASE		0xE0000000
#define HPRO2_OR_AM		0xFFFF8000
#define HPRO2_TIMING		0x00000934

#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
#define CONFIG_SYS_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3/OR3: not used
 * BR4/OR4: not used
 * BR5/OR5: not used
 * BR6/OR6: not used
 * BR7/OR7: not used
 */

/*
 * MAMR settings for SDRAM
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
#endif	/* __CONFIG_H */
Commit	Line	Data
e0648062 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
	37	#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0xFE000000
2ae18241 WD	40
e0648062 WD	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	42	#undef CONFIG_8xx_CONS_SMC2
	43	#undef CONFIG_8xx_CONS_NONE
	44	#define CONFIG_BAUDRATE 9600
	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
	48	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	49	#endif
	50
	51	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	52
	53	#define CONFIG_BOARD_TYPES 1 /* support board types */
	54
	55	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
	56
	57	#undef CONFIG_BOOTARGS
	58	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	59	"bootp; " \
	60	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	61	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
e0648062 WD	62	"bootm"
	63
	64	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	65	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
e0648062 WD	66
	67	#undef CONFIG_WATCHDOG /* watchdog disabled */
	68
e0648062	69
48d5d102 JL	70	/*
	71	* Command line configuration.
	72	*/
	73	#include <config_cmd_default.h>
e0648062	74
e0648062	75
2fd90ce5 JL	76	/*
	77	* BOOTP options
	78	*/
	79	#define CONFIG_BOOTP_SUBNETMASK
	80	#define CONFIG_BOOTP_GATEWAY
	81	#define CONFIG_BOOTP_HOSTNAME
	82	#define CONFIG_BOOTP_BOOTPATH
	83
e0648062 WD	84
	85	/*
	86	* Miscellaneous configurable options
	87	*/
6d0f6bcf JCPV	88	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	89	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
48d5d102	90	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	91	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e0648062	92	#else
6d0f6bcf	93	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e0648062	94	#endif
6d0f6bcf JCPV	95	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	96	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	97	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e0648062	98
6d0f6bcf JCPV	99	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	100	#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
e0648062	101
6d0f6bcf	102	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
e0648062	103
6d0f6bcf	104	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
e0648062	105
6d0f6bcf	106	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e0648062	107
6d0f6bcf	108	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
e0648062	109
6d0f6bcf	110	#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
e0648062 WD	111	/*
	112	* Low Level Configuration Settings
	113	* (address mappings, register initial values, etc.)
	114	* You should know what you are doing if you make changes here.
	115	*/
	116	/*-----------------------------------------------------------------------
	117	* Internal Memory Mapped Register
	118	*/
6d0f6bcf	119	#define CONFIG_SYS_IMMR 0xFF000000 /* Non-Standard value! */
e0648062 WD	120
	121	/*-----------------------------------------------------------------------
	122	* Definitions for initial stack pointer and data area (in DPRAM)
	123	*/
6d0f6bcf	124	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	125	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
6d0f6bcf	126	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	127	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	128	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e0648062 WD	129
	130	/*-----------------------------------------------------------------------
	131	* Start addresses for the final memory configuration
	132	* (Set up by the startup code)
6d0f6bcf	133	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e0648062	134	*/
6d0f6bcf JCPV	135	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	136	#define CONFIG_SYS_FLASH_BASE 0xFE000000
e0648062	137	#ifdef DEBUG
6d0f6bcf	138	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e0648062	139	#else
6d0f6bcf	140	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
e0648062	141	#endif
6d0f6bcf JCPV	142	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	143	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e0648062 WD	144
	145	/*
	146	* For booting Linux, the board info and command line data
	147	* have to be in the first 8 MB of memory, since this is
	148	* the maximum mapped by the Linux kernel during initialization.
	149	*/
6d0f6bcf	150	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e0648062 WD	151	/*-----------------------------------------------------------------------
	152	* FLASH organization
	153	*/
6d0f6bcf JCPV	154	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	155	#define CONFIG_SYS_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
e0648062	156
6d0f6bcf JCPV	157	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	158	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
e0648062	159
5a1aceb0	160	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	161	#define CONFIG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
0e8d1586 JCPV	162	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
e0648062 WD	163	/*-----------------------------------------------------------------------
	164	* Cache Configuration
	165	*/
6d0f6bcf	166	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
48d5d102	167	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	168	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
e0648062 WD	169	#endif
	170
	171	/*-----------------------------------------------------------------------
	172	* SYPCR - System Protection Control 11-9
	173	* SYPCR can only be written once after reset!
	174	*-----------------------------------------------------------------------
	175	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	176	* +0x0004
	177	*/
	178	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	179	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
e0648062 WD	180	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
e0648062 WD	181	#else
6d0f6bcf	182	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
e0648062 WD	183	#endif
	184
	185	/*-----------------------------------------------------------------------
	186	* SIUMCR - SIU Module Configuration 11-6
	187	*-----------------------------------------------------------------------
	188	* +0x0000 => 0x000000C0
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_SIUMCR 0
e0648062 WD	191
	192	/*-----------------------------------------------------------------------
	193	* TBSCR - Time Base Status and Control 11-26
	194	*-----------------------------------------------------------------------
	195	* Clear Reference Interrupt Status, Timebase freezing enabled
	196	* +0x0200 => 0x00C2
	197	*/
6d0f6bcf	198	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
e0648062 WD	199
	200	/*-----------------------------------------------------------------------
	201	* PISCR - Periodic Interrupt Status and Control 11-31
	202	*-----------------------------------------------------------------------
	203	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	204	* +0x0240 => 0x0082
	205	*/
6d0f6bcf	206	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
e0648062 WD	207
	208	/*-----------------------------------------------------------------------
	209	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	210	*-----------------------------------------------------------------------
	211	* Reset PLL lock status sticky bit, timer expired status bit and timer
	212	* interrupt status bit, set PLL multiplication factor !
	213	*/
	214	/* +0x0286 => 0x00B0D0C0 */
6d0f6bcf	215	#define CONFIG_SYS_PLPRCR \
e0648062 WD	216	( (11 << PLPRCR_MF_SHIFT) \| \
	217	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST \| \
	218	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
	219	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
	220	)
	221
	222	/*-----------------------------------------------------------------------
	223	* SCCR - System Clock and reset Control Register 15-27
	224	*-----------------------------------------------------------------------
	225	* Set clock output, timebase and RTC source and divider,
	226	* power management and some other internal clocks
	227	*/
	228	#define SCCR_MASK SCCR_EBDF11
	229	/* +0x0282 => 0x03800000 */
6d0f6bcf	230	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_TBS \| \
e0648062	231	SCCR_RTDIV \| SCCR_RTSEL \| \
53677ef1	232	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
e0648062 WD	233	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
	234	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
	235	SCCR_DFNH000)
	236
	237	/*-----------------------------------------------------------------------
	238	* RTCSC - Real-Time Clock Status and Control Register 11-27
	239	*-----------------------------------------------------------------------
	240	*/
	241	/* +0x0220 => 0x00C3 */
6d0f6bcf	242	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
e0648062 WD	243
	244
	245	/*-----------------------------------------------------------------------
	246	* RCCR - RISC Controller Configuration Register 19-4
	247	*-----------------------------------------------------------------------
	248	*/
	249	/* +0x09C4 => TIMEP=1 */
6d0f6bcf	250	#define CONFIG_SYS_RCCR 0x0100
e0648062 WD	251
	252	/*-----------------------------------------------------------------------
	253	* RMDS - RISC Microcode Development Support Control Register
	254	*-----------------------------------------------------------------------
	255	*/
6d0f6bcf	256	#define CONFIG_SYS_RMDS 0
e0648062 WD	257
	258	/*-----------------------------------------------------------------------
	259	*
	260	*-----------------------------------------------------------------------
	261	*
	262	*/
6d0f6bcf	263	#define CONFIG_SYS_DER 0
e0648062 WD	264
	265	/*
	266	* Init Memory Controller:
	267	*
	268	* BR0 and OR0 (FLASH)
	269	*/
	270
	271	#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
	272
	273	/* used to re-map FLASH
	274	* restrict access enough to keep SRAM working (if any)
	275	* but not too much to meddle with FLASH accesses
	276	*/
	277	/* allow for max 4 MB of Flash */
6d0f6bcf JCPV	278	#define CONFIG_SYS_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
6d0f6bcf JCPV	279	#define CONFIG_SYS_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
e0648062 WD	280
e0648062 WD	281	/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
6d0f6bcf	282	#define CONFIG_SYS_OR_TIMING_FLASH ( OR_CSNT_SAM \| /OR_ACS_DIV4 \|/ OR_BI \| \
e0648062 WD	283	OR_SCY_5_CLK \| OR_TRLX)
e0648062 WD	284
6d0f6bcf JCPV	285	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	286	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
e0648062	287	/* 8 bit, bank valid */
6d0f6bcf	288	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
e0648062 WD	289
	290	/*
	291	* BR1/OR1 - SDRAM
	292	*
	293	* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
	294	*/
	295	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
	296	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
	297	#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
	298
	299	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
	300
6d0f6bcf JCPV	301	#define CONFIG_SYS_OR1_PRELIM (SDRAM_PRELIM_OR_AM \| SDRAM_TIMING )
6d0f6bcf JCPV	302	#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e0648062 WD	303
	304	/*
	305	* BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
	306	*/
	307	#define HPRO2_BASE 0xE0000000
	308	#define HPRO2_OR_AM 0xFFFF8000
	309	#define HPRO2_TIMING 0x00000934
	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_OR2 (HPRO2_OR_AM \| HPRO2_TIMING)
6d0f6bcf JCPV	312	#define CONFIG_SYS_BR2 ((HPRO2_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
e0648062 WD	313
	314	/*
	315	* BR3/OR3: not used
	316	* BR4/OR4: not used
	317	* BR5/OR5: not used
	318	* BR6/OR6: not used
	319	* BR7/OR7: not used
	320	*/
	321
	322	/*
	323	* MAMR settings for SDRAM
	324	*/
	325
	326	/* periodic timer for refresh */
6d0f6bcf	327	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
e0648062 WD	328
e0648062 WD	329	/* 8 column SDRAM */
6d0f6bcf	330	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e0648062 WD	331	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	332	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	333	/* 9 column SDRAM */
6d0f6bcf	334	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e0648062 WD	335	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
e0648062 WD	336	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
e0648062	337	#endif /* __CONFIG_H */