[J-u-boot.git] / include / configs / RRvision.h

/*
 * (C) Copyright 2000, 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_RRVISION		1	/* ...on a RRvision board	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_8xx_GCLK_FREQ 64000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_PREBOOT	"setenv stdout serial"

#undef	CONFIG_BOOTARGS
#define CONFIG_ETHADDR                00:50:C2:00:E0:70
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
#define CONFIG_IPADDR                 10.0.0.5
#define CONFIG_SERVERIP               10.0.0.2
#define CONFIG_NETMASK                255.0.0.0
#define CONFIG_ROOTPATH               /opt/eldk/ppc_8xx
#define CONFIG_BOOTCOMMAND            "run flash_self"

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}"	\
		":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0"	\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
	"update=protect off 1:0-8;era 1:0-8;"				\
		"cp.b 100000 40000000 ${filesize};"			\
		"setenv filesize;saveenv\0"				\
	"kernel_addr=40040000\0"					\
	"ramdisk_addr=40100000\0"					\
	"kernel_img=/tftpboot/uImage\0"					\
	"kernel_load=tftp 200000 ${kernel_img}\0"			\
	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0"		\
	"flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0"	\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"


#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#undef	CONFIG_STATUS_LED		/* disturbs display		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


#ifndef CONFIG_LCD
#define CONFIG_VIDEO		1	/* To enable the video initialization */

/* Video related */
#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7179		1	/* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7179_ADDR	0x2A	/* ALSB to ground */
#endif

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C			/* I2C bit-banged		*/

# define CONFIG_SYS_I2C_SPEED		50000	/* 50 kHz is supposed to work	*/
# define CONFIG_SYS_I2C_SLAVE		0xFE

#ifdef CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(1)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SOFT_I2C */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DATE

#undef CONFIG_CMD_PCMCIA
#undef CONFIG_CMD_IDE


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

/* timeout values are in ticks = ms */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(120*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	(1 * CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */

/* for 64 MHz, we use a 16 MHz clock * 4 */
#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_3_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#ifndef	CONFIG_CAN_DRIVER
#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
					BR_PS_8 | BR_MS_UPMB | BR_V )
#endif	/* CONFIG_CAN_DRIVER */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#define CONFIG_SYS_MAMR_PTA		129

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)


#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	37	#define CONFIG_RRVISION 1 /* ...on a RRvision board */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	40
e2211743 WD	41	#define CONFIG_8xx_GCLK_FREQ 64000000
	42
	43	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	44	#undef CONFIG_8xx_CONS_SMC2
	45	#undef CONFIG_8xx_CONS_NONE
	46	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	47	#if 0
	48	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	49	#else
	50	#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
	51	#endif
	52
	53	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	54
	55	#define CONFIG_PREBOOT "setenv stdout serial"
	56
	57	#undef CONFIG_BOOTARGS
	58	#define CONFIG_ETHADDR 00:50:C2:00:E0:70
	59	#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
	60	#define CONFIG_IPADDR 10.0.0.5
	61	#define CONFIG_SERVERIP 10.0.0.2
	62	#define CONFIG_NETMASK 255.0.0.0
	63	#define CONFIG_ROOTPATH /opt/eldk/ppc_8xx
	64	#define CONFIG_BOOTCOMMAND "run flash_self"
	65
	66	#define CONFIG_EXTRA_ENV_SETTINGS \
	67	"netdev=eth0\0" \
	68	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	69	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b WD	70	"nfsroot=${serverip}:${rootpath}\0" \
	71	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}" \
	72	":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
	73	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
e2211743 WD	74	"load=tftp 100000 /tftpboot/u-boot.bin\0" \
e2211743 WD	75	"update=protect off 1:0-8;era 1:0-8;" \
fe126d8b	76	"cp.b 100000 40000000 ${filesize};" \
e2211743 WD	77	"setenv filesize;saveenv\0" \
	78	"kernel_addr=40040000\0" \
	79	"ramdisk_addr=40100000\0" \
3bac3513	80	"kernel_img=/tftpboot/uImage\0" \
fe126d8b	81	"kernel_load=tftp 200000 ${kernel_img}\0" \
e2211743	82	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
fe126d8b	83	"flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0" \
e2211743	84	"flash_self=run ramargs addip addtty;" \
fe126d8b	85	"bootm ${kernel_addr} ${ramdisk_addr}\0"
e2211743 WD	86
	87
	88	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	89	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
e2211743 WD	90
	91	#undef CONFIG_WATCHDOG /* watchdog disabled */
	92
	93	#undef CONFIG_STATUS_LED /* disturbs display */
	94
	95	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	96
18225e8d JL	97	/*
	98	* BOOTP options
	99	*/
	100	#define CONFIG_BOOTP_SUBNETMASK
	101	#define CONFIG_BOOTP_GATEWAY
	102	#define CONFIG_BOOTP_HOSTNAME
	103	#define CONFIG_BOOTP_BOOTPATH
	104	#define CONFIG_BOOTP_BOOTFILESIZE
	105
e2211743 WD	106
	107	#define CONFIG_MAC_PARTITION
	108	#define CONFIG_DOS_PARTITION
	109
	110	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	111
	112
8564acf9	113	#ifndef CONFIG_LCD
e2211743 WD	114	#define CONFIG_VIDEO 1 /* To enable the video initialization */
	115
	116	/* Video related */
	117	#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
8564acf9 WD	118	#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
8564acf9 WD	119	#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
e2211743 WD	120	#endif
	121
	122	/* enable I2C and select the hardware/software driver */
	123	#undef CONFIG_HARD_I2C /* I2C with hardware support */
53677ef1	124	#define CONFIG_SOFT_I2C /* I2C bit-banged */
e2211743	125
6d0f6bcf JCPV	126	# define CONFIG_SYS_I2C_SPEED 50000 /* 50 kHz is supposed to work */
6d0f6bcf JCPV	127	# define CONFIG_SYS_I2C_SLAVE 0xFE
e2211743 WD	128
	129	#ifdef CONFIG_SOFT_I2C
	130	/*
	131	* Software (bit-bang) I2C driver configuration
	132	*/
	133	#define PB_SCL 0x00000020 /* PB 26 */
	134	#define PB_SDA 0x00000010 /* PB 27 */
	135
	136	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	137	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	138	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	139	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	140	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	141	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	142	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	143	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	144	#define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
	145	#endif /* CONFIG_SOFT_I2C */
	146
	147
e9a0f8f1 JL	148	/*
	149	* Command line configuration.
	150	*/
	151	#include <config_cmd_default.h>
	152
	153	#define CONFIG_CMD_DHCP
	154	#define CONFIG_CMD_I2C
	155	#define CONFIG_CMD_IDE
	156	#define CONFIG_CMD_DATE
	157
	158	#undef CONFIG_CMD_PCMCIA
	159	#undef CONFIG_CMD_IDE
e2211743	160
e2211743 WD	161
	162	/*
	163	* Miscellaneous configurable options
	164	*/
6d0f6bcf JCPV	165	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	166	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
e9a0f8f1	167	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	168	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	169	#else
6d0f6bcf	170	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	171	#endif
6d0f6bcf JCPV	172	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	173	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	174	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	177	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
e2211743	178
6d0f6bcf	179	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
e2211743	180
6d0f6bcf	181	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743	182
6d0f6bcf	183	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
e2211743 WD	184
	185	/*
	186	* Low Level Configuration Settings
	187	* (address mappings, register initial values, etc.)
	188	* You should know what you are doing if you make changes here.
	189	*/
	190	/*-----------------------------------------------------------------------
	191	* Internal Memory Mapped Register
	192	*/
6d0f6bcf	193	#define CONFIG_SYS_IMMR 0xFFF00000
e2211743 WD	194
	195	/*-----------------------------------------------------------------------
	196	* Definitions for initial stack pointer and data area (in DPRAM)
	197	*/
6d0f6bcf	198	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	199	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
6d0f6bcf	200	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	201	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf	202	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	203
	204	/*-----------------------------------------------------------------------
	205	* Start addresses for the final memory configuration
	206	* (Set up by the startup code)
6d0f6bcf	207	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	210	#define CONFIG_SYS_FLASH_BASE 0x40000000
	211	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	212	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	213	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 WD	214
	215	/*
	216	* For booting Linux, the board info and command line data
	217	* have to be in the first 8 MB of memory, since this is
	218	* the maximum mapped by the Linux kernel during initialization.
	219	*/
6d0f6bcf	220	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	221
	222	/*-----------------------------------------------------------------------
	223	* FLASH organization
	224	*/
6d0f6bcf JCPV	225	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	226	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
e2211743 WD	227
e2211743 WD	228	/* timeout values are in ticks = ms */
6d0f6bcf JCPV	229	#define CONFIG_SYS_FLASH_ERASE_TOUT (120CONFIG_SYS_HZ) / Timeout for Flash Erase */
6d0f6bcf JCPV	230	#define CONFIG_SYS_FLASH_WRITE_TOUT (1 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
e2211743	231
5a1aceb0	232	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	233	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	234	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
e2211743 WD	235
e2211743 WD	236	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	237	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	238	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
e2211743	239
6d0f6bcf	240	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
67c31036	241
e2211743 WD	242	/*-----------------------------------------------------------------------
	243	* Cache Configuration
	244	*/
6d0f6bcf	245	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e9a0f8f1	246	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	247	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
e2211743 WD	248	#endif
	249
	250	/*-----------------------------------------------------------------------
	251	* SYPCR - System Protection Control 11-9
	252	* SYPCR can only be written once after reset!
	253	*-----------------------------------------------------------------------
	254	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	255	*/
	256	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	257	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
e2211743 WD	258	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
e2211743 WD	259	#else
6d0f6bcf	260	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
e2211743 WD	261	#endif
	262
	263	/*-----------------------------------------------------------------------
	264	* SIUMCR - SIU Module Configuration 11-6
	265	*-----------------------------------------------------------------------
	266	* PCMCIA config., multi-function pin tri-state
	267	*/
	268	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf	269	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
e2211743	270	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	271	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
e2211743 WD	272	#endif /* CONFIG_CAN_DRIVER */
	273
	274	/*-----------------------------------------------------------------------
	275	* TBSCR - Time Base Status and Control 11-26
	276	*-----------------------------------------------------------------------
	277	* Clear Reference Interrupt Status, Timebase freezing enabled
	278	*/
6d0f6bcf	279	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
e2211743 WD	280
	281	/*-----------------------------------------------------------------------
	282	* RTCSC - Real-Time Clock Status and Control Register 11-27
	283	*-----------------------------------------------------------------------
	284	*/
6d0f6bcf	285	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
e2211743 WD	286
	287	/*-----------------------------------------------------------------------
	288	* PISCR - Periodic Interrupt Status and Control 11-31
	289	*-----------------------------------------------------------------------
	290	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	291	*/
6d0f6bcf	292	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
e2211743 WD	293
	294	/*-----------------------------------------------------------------------
	295	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	296	*-----------------------------------------------------------------------
	297	* Reset PLL lock status sticky bit, timer expired status bit and timer
	298	* interrupt status bit
	299	*/
	300
	301	/* for 64 MHz, we use a 16 MHz clock * 4 */
6d0f6bcf	302	#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
e2211743 WD	303
	304	/*-----------------------------------------------------------------------
	305	* SCCR - System Clock and reset Control Register 15-27
	306	*-----------------------------------------------------------------------
	307	* Set clock output, timebase and RTC source and divider,
	308	* power management and some other internal clocks
	309	*/
	310	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	311	#define CONFIG_SYS_SCCR (/* SCCR_TBS \| */ SCCR_RTSEL \| SCCR_RTDIV \| \
e2211743 WD	312	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	313	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	314	SCCR_DFALCD00)
	315
	316	/*-----------------------------------------------------------------------
	317	* PCMCIA stuff
	318	*-----------------------------------------------------------------------
	319	*
	320	*/
6d0f6bcf JCPV	321	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	322	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	323	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	324	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	325	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	326	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	327	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	328	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
e2211743 WD	329
	330	/*-----------------------------------------------------------------------
	331	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	332	*-----------------------------------------------------------------------
	333	*/
	334
	335	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	336
	337	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	338	#undef CONFIG_IDE_LED /* LED for ide not supported */
	339	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	340
6d0f6bcf JCPV	341	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	342	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
e2211743	343
6d0f6bcf	344	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
e2211743	345
6d0f6bcf	346	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
e2211743 WD	347
e2211743 WD	348	/* Offset for data I/O */
6d0f6bcf	349	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
e2211743 WD	350
e2211743 WD	351	/* Offset for normal register accesses */
6d0f6bcf	352	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
e2211743 WD	353
e2211743 WD	354	/* Offset for alternate registers */
6d0f6bcf	355	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
e2211743 WD	356
	357	/*-----------------------------------------------------------------------
	358	*
	359	*-----------------------------------------------------------------------
	360	*
	361	*/
6d0f6bcf JCPV	362	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	363	#define CONFIG_SYS_DER 0
e2211743 WD	364
	365	/*
	366	* Init Memory Controller:
	367	*
	368	* BR0/1 (FLASH)
	369	*/
	370
	371	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	372
	373	/* used to re-map FLASH both when starting from SRAM or FLASH:
	374	* restrict access enough to keep SRAM working (if any)
	375	* but not too much to meddle with FLASH accesses
	376	*/
6d0f6bcf JCPV	377	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	378	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
e2211743 WD	379
	380	/*
	381	* FLASH timing:
	382	*/
	383	/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
6d0f6bcf	384	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
e2211743 WD	385	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
e2211743 WD	386
6d0f6bcf JCPV	387	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	388	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	389	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
e2211743 WD	390
	391	/*
	392	* BR2/3 and OR2/3 (SDRAM)
	393	*
	394	*/
	395	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	396	#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
	397	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	398
	399	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	400	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
e2211743	401
6d0f6bcf JCPV	402	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	403	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e2211743 WD	404
e2211743 WD	405	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	406	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	407	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e2211743	408	#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
6d0f6bcf JCPV	409	#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
	410	#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
	411	#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM \| OR_G5LA \| OR_BI)
	412	#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) \| \
e2211743 WD	413	BR_PS_8 \| BR_MS_UPMB \| BR_V )
	414	#endif /* CONFIG_CAN_DRIVER */
	415
	416	/*
	417	* Memory Periodic Timer Prescaler
	418	*
	419	* The Divider for PTA (refresh timer) configuration is based on an
	420	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	421	* the number of chip selects (NCS) and the actually needed refresh
	422	* rate is done by setting MPTPR.
	423	*
	424	* PTA is calculated from
	425	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	426	*
	427	* gclk CPU clock (not bus clock!)
	428	* Trefresh Refresh cycle * 4 (four word bursts used)
	429	*
	430	* 4096 Rows from SDRAM example configuration
	431	* 1000 factor s -> ms
	432	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	433	* 4 Number of refresh cycles per period
	434	* 64 Refresh cycle in ms per number of rows
	435	* --------------------------------------------
	436	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	437	*
	438	* 50 MHz => 50.000.000 / Divider = 98
	439	* 66 Mhz => 66.000.000 / Divider = 129
	440	* 80 Mhz => 80.000.000 / Divider = 156
	441	*/
6d0f6bcf	442	#define CONFIG_SYS_MAMR_PTA 129
e2211743 WD	443
	444	/*
	445	* For 16 MBit, refresh rates could be 31.3 us
	446	* (= 64 ms / 2K = 125 / quad bursts).
	447	* For a simpler initialization, 15.6 us is used instead.
	448	*
6d0f6bcf JCPV	449	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	450	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
e2211743	451	*/
6d0f6bcf JCPV	452	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	453	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
e2211743 WD	454
e2211743 WD	455	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	456	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	457	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
e2211743 WD	458
	459	/*
	460	* MAMR settings for SDRAM
	461	*/
	462
	463	/* 8 column SDRAM */
6d0f6bcf	464	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e2211743 WD	465	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	466	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	467	/* 9 column SDRAM */
6d0f6bcf	468	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
e2211743 WD	469	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	470	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	471
	472
e2211743	473	#endif /* __CONFIG_H */