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imx: reorganize IMX code as other SOCs
[J-u-boot.git] / board / phytec / pcm058 / pcm058.c
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876a25d2
SB		 1/*
2 * Copyright (C) 2016 Stefano Babic <[email protected]>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * Please note: there are two version of the board
9 * one with NAND and the other with eMMC.
10 * Both NAND and eMMC cannot be set because they share the
11 * same pins (SD4)
12 */
13#include <common.h>
14#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/crm_regs.h>
18#include <asm/arch/mx6-ddr.h>
19#include <asm/arch/iomux.h>
20#include <asm/arch/mx6-pins.h>
552a848e
SB		 21#include <asm/mach-imx/iomux-v3.h>
22#include <asm/mach-imx/boot_mode.h>
23#include <asm/mach-imx/mxc_i2c.h>
24#include <asm/mach-imx/spi.h>
1221ce45 25#include <linux/errno.h>
876a25d2
SB		 26#include <asm/gpio.h>
27#include <mmc.h>
28#include <i2c.h>
29#include <fsl_esdhc.h>
30#include <nand.h>
31#include <miiphy.h>
32#include <netdev.h>
33#include <asm/arch/sys_proto.h>
34#include <asm/sections.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
40 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
41
42#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
44 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
45
46#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
48
49#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
51
52#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
53 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
54 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
55
56#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
57
58#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
60
61#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
62 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63
64#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14)
65#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31)
66#define USER_LED IMX_GPIO_NR(1, 4)
67#define IMX6Q_DRIVE_STRENGTH 0x30
68
69int dram_init(void)
70{
71 gd->ram_size = imx_ddr_size();
72 return 0;
73}
74
75void board_turn_off_led(void)
76{
77 gpio_direction_output(USER_LED, 0);
78}
79
80static iomux_v3_cfg_t const uart1_pads[] = {
81 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
82 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
83};
84
85static iomux_v3_cfg_t const enet_pads[] = {
86 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
91 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
92 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
93 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
94 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
95 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
96 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
97 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
98 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
99 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
100 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
101 MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
102};
103
104static iomux_v3_cfg_t const ecspi1_pads[] = {
105 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
106 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
107 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
108 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
109};
110
b3cf4339 111#ifdef CONFIG_CMD_NAND
876a25d2
SB		 112/* NAND */
113static iomux_v3_cfg_t const nfc_pads[] = {
114 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
115 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
116 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
117 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
118 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
119 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
120 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
121 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
122 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
123 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
124 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
125 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
126 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
127 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
128 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
129 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
130 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
131 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
132 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
133};
b3cf4339 134#endif
876a25d2
SB		 135
136static struct i2c_pads_info i2c_pad_info2 = {
137 .scl = {
138 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
139 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
140 .gp = IMX_GPIO_NR(1, 5)
141 },
142 .sda = {
143 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
144 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
145 .gp = IMX_GPIO_NR(1, 6)
146 }
147};
148
149static struct fsl_esdhc_cfg usdhc_cfg[] = {
150 {.esdhc_base = USDHC1_BASE_ADDR,
151 .max_bus_width = 4},
152#ifndef CONFIG_CMD_NAND
153 {USDHC4_BASE_ADDR},
154#endif
155};
156
157static iomux_v3_cfg_t const usdhc1_pads[] = {
158 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
165};
166
b3cf4339 167#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD)
876a25d2
SB		 168static iomux_v3_cfg_t const usdhc4_pads[] = {
169 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
176 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
177 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
178 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
179};
180#endif
181
182int board_mmc_get_env_dev(int devno)
183{
184 return devno - 1;
185}
186
187int board_mmc_getcd(struct mmc *mmc)
188{
189 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
190 int ret = 0;
191
192 switch (cfg->esdhc_base) {
193 case USDHC1_BASE_ADDR:
194 ret = !gpio_get_value(USDHC1_CD_GPIO);
195 break;
196 case USDHC4_BASE_ADDR:
197 ret = 1; /* eMMC/uSDHC4 is always present */
198 break;
199 }
200
201 return ret;
202}
203
204int board_mmc_init(bd_t *bis)
205{
206#ifndef CONFIG_SPL_BUILD
207 int ret;
208 int i;
209
210 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
211 switch (i) {
212 case 0:
213 imx_iomux_v3_setup_multiple_pads(
214 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
215 gpio_direction_input(USDHC1_CD_GPIO);
216 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
217 break;
218#ifndef CONFIG_CMD_NAND
219 case 1:
220 imx_iomux_v3_setup_multiple_pads(
221 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
222 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
223 break;
224#endif
225 default:
226 printf("Warning: you configured more USDHC controllers"
227 "(%d) then supported by the board (%d)\n",
228 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
229 return -EINVAL;
230 }
231
232 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
233 if (ret)
234 return ret;
235 }
236
237 return 0;
238#else
239 struct src *psrc = (struct src *)SRC_BASE_ADDR;
240 unsigned reg = readl(&psrc->sbmr1) >> 11;
241 /*
242 * Upon reading BOOT_CFG register the following map is done:
243 * Bit 11 and 12 of BOOT_CFG register can determine the current
244 * mmc port
245 * 0x1 SD1
246 * 0x2 SD2
247 * 0x3 SD4
248 */
249
250 switch (reg & 0x3) {
251 case 0x0:
252 imx_iomux_v3_setup_multiple_pads(
253 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
254 gpio_direction_input(USDHC1_CD_GPIO);
255 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
256 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
257 usdhc_cfg[0].max_bus_width = 4;
258 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
259 break;
260 }
261 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
262#endif
263}
264
265static void setup_iomux_uart(void)
266{
267 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
268}
269
270static void setup_iomux_enet(void)
271{
272 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
273
274 gpio_direction_output(ENET_PHY_RESET_GPIO, 0);
275 mdelay(10);
276 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
277 mdelay(30);
278}
279
280static void setup_spi(void)
281{
282 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0");
283 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
284
285 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
286
287 enable_spi_clk(true, 0);
288}
289
290#ifdef CONFIG_CMD_NAND
291static void setup_gpmi_nand(void)
292{
293 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
294
295 /* config gpmi nand iomux */
296 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
297
298 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
299 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
300
301 /* config gpmi and bch clock to 100 MHz */
302 clrsetbits_le32(&mxc_ccm->cs2cdr,
303 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
304 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
305 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
306 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
307 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
308 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
309
310 /* enable ENFC_CLK_ROOT clock */
311 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
312
313 /* enable gpmi and bch clock gating */
314 setbits_le32(&mxc_ccm->CCGR4,
315 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
316 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
317 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
318 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
319 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
320
321 /* enable apbh clock gating */
322 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
323}
324#endif
325
326int board_spi_cs_gpio(unsigned bus, unsigned cs)
327{
328 if (bus != 0 || (cs != 0))
329 return -EINVAL;
330
331 return IMX_GPIO_NR(3, 19);
332}
333
334int board_eth_init(bd_t *bis)
335{
336 setup_iomux_enet();
337
338 return cpu_eth_init(bis);
339}
340
341int board_early_init_f(void)
342{
343 setup_iomux_uart();
344
345 return 0;
346}
347
348int board_init(void)
349{
350 /* address of boot parameters */
351 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
352
353#ifdef CONFIG_SYS_I2C_MXC
354 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
355#endif
356
357#ifdef CONFIG_MXC_SPI
358 setup_spi();
359#endif
360
361#ifdef CONFIG_CMD_NAND
362 setup_gpmi_nand();
363#endif
364 return 0;
365}
366
367
368#ifdef CONFIG_CMD_BMODE
369/*
370 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
371 * see Table 8-11 and Table 5-9
372 * BOOT_CFG1[7] = 1 (boot from NAND)
373 * BOOT_CFG1[5] = 0 - raw NAND
374 * BOOT_CFG1[4] = 0 - default pad settings
375 * BOOT_CFG1[3:2] = 00 - devices = 1
376 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
377 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
378 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
379 * BOOT_CFG2[0] = 0 - Reset time 12ms
380 */
381static const struct boot_mode board_boot_modes[] = {
382 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
383 {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
384 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
385 {NULL, 0},
386};
387#endif
388
389int board_late_init(void)
390{
391#ifdef CONFIG_CMD_BMODE
392 add_board_boot_modes(board_boot_modes);
393#endif
394
395 return 0;
396}
397
398#ifdef CONFIG_SPL_BUILD
399#include <spl.h>
400#include <libfdt.h>
401
402static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
403 .dram_sdclk_0 = 0x00000030,
404 .dram_sdclk_1 = 0x00000030,
405 .dram_cas = 0x00000030,
406 .dram_ras = 0x00000030,
407 .dram_reset = 0x00000030,
408 .dram_sdcke0 = 0x00000030,
409 .dram_sdcke1 = 0x00000030,
410 .dram_sdba2 = 0x00000000,
411 .dram_sdodt0 = 0x00000030,
412 .dram_sdodt1 = 0x00000030,
413 .dram_sdqs0 = 0x00000030,
414 .dram_sdqs1 = 0x00000030,
415 .dram_sdqs2 = 0x00000030,
416 .dram_sdqs3 = 0x00000030,
417 .dram_sdqs4 = 0x00000030,
418 .dram_sdqs5 = 0x00000030,
419 .dram_sdqs6 = 0x00000030,
420 .dram_sdqs7 = 0x00000030,
421 .dram_dqm0 = 0x00000030,
422 .dram_dqm1 = 0x00000030,
423 .dram_dqm2 = 0x00000030,
424 .dram_dqm3 = 0x00000030,
425 .dram_dqm4 = 0x00000030,
426 .dram_dqm5 = 0x00000030,
427 .dram_dqm6 = 0x00000030,
428 .dram_dqm7 = 0x00000030,
429};
430
431static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
432 .grp_ddr_type = 0x000C0000,
433 .grp_ddrmode_ctl = 0x00020000,
434 .grp_ddrpke = 0x00000000,
435 .grp_addds = IMX6Q_DRIVE_STRENGTH,
436 .grp_ctlds = IMX6Q_DRIVE_STRENGTH,
437 .grp_ddrmode = 0x00020000,
438 .grp_b0ds = IMX6Q_DRIVE_STRENGTH,
439 .grp_b1ds = IMX6Q_DRIVE_STRENGTH,
440 .grp_b2ds = IMX6Q_DRIVE_STRENGTH,
441 .grp_b3ds = IMX6Q_DRIVE_STRENGTH,
442 .grp_b4ds = IMX6Q_DRIVE_STRENGTH,
443 .grp_b5ds = IMX6Q_DRIVE_STRENGTH,
444 .grp_b6ds = IMX6Q_DRIVE_STRENGTH,
445 .grp_b7ds = IMX6Q_DRIVE_STRENGTH,
446};
447
448static const struct mx6_mmdc_calibration mx6_mmcd_calib = {
449 .p0_mpwldectrl0 = 0x00140014,
450 .p0_mpwldectrl1 = 0x000A0015,
451 .p1_mpwldectrl0 = 0x000A001E,
452 .p1_mpwldectrl1 = 0x000A0015,
453 .p0_mpdgctrl0 = 0x43080314,
454 .p0_mpdgctrl1 = 0x02680300,
455 .p1_mpdgctrl0 = 0x430C0318,
456 .p1_mpdgctrl1 = 0x03000254,
457 .p0_mprddlctl = 0x3A323234,
458 .p1_mprddlctl = 0x3E3C3242,
459 .p0_mpwrdlctl = 0x2A2E3632,
460 .p1_mpwrdlctl = 0x3C323E34,
461};
462
463static struct mx6_ddr3_cfg mem_ddr = {
464 .mem_speed = 1600,
465 .density = 2,
466 .width = 16,
467 .banks = 8,
468 .rowaddr = 14,
469 .coladdr = 10,
470 .pagesz = 2,
471 .trcd = 1375,
472 .trcmin = 4875,
473 .trasmin = 3500,
474 .SRT = 1,
475};
476
477static void ccgr_init(void)
478{
479 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
480
481 writel(0x00C03F3F, &ccm->CCGR0);
482 writel(0x0030FC03, &ccm->CCGR1);
483 writel(0x0FFFC000, &ccm->CCGR2);
484 writel(0x3FF00000, &ccm->CCGR3);
485 writel(0x00FFF300, &ccm->CCGR4);
486 writel(0x0F0000C3, &ccm->CCGR5);
487 writel(0x000003FF, &ccm->CCGR6);
488}
489
490static void gpr_init(void)
491{
492 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
493
494 /* enable AXI cache for VDOA/VPU/IPU */
495 writel(0xF00000CF, &iomux->gpr[4]);
496 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
497 writel(0x007F007F, &iomux->gpr[6]);
498 writel(0x007F007F, &iomux->gpr[7]);
499}
500
501
502static void spl_dram_init(void)
503{
504 struct mx6_ddr_sysinfo sysinfo = {
505 /* width of data bus:0=16,1=32,2=64 */
506 .dsize = 2,
507 /* config for full 4GB range so that get_mem_size() works */
508 .cs_density = 32, /* 32Gb per CS */
509 /* single chip select */
510 .ncs = 1,
511 .cs1_mirror = 0,
512 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
513 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
514 .walat = 1, /* Write additional latency */
515 .ralat = 5, /* Read additional latency */
516 .mif3_mode = 3, /* Command prediction working mode */
517 .bi_on = 1, /* Bank interleaving enabled */
518 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
519 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
520 .ddr_type = DDR_TYPE_DDR3,
edf00937
FE		 521 .refsel = 1, /* Refresh cycles at 32KHz */
522 .refr = 7, /* 8 refresh commands per refresh cycle */
876a25d2
SB		 523 };
524
525 mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
526 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
527}
528
529void board_boot_order(u32 *spl_boot_list)
530{
531 spl_boot_list[0] = spl_boot_device();
532 printf("Boot device %x\n", spl_boot_list[0]);
533 switch (spl_boot_list[0]) {
534 case BOOT_DEVICE_SPI:
535 spl_boot_list[1] = BOOT_DEVICE_UART;
536 break;
537 case BOOT_DEVICE_MMC1:
538 spl_boot_list[1] = BOOT_DEVICE_SPI;
539 spl_boot_list[2] = BOOT_DEVICE_UART;
540 break;
541 default:
542 printf("Boot device %x\n", spl_boot_list[0]);
543 }
544}
545
546void board_init_f(ulong dummy)
547{
548#ifdef CONFIG_CMD_NAND
549 /* Enable NAND */
550 setup_gpmi_nand();
551#endif
552
553 /* setup clock gating */
554 ccgr_init();
555
556 /* setup AIPS and disable watchdog */
557 arch_cpu_init();
558
559 /* setup AXI */
560 gpr_init();
561
562 board_early_init_f();
563
564 /* setup GP timer */
565 timer_init();
566
567 setup_spi();
568
569 /* UART clocks enabled and gd valid - init serial console */
570 preloader_console_init();
571
572 /* DDR initialization */
573 spl_dram_init();
574
575 /* Clear the BSS. */
576 memset(__bss_start, 0, __bss_end - __bss_start);
577
578 /* load/boot image from boot device */
579 board_init_r(NULL, 0);
580}
581#endif
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