[J-u-boot.git] / board / ti / ks2_evm / ddr3_k2l.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Keystone2: DDR3 initialization
 *
 * (C) Copyright 2014
 *     Texas Instruments Incorporated, <www.ti.com>
 */

#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>

static struct pll_init_data ddr3_400 = DDR3_PLL_400;

u32 ddr3_init(void)
{
	init_pll(&ddr3_400);

	/* No SO-DIMM, 2GB discreet DDR */
	printf("DRAM: 2 GiB\n");

	/* Reset DDR3 PHY after PLL enabled */
	ddr3_reset_ddrphy();

	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);

	return 2;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
345af534 HZ	2	/*
	3	* Keystone2: DDR3 initialization
	4	*
	5	* (C) Copyright 2014
	6	* Texas Instruments Incorporated, <www.ti.com>
345af534 HZ	7	*/
345af534 HZ	8
345af534 HZ	9	#include "ddr3_cfg.h"
	10	#include <asm/arch/ddr3.h>
	11
345af534 HZ	12	static struct pll_init_data ddr3_400 = DDR3_PLL_400;
345af534 HZ	13
66c98a0c	14	u32 ddr3_init(void)
345af534 HZ	15	{
	16	init_pll(&ddr3_400);
	17
	18	/* No SO-DIMM, 2GB discreet DDR */
	19	printf("DRAM: 2 GiB\n");
345af534 HZ	20
	21	/* Reset DDR3 PHY after PLL enabled */
	22	ddr3_reset_ddrphy();
	23
	24	ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
	25	ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
345af534	26
66c98a0c	27	return 2;
345af534	28	}