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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
536e7dac TL |
2 | /* |
3 | * Configuation settings for the Freescale MCF53017EVB. | |
4 | * | |
5 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
6 | * TsiChung Liew ([email protected]) | |
536e7dac TL |
7 | */ |
8 | ||
9 | /* | |
10 | * board/config.h - configuration options, board specific | |
11 | */ | |
12 | ||
13 | #ifndef _M53017EVB_H | |
14 | #define _M53017EVB_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
536e7dac | 20 | |
65cc0e2a | 21 | #define CFG_SYS_UART_PORT (0) |
536e7dac | 22 | |
536e7dac | 23 | #ifdef CONFIG_MCFFEC |
65cc0e2a TR |
24 | # define CFG_SYS_TX_ETH_BUFFER 8 |
25 | # define CFG_SYS_FEC_BUF_USE_SRAM | |
536e7dac TL |
26 | #endif |
27 | ||
65cc0e2a TR |
28 | #define CFG_SYS_RTC_CNT (0x8000) |
29 | #define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) | |
536e7dac | 30 | |
536e7dac | 31 | /* I2C */ |
536e7dac | 32 | |
536e7dac TL |
33 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
34 | "netdev=eth0\0" \ | |
35 | "loadaddr=40010000\0" \ | |
36 | "u-boot=u-boot.bin\0" \ | |
37 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
38 | "upd=run load; run prog\0" \ | |
39 | "prog=prot off 0 3ffff;" \ | |
40 | "era 0 3ffff;" \ | |
41 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
42 | "save\0" \ | |
43 | "" | |
44 | ||
45 | #define CONFIG_PRAM 512 /* 512 KB */ | |
536e7dac | 46 | |
65cc0e2a TR |
47 | #define CFG_SYS_CLK 80000000 |
48 | #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 | |
536e7dac | 49 | |
65cc0e2a | 50 | #define CFG_SYS_MBAR 0xFC000000 |
536e7dac TL |
51 | |
52 | /* | |
53 | * Low Level Configuration Settings | |
54 | * (address mappings, register initial values, etc.) | |
55 | * You should know what you are doing if you make changes here. | |
56 | */ | |
57 | /* | |
58 | * Definitions for initial stack pointer and data area (in DPRAM) | |
59 | */ | |
65cc0e2a TR |
60 | #define CFG_SYS_INIT_RAM_ADDR 0x80000000 |
61 | #define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ | |
62 | #define CFG_SYS_INIT_RAM_CTRL 0x221 | |
536e7dac TL |
63 | |
64 | /* | |
65 | * Start addresses for the final memory configuration | |
66 | * (Set up by the startup code) | |
aa6e94de | 67 | * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 |
536e7dac | 68 | */ |
aa6e94de TR |
69 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
70 | #define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ | |
71 | #define CFG_SYS_SDRAM_CFG1 0x43711630 | |
72 | #define CFG_SYS_SDRAM_CFG2 0x56670000 | |
73 | #define CFG_SYS_SDRAM_CTRL 0xE1092000 | |
74 | #define CFG_SYS_SDRAM_EMOD 0x80010000 | |
75 | #define CFG_SYS_SDRAM_MODE 0x00CD0000 | |
536e7dac | 76 | |
536e7dac TL |
77 | /* |
78 | * For booting Linux, the board info and command line data | |
79 | * have to be in the first 8 MB of memory, since this is | |
80 | * the maximum mapped by the Linux kernel during initialization ?? | |
81 | */ | |
65cc0e2a | 82 | #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) |
536e7dac TL |
83 | |
84 | /*----------------------------------------------------------------------- | |
85 | * FLASH organization | |
86 | */ | |
536e7dac | 87 | #ifdef CONFIG_SYS_FLASH_CFI |
65cc0e2a | 88 | # define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
536e7dac TL |
89 | #endif |
90 | ||
65cc0e2a | 91 | #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE |
536e7dac TL |
92 | |
93 | /* Configuration for environment | |
94 | * Environment is embedded in u-boot in the second sector of the flash | |
95 | */ | |
536e7dac | 96 | |
5296cb1d | 97 | #define LDS_BOARD_TEXT \ |
98 | . = DEFINED(env_offset) ? env_offset : .; \ | |
0649cd0d | 99 | env/embedded.o(.text*) |
5296cb1d | 100 | |
536e7dac TL |
101 | /*----------------------------------------------------------------------- |
102 | * Cache Configuration | |
103 | */ | |
536e7dac | 104 | |
65cc0e2a TR |
105 | #define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ |
106 | CFG_SYS_INIT_RAM_SIZE - 8) | |
107 | #define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ | |
108 | CFG_SYS_INIT_RAM_SIZE - 4) | |
109 | #define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) | |
110 | #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ | |
aa6e94de | 111 | CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ |
dd9f054e | 112 | CF_ACR_EN | CF_ACR_SM_ALL) |
65cc0e2a | 113 | #define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ |
dd9f054e TL |
114 | CF_CACR_DCM_P) |
115 | ||
536e7dac TL |
116 | /*----------------------------------------------------------------------- |
117 | * Chipselect bank definitions | |
118 | */ | |
119 | /* | |
120 | * CS0 - NOR Flash | |
121 | * CS1 - Ext SRAM | |
122 | * CS2 - Available | |
123 | * CS3 - Available | |
124 | * CS4 - Available | |
125 | * CS5 - Available | |
126 | */ | |
65cc0e2a TR |
127 | #define CFG_SYS_CS0_BASE 0 |
128 | #define CFG_SYS_CS0_MASK 0x00FF0001 | |
129 | #define CFG_SYS_CS0_CTRL 0x00001FA0 | |
536e7dac | 130 | |
65cc0e2a TR |
131 | #define CFG_SYS_CS1_BASE 0xC0000000 |
132 | #define CFG_SYS_CS1_MASK 0x00070001 | |
133 | #define CFG_SYS_CS1_CTRL 0x00001FA0 | |
536e7dac TL |
134 | |
135 | #endif /* _M53017EVB_H */ |