[J-u-boot.git] / board / freescale / t4qds / ddr.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"

DECLARE_GLOBAL_DATA_PTR;

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	ulong ddr_freq;

	if (ctrl_num > 2) {
		printf("Not supported controller number %d\n", ctrl_num);
		return;
	}
	if (!pdimm->n_ranks)
		return;

	/*
	 * we use identical timing for all slots. If needed, change the code
	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
	 */
	if (popts->registered_dimm_en)
		pbsp = rdimms[0];
	else
		pbsp = udimms[0];


	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(0) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm->n_ranks &&
		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->cpo_override = pbsp->cpo;
				popts->write_data_delay =
					pbsp->write_data_delay;
				popts->clk_adjust = pbsp->clk_adjust;
				popts->wrlvl_start = pbsp->wrlvl_start;
				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
				popts->twot_en = pbsp->force_2t;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found "
			"for data rate %lu MT/s\n"
			"Trying to use the highest speed (%u) parameters\n",
			ddr_freq, pbsp_highest->datarate_mhz_high);
		popts->cpo_override = pbsp_highest->cpo;
		popts->write_data_delay = pbsp_highest->write_data_delay;
		popts->clk_adjust = pbsp_highest->clk_adjust;
		popts->wrlvl_start = pbsp_highest->wrlvl_start;
		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
		popts->twot_en = pbsp_highest->force_2t;
	} else {
		panic("DIMM is not supported by this board");
	}
found:
	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
		"wrlvl_ctrl_3 0x%x\n",
		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
		pbsp->wrlvl_ctl_3);

	/*
	 * Factors to consider for half-strength driver enable:
	 *	- number of DIMMs installed
	 */
	popts->half_strength_driver_enable = 0;
	/*
	 * Write leveling override
	 */
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;

	/*
	 * Rtt and Rtt_WR override
	 */
	popts->rtt_override = 0;

	/* Enable ZQ calibration */
	popts->zq_en = 1;

	/* DHC_EN =1, ODT = 75 Ohm */
	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
}

phys_size_t initdram(int board_type)
{
	phys_size_t dram_size;

	puts("Initializing....using SPD\n");

#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
	dram_size = fsl_ddr_sdram();
#else
	/* DDR has been initialised by first stage boot loader */
	dram_size = fsl_ddr_sdram_size();
#endif
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	return dram_size;
}
Commit	Line	Data
ee52b188 YS	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
ee52b188 YS	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <hwconfig.h>
	10	#include <asm/mmu.h>
5614e71b YS	11	#include <fsl_ddr_sdram.h>
5614e71b YS	12	#include <fsl_ddr_dimm_params.h>
ee52b188	13	#include <asm/fsl_law.h>
1cb19fbb	14	#include "ddr.h"
ee52b188 YS	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
ee52b188 YS	18	void fsl_ddr_board_options(memctl_options_t *popts,
	19	dimm_params_t *pdimm,
	20	unsigned int ctrl_num)
	21	{
	22	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
	23	ulong ddr_freq;
	24
	25	if (ctrl_num > 2) {
	26	printf("Not supported controller number %d\n", ctrl_num);
	27	return;
	28	}
	29	if (!pdimm->n_ranks)
	30	return;
	31
	32	/*
	33	* we use identical timing for all slots. If needed, change the code
	34	* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
	35	*/
	36	if (popts->registered_dimm_en)
	37	pbsp = rdimms[0];
	38	else
	39	pbsp = udimms[0];
	40
	41
	42	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
	43	* freqency and n_banks specified in board_specific_parameters table.
	44	*/
	45	ddr_freq = get_ddr_freq(0) / 1000000;
	46	while (pbsp->datarate_mhz_high) {
054dfd9b YS	47	if (pbsp->n_ranks == pdimm->n_ranks &&
054dfd9b YS	48	(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
ee52b188 YS	49	if (ddr_freq <= pbsp->datarate_mhz_high) {
	50	popts->cpo_override = pbsp->cpo;
	51	popts->write_data_delay =
	52	pbsp->write_data_delay;
	53	popts->clk_adjust = pbsp->clk_adjust;
	54	popts->wrlvl_start = pbsp->wrlvl_start;
	55	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	56	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
0dd38a35	57	popts->twot_en = pbsp->force_2t;
ee52b188 YS	58	goto found;
	59	}
	60	pbsp_highest = pbsp;
	61	}
	62	pbsp++;
	63	}
	64
	65	if (pbsp_highest) {
	66	printf("Error: board specific timing not found "
	67	"for data rate %lu MT/s\n"
	68	"Trying to use the highest speed (%u) parameters\n",
	69	ddr_freq, pbsp_highest->datarate_mhz_high);
	70	popts->cpo_override = pbsp_highest->cpo;
	71	popts->write_data_delay = pbsp_highest->write_data_delay;
	72	popts->clk_adjust = pbsp_highest->clk_adjust;
	73	popts->wrlvl_start = pbsp_highest->wrlvl_start;
	74	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	75	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
0dd38a35	76	popts->twot_en = pbsp_highest->force_2t;
ee52b188 YS	77	} else {
	78	panic("DIMM is not supported by this board");
	79	}
	80	found:
054dfd9b YS	81	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
	82	"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
	83	"wrlvl_ctrl_3 0x%x\n",
	84	pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
	85	pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
	86	pbsp->wrlvl_ctl_3);
	87
ee52b188 YS	88	/*
	89	* Factors to consider for half-strength driver enable:
	90	* - number of DIMMs installed
	91	*/
	92	popts->half_strength_driver_enable = 0;
	93	/*
	94	* Write leveling override
	95	*/
	96	popts->wrlvl_override = 1;
	97	popts->wrlvl_sample = 0xf;
	98
	99	/*
	100	* Rtt and Rtt_WR override
	101	*/
	102	popts->rtt_override = 0;
	103
	104	/* Enable ZQ calibration */
	105	popts->zq_en = 1;
	106
	107	/* DHC_EN =1, ODT = 75 Ohm */
	108	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	109	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
	110	}
	111
	112	phys_size_t initdram(int board_type)
	113	{
	114	phys_size_t dram_size;
	115
	116	puts("Initializing....using SPD\n");
	117
b6036993	118	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
ee52b188	119	dram_size = fsl_ddr_sdram();
b6036993 SX	120	#else
	121	/* DDR has been initialised by first stage boot loader */
	122	dram_size = fsl_ddr_sdram_size();
	123	#endif
53499282 SL	124	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	125	dram_size *= 0x100000;
	126
ee52b188 YS	127	return dram_size;
ee52b188 YS	128	}