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mmc: initialize an err variable
[J-u-boot.git] / drivers / fpga / socfpga_arria10.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
2baa9972 2/*
0a42a132 3 * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
2baa9972 4 */
4d72caa5 5#include <image.h>
f7ae49fc 6#include <log.h>
401d1c4f 7#include <asm/global_data.h>
2baa9972
TFC		 8#include <asm/io.h>
9#include <asm/arch/fpga_manager.h>
10#include <asm/arch/reset_manager.h>
11#include <asm/arch/system_manager.h>
12#include <asm/arch/sdram.h>
13#include <asm/arch/misc.h>
14#include <altera.h>
0a42a132 15#include <asm/arch/pinmux.h>
2baa9972 16#include <common.h>
c2848cc2 17#include <dm.h>
0a42a132 18#include <dm/ofnode.h>
2baa9972 19#include <errno.h>
0a42a132 20#include <fs_loader.h>
2baa9972
TFC		 21#include <wait_bit.h>
22#include <watchdog.h>
cd93d625 23#include <linux/bitops.h>
c05ed00a 24#include <linux/delay.h>
2baa9972
TFC		 25
26#define CFGWDTH_32 1
27#define MIN_BITSTREAM_SIZECHECK 230
28#define ENCRYPTION_OFFSET 69
29#define COMPRESSION_OFFSET 229
30#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
31#define FPGA_TIMEOUT_CNT 0x1000000
0a42a132
TFC		 32#define DEFAULT_DDR_LOAD_ADDRESS 0x400
33
34DECLARE_GLOBAL_DATA_PTR;
2baa9972 35
2baa9972
TFC		 36static const struct socfpga_fpga_manager *fpga_manager_base =
37 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
38
2baa9972
TFC		 39static void fpgamgr_set_cd_ratio(unsigned long ratio);
40
41static uint32_t fpgamgr_get_msel(void)
42{
43 u32 reg;
44
45 reg = readl(&fpga_manager_base->imgcfg_stat);
46 reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
47 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
48
49 return reg;
50}
51
52static void fpgamgr_set_cfgwdth(int width)
53{
54 if (width)
55 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
56 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
57 else
58 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
59 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
60}
61
62int is_fpgamgr_user_mode(void)
63{
64 return (readl(&fpga_manager_base->imgcfg_stat) &
65 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
66}
67
68static int wait_for_user_mode(void)
69{
48263504 70 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
2baa9972
TFC		 71 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
72 1, FPGA_TIMEOUT_MSEC, false);
73}
74
1085bb3c 75int is_fpgamgr_early_user_mode(void)
2baa9972
TFC		 76{
77 return (readl(&fpga_manager_base->imgcfg_stat) &
78 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
79}
80
81int fpgamgr_wait_early_user_mode(void)
82{
83 u32 sync_data = 0xffffffff;
84 u32 i = 0;
85 unsigned start = get_timer(0);
86 unsigned long cd_ratio;
87
88 /* Getting existing CDRATIO */
89 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
90 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
91 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
92
93 /* Using CDRATIO_X1 for better compatibility */
94 fpgamgr_set_cd_ratio(CDRATIO_x1);
95
96 while (!is_fpgamgr_early_user_mode()) {
97 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
98 return -ETIMEDOUT;
99 fpgamgr_program_write((const long unsigned int *)&sync_data,
100 sizeof(sync_data));
101 udelay(FPGA_TIMEOUT_MSEC);
102 i++;
103 }
104
f4b53b24 105 debug("FPGA: Additional %i sync word needed\n", i);
2baa9972
TFC		 106
107 /* restoring original CDRATIO */
108 fpgamgr_set_cd_ratio(cd_ratio);
109
110 return 0;
111}
112
113/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
114static int wait_for_nconfig_pin_and_nstatus_pin(void)
115{
116 unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
117 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
118
4ae87a83
TFC		 119 /*
120 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
121 * de-asserted, timeout at 1000ms
2baa9972 122 */
4ae87a83
TFC		 123 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
124 true, FPGA_TIMEOUT_MSEC, false);
2baa9972
TFC		 125}
126
127static int wait_for_f2s_nstatus_pin(unsigned long value)
128{
129 /* Poll until f2s to specific value, timeout at 1000ms */
48263504
ÁFR		 130 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
131 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
132 value, FPGA_TIMEOUT_MSEC, false);
2baa9972
TFC		 133}
134
135/* set CD ratio */
136static void fpgamgr_set_cd_ratio(unsigned long ratio)
137{
138 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
139 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
140
141 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
142 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
143 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
144}
145
146/* get the MSEL value, verify we are set for FPP configuration mode */
147static int fpgamgr_verify_msel(void)
148{
149 u32 msel = fpgamgr_get_msel();
150
151 if (msel & ~BIT(0)) {
152 printf("Fail: read msel=%d\n", msel);
153 return -EPERM;
154 }
155
156 return 0;
157}
158
159/*
160 * Write cdratio and cdwidth based on whether the bitstream is compressed
161 * and/or encoded
162 */
163static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
164 size_t rbf_size)
165{
166 unsigned int cd_ratio;
167 bool encrypt, compress;
168
169 /*
170 * According to the bitstream specification,
171 * both encryption and compression status are
172 * in location before offset 230 of the buffer.
173 */
174 if (rbf_size < MIN_BITSTREAM_SIZECHECK)
175 return -EINVAL;
176
177 encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
178 encrypt = encrypt != 0;
179
180 compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
181 compress = !compress;
182
f4b53b24
TFC		 183 debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]);
184 debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]);
185 debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt,
186 compress);
2baa9972
TFC		 187
188 /*
189 * from the register map description of cdratio in imgcfg_ctrl_02:
190 * Normal Configuration : 32bit Passive Parallel
191 * Partial Reconfiguration : 16bit Passive Parallel
192 */
193
194 /*
195 * cd ratio is dependent on cfg width and whether the bitstream
196 * is encrypted and/or compressed.
197 *
198 * | width | encr. | compr. | cd ratio |
199 * | 16 | 0 | 0 | 1 |
200 * | 16 | 0 | 1 | 4 |
201 * | 16 | 1 | 0 | 2 |
202 * | 16 | 1 | 1 | 4 |
203 * | 32 | 0 | 0 | 1 |
204 * | 32 | 0 | 1 | 8 |
205 * | 32 | 1 | 0 | 4 |
206 * | 32 | 1 | 1 | 8 |
207 */
208 if (!compress && !encrypt) {
209 cd_ratio = CDRATIO_x1;
210 } else {
211 if (compress)
212 cd_ratio = CDRATIO_x4;
213 else
214 cd_ratio = CDRATIO_x2;
215
216 /* if 32 bit, double the cd ratio (so register
217 field setting is incremented) */
218 if (cfg_width == CFGWDTH_32)
219 cd_ratio += 1;
220 }
221
222 fpgamgr_set_cfgwdth(cfg_width);
223 fpgamgr_set_cd_ratio(cd_ratio);
224
225 return 0;
226}
227
228static int fpgamgr_reset(void)
229{
230 unsigned long reg;
231
232 /* S2F_NCONFIG = 0 */
233 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
234 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
235
236 /* Wait for f2s_nstatus == 0 */
237 if (wait_for_f2s_nstatus_pin(0))
238 return -ETIME;
239
240 /* S2F_NCONFIG = 1 */
241 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
242 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
243
244 /* Wait for f2s_nstatus == 1 */
245 if (wait_for_f2s_nstatus_pin(1))
246 return -ETIME;
247
248 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
249 reg = readl(&fpga_manager_base->imgcfg_stat);
250 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
251 return -EPERM;
252
253 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
254 return -EPERM;
255
256 return 0;
257}
258
259/* Start the FPGA programming by initialize the FPGA Manager */
260int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
261{
262 int ret;
263
264 /* Step 1 */
265 if (fpgamgr_verify_msel())
266 return -EPERM;
267
268 /* Step 2 */
269 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
270 return -EPERM;
271
272 /*
273 * Step 3:
274 * Make sure no other external devices are trying to interfere with
275 * programming:
276 */
277 if (wait_for_nconfig_pin_and_nstatus_pin())
278 return -ETIME;
279
280 /*
281 * Step 4:
282 * Deassert the signal drives from HPS
283 *
284 * S2F_NCE = 1
285 * S2F_PR_REQUEST = 0
286 * EN_CFG_CTRL = 0
287 * EN_CFG_DATA = 0
288 * S2F_NCONFIG = 1
289 * S2F_NSTATUS_OE = 0
290 * S2F_CONDONE_OE = 0
291 */
292 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
293 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
294
295 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
296 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
297
298 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
299 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
300 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
301
302 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
303 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
304
305 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
306 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
307 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
308
309 /*
310 * Step 5:
311 * Enable overrides
312 * S2F_NENABLE_CONFIG = 0
313 * S2F_NENABLE_NCONFIG = 0
314 */
315 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
316 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
317 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
318 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
319
320 /*
321 * Disable driving signals that HPS doesn't need to drive.
322 * S2F_NENABLE_NSTATUS = 1
323 * S2F_NENABLE_CONDONE = 1
324 */
325 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
326 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
327 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
328
329 /*
330 * Step 6:
331 * Drive chip select S2F_NCE = 0
332 */
333 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
334 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
335
336 /* Step 7 */
337 if (wait_for_nconfig_pin_and_nstatus_pin())
338 return -ETIME;
339
340 /* Step 8 */
341 ret = fpgamgr_reset();
342
343 if (ret)
344 return ret;
345
346 /*
347 * Step 9:
348 * EN_CFG_CTRL and EN_CFG_DATA = 1
349 */
350 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
351 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
352 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
353
354 return 0;
355}
356
357/* Ensure the FPGA entering config done */
358static int fpgamgr_program_poll_cd(void)
359{
360 unsigned long reg, i;
361
362 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
363 reg = readl(&fpga_manager_base->imgcfg_stat);
364 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
365 return 0;
366
367 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
368 printf("nstatus == 0 while waiting for condone\n");
369 return -EPERM;
370 }
c1cf5391 371 WATCHDOG_RESET();
2baa9972
TFC		 372 }
373
374 if (i == FPGA_TIMEOUT_CNT)
375 return -ETIME;
376
377 return 0;
378}
379
380/* Ensure the FPGA entering user mode */
381static int fpgamgr_program_poll_usermode(void)
382{
383 unsigned long reg;
384 int ret = 0;
385
386 if (fpgamgr_dclkcnt_set(0xf))
387 return -ETIME;
388
389 ret = wait_for_user_mode();
390 if (ret < 0) {
391 printf("%s: Failed to enter user mode with ", __func__);
392 printf("error code %d\n", ret);
393 return ret;
394 }
395
396 /*
397 * Step 14:
398 * Stop DATA path and Dclk
399 * EN_CFG_CTRL and EN_CFG_DATA = 0
400 */
401 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
402 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
403 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
404
405 /*
406 * Step 15:
407 * Disable overrides
408 * S2F_NENABLE_CONFIG = 1
409 * S2F_NENABLE_NCONFIG = 1
410 */
411 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
412 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
413 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
414 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
415
416 /* Disable chip select S2F_NCE = 1 */
417 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
418 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
419
420 /*
421 * Step 16:
422 * Final check
423 */
424 reg = readl(&fpga_manager_base->imgcfg_stat);
425 if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
426 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
427 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
428 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
429 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
430 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
431 return -EPERM;
432
433 return 0;
434}
435
436int fpgamgr_program_finish(void)
437{
438 /* Ensure the FPGA entering config done */
439 int status = fpgamgr_program_poll_cd();
440
441 if (status) {
442 printf("FPGA: Poll CD failed with error code %d\n", status);
443 return -EPERM;
444 }
2baa9972
TFC		 445
446 /* Ensure the FPGA entering user mode */
447 status = fpgamgr_program_poll_usermode();
448 if (status) {
449 printf("FPGA: Poll usermode failed with error code %d\n",
450 status);
451 return -EPERM;
452 }
453
454 printf("Full Configuration Succeeded.\n");
455
456 return 0;
457}
458
0a42a132
TFC		 459ofnode get_fpga_mgr_ofnode(ofnode from)
460{
461 return ofnode_by_compatible(from, "altr,socfpga-a10-fpga-mgr");
462}
463
464const char *get_fpga_filename(void)
465{
466 const char *fpga_filename = NULL;
467
468 ofnode fpgamgr_node = get_fpga_mgr_ofnode(ofnode_null());
469
470 if (ofnode_valid(fpgamgr_node))
471 fpga_filename = ofnode_read_string(fpgamgr_node,
472 "altr,bitstream");
473
474 return fpga_filename;
475}
476
477static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
478{
479 /*
480 * Magic ID starting at:
481 * -> 1st dword[15:0] in periph.rbf
482 * -> 2nd dword[15:0] in core.rbf
483 * Note: dword == 32 bits
484 */
485 u32 word_reading_max = 2;
486 u32 i;
487
488 for (i = 0; i < word_reading_max; i++) {
489 if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
490 rbf->security = unencrypted;
491 } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
492 rbf->security = encrypted;
493 } else if (*(buffer + i + 1) ==
494 FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) {
495 rbf->security = unencrypted;
496 } else if (*(buffer + i + 1) ==
497 FPGA_SOCFPGA_A10_RBF_ENCRYPTED) {
498 rbf->security = encrypted;
499 } else {
500 rbf->security = invalid;
501 continue;
502 }
503
504 /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */
505 if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
506 rbf->section = periph_section;
507 break;
508 } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) {
509 rbf->section = core_section;
510 break;
511 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) {
512 rbf->section = periph_section;
513 break;
514 } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) {
515 rbf->section = core_section;
516 break;
517 }
518
519 rbf->section = unknown;
520 break;
521
522 WATCHDOG_RESET();
523 }
524}
525
526#ifdef CONFIG_FS_LOADER
527static int first_loading_rbf_to_buffer(struct udevice *dev,
528 struct fpga_loadfs_info *fpga_loadfs,
529 u32 *buffer, size_t *buffer_bsize)
530{
531 u32 *buffer_p = (u32 *)*buffer;
532 u32 *loadable = buffer_p;
533 size_t buffer_size = *buffer_bsize;
534 size_t fit_size;
535 int ret, i, count, confs_noffset, images_noffset, rbf_offset, rbf_size;
536 const char *fpga_node_name = NULL;
537 const char *uname = NULL;
538
539 /* Load image header into buffer */
540 ret = request_firmware_into_buf(dev,
541 fpga_loadfs->fpga_fsinfo->filename,
542 buffer_p, sizeof(struct image_header),
543 0);
544 if (ret < 0) {
545 debug("FPGA: Failed to read image header from flash.\n");
546 return -ENOENT;
547 }
548
549 if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) {
550 debug("FPGA: No FDT magic was found.\n");
551 return -EBADF;
552 }
553
554 fit_size = fdt_totalsize(buffer_p);
555
556 if (fit_size > buffer_size) {
557 debug("FPGA: FIT image is larger than available buffer.\n");
558 debug("Please use FIT external data or increasing buffer.\n");
559 return -ENOMEM;
560 }
561
562 /* Load entire FIT into buffer */
563 ret = request_firmware_into_buf(dev,
564 fpga_loadfs->fpga_fsinfo->filename,
565 buffer_p, fit_size, 0);
566 if (ret < 0)
567 return ret;
568
c5819701
SG		 569 ret = fit_check_format(buffer_p, IMAGE_SIZE_INVAL);
570 if (ret) {
0a42a132 571 debug("FPGA: No valid FIT image was found.\n");
c5819701 572 return ret;
0a42a132
TFC		 573 }
574
575 confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH);
576 images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH);
577 if (confs_noffset < 0 || images_noffset < 0) {
578 debug("FPGA: No Configurations or images nodes were found.\n");
579 return -ENOENT;
580 }
581
582 /* Get default configuration unit name from default property */
583 confs_noffset = fit_conf_get_node(buffer_p, NULL);
584 if (confs_noffset < 0) {
585 debug("FPGA: No default configuration was found in config.\n");
586 return -ENOENT;
587 }
588
589 count = fit_conf_get_prop_node_count(buffer_p, confs_noffset,
590 FIT_FPGA_PROP);
591 if (count < 0) {
592 debug("FPGA: Invalid configuration format for FPGA node.\n");
593 return count;
594 }
595 debug("FPGA: FPGA node count: %d\n", count);
596
597 for (i = 0; i < count; i++) {
598 images_noffset = fit_conf_get_prop_node_index(buffer_p,
599 confs_noffset,
600 FIT_FPGA_PROP, i);
601 uname = fit_get_name(buffer_p, images_noffset, NULL);
602 if (uname) {
603 debug("FPGA: %s\n", uname);
604
605 if (strstr(uname, "fpga-periph") &&
606 (!is_fpgamgr_early_user_mode() ||
607 is_fpgamgr_user_mode())) {
608 fpga_node_name = uname;
609 printf("FPGA: Start to program ");
610 printf("peripheral/full bitstream ...\n");
611 break;
612 } else if (strstr(uname, "fpga-core") &&
613 (is_fpgamgr_early_user_mode() &&
614 !is_fpgamgr_user_mode())) {
615 fpga_node_name = uname;
616 printf("FPGA: Start to program core ");
617 printf("bitstream ...\n");
618 break;
619 }
620 }
621 WATCHDOG_RESET();
622 }
623
624 if (!fpga_node_name) {
625 debug("FPGA: No suitable bitstream was found, count: %d.\n", i);
626 return 1;
627 }
628
629 images_noffset = fit_image_get_node(buffer_p, fpga_node_name);
630 if (images_noffset < 0) {
631 debug("FPGA: No node '%s' was found in FIT.\n",
632 fpga_node_name);
633 return -ENOENT;
634 }
635
636 if (!fit_image_get_data_position(buffer_p, images_noffset,
637 &rbf_offset)) {
638 debug("FPGA: Data position was found.\n");
639 } else if (!fit_image_get_data_offset(buffer_p, images_noffset,
640 &rbf_offset)) {
641 /*
642 * For FIT with external data, figure out where
643 * the external images start. This is the base
644 * for the data-offset properties in each image.
645 */
646 rbf_offset += ((fdt_totalsize(buffer_p) + 3) & ~3);
647 debug("FPGA: Data offset was found.\n");
648 } else {
649 debug("FPGA: No data position/offset was found.\n");
650 return -ENOENT;
651 }
652
653 ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size);
654 if (ret < 0) {
655 debug("FPGA: No data size was found (err=%d).\n", ret);
656 return -ENOENT;
657 }
658
659 if (gd->ram_size < rbf_size) {
660 debug("FPGA: Using default OCRAM buffer and size.\n");
661 } else {
662 ret = fit_image_get_load(buffer_p, images_noffset,
663 (ulong *)loadable);
664 if (ret < 0) {
665 buffer_p = (u32 *)DEFAULT_DDR_LOAD_ADDRESS;
666 debug("FPGA: No loadable was found.\n");
667 debug("FPGA: Using default DDR load address: 0x%x .\n",
668 DEFAULT_DDR_LOAD_ADDRESS);
669 } else {
670 buffer_p = (u32 *)*loadable;
671 debug("FPGA: Found loadable address = 0x%x.\n",
672 *loadable);
673 }
674
675 buffer_size = rbf_size;
676 }
677
678 debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
679 rbf_offset, rbf_size);
680
681 fpga_loadfs->remaining = rbf_size;
682
683 /*
684 * Determine buffer size vs bitstream size, and calculating number of
685 * chunk by chunk transfer is required due to smaller buffer size
686 * compare to bitstream
687 */
688 if (rbf_size <= buffer_size) {
689 /* Loading whole bitstream into buffer */
690 buffer_size = rbf_size;
691 fpga_loadfs->remaining = 0;
692 } else {
693 fpga_loadfs->remaining -= buffer_size;
694 }
695
696 fpga_loadfs->offset = rbf_offset;
697 /* Loading bitstream into buffer */
698 ret = request_firmware_into_buf(dev,
699 fpga_loadfs->fpga_fsinfo->filename,
700 buffer_p, buffer_size,
701 fpga_loadfs->offset);
702 if (ret < 0) {
703 debug("FPGA: Failed to read bitstream from flash.\n");
704 return -ENOENT;
705 }
706
707 /* Getting info about bitstream types */
708 get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p);
709
710 /* Update next reading bitstream offset */
711 fpga_loadfs->offset += buffer_size;
712
713 /* Update the final addr for bitstream */
714 *buffer = (u32)buffer_p;
715
716 /* Update the size of bitstream to be programmed into FPGA */
717 *buffer_bsize = buffer_size;
718
719 return 0;
720}
721
722static int subsequent_loading_rbf_to_buffer(struct udevice *dev,
723 struct fpga_loadfs_info *fpga_loadfs,
724 u32 *buffer, size_t *buffer_bsize)
725{
726 int ret = 0;
727 u32 *buffer_p = (u32 *)*buffer;
728
729 /* Read the bitstream chunk by chunk. */
730 if (fpga_loadfs->remaining > *buffer_bsize) {
731 fpga_loadfs->remaining -= *buffer_bsize;
732 } else {
733 *buffer_bsize = fpga_loadfs->remaining;
734 fpga_loadfs->remaining = 0;
735 }
736
737 ret = request_firmware_into_buf(dev,
738 fpga_loadfs->fpga_fsinfo->filename,
739 buffer_p, *buffer_bsize,
740 fpga_loadfs->offset);
741 if (ret < 0) {
742 debug("FPGA: Failed to read bitstream from flash.\n");
743 return -ENOENT;
744 }
745
746 /* Update next reading bitstream offset */
747 fpga_loadfs->offset += *buffer_bsize;
748
749 return 0;
750}
751
752int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
753 u32 offset)
754{
755 struct fpga_loadfs_info fpga_loadfs;
756 struct udevice *dev;
757 int status, ret, size;
758 u32 buffer = (uintptr_t)buf;
759 size_t buffer_sizebytes = bsize;
760 size_t buffer_sizebytes_ori = bsize;
761 size_t total_sizeof_image = 0;
762 ofnode node;
763 const fdt32_t *phandle_p;
764 u32 phandle;
765
766 node = get_fpga_mgr_ofnode(ofnode_null());
767
768 if (ofnode_valid(node)) {
769 phandle_p = ofnode_get_property(node, "firmware-loader", &size);
770 if (!phandle_p) {
771 node = ofnode_path("/chosen");
772 if (!ofnode_valid(node)) {
773 debug("FPGA: /chosen node was not found.\n");
774 return -ENOENT;
775 }
776
777 phandle_p = ofnode_get_property(node, "firmware-loader",
778 &size);
779 if (!phandle_p) {
780 debug("FPGA: firmware-loader property was not");
781 debug(" found.\n");
782 return -ENOENT;
783 }
784 }
785 } else {
786 debug("FPGA: FPGA manager node was not found.\n");
787 return -ENOENT;
788 }
789
790 phandle = fdt32_to_cpu(*phandle_p);
791 ret = uclass_get_device_by_phandle_id(UCLASS_FS_FIRMWARE_LOADER,
792 phandle, &dev);
793 if (ret)
794 return ret;
795
796 memset(&fpga_loadfs, 0, sizeof(fpga_loadfs));
797
798 fpga_loadfs.fpga_fsinfo = fpga_fsinfo;
799 fpga_loadfs.offset = offset;
800
801 printf("FPGA: Checking FPGA configuration setting ...\n");
802
803 /*
804 * Note: Both buffer and buffer_sizebytes values can be altered by
805 * function below.
806 */
807 ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
808 &buffer_sizebytes);
809 if (ret == 1) {
810 printf("FPGA: Skipping configuration ...\n");
811 return 0;
812 } else if (ret) {
813 return ret;
814 }
815
816 if (fpga_loadfs.rbfinfo.section == core_section &&
817 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
818 debug("FPGA : Must be in Early Release mode to program ");
819 debug("core bitstream.\n");
820 return -EPERM;
821 }
822
823 /* Disable all signals from HPS peripheral controller to FPGA */
db5741f7 824 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
0a42a132
TFC		 825
826 /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
827 socfpga_bridges_reset();
828
829 if (fpga_loadfs.rbfinfo.section == periph_section) {
830 /* Initialize the FPGA Manager */
831 status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes);
832 if (status) {
833 debug("FPGA: Init with peripheral bitstream failed.\n");
834 return -EPERM;
835 }
836 }
837
838 /* Transfer bitstream to FPGA Manager */
839 fpgamgr_program_write((void *)buffer, buffer_sizebytes);
840
841 total_sizeof_image += buffer_sizebytes;
842
843 while (fpga_loadfs.remaining) {
844 ret = subsequent_loading_rbf_to_buffer(dev,
845 &fpga_loadfs,
846 &buffer,
847 &buffer_sizebytes_ori);
848
849 if (ret)
850 return ret;
851
852 /* Transfer data to FPGA Manager */
853 fpgamgr_program_write((void *)buffer,
854 buffer_sizebytes_ori);
855
856 total_sizeof_image += buffer_sizebytes_ori;
857
858 WATCHDOG_RESET();
859 }
860
861 if (fpga_loadfs.rbfinfo.section == periph_section) {
862 if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
863 config_pins(gd->fdt_blob, "shared");
864 puts("FPGA: Early Release Succeeded.\n");
865 } else {
866 debug("FPGA: Failed to see Early Release.\n");
867 return -EIO;
868 }
869
870 /* For monolithic bitstream */
871 if (is_fpgamgr_user_mode()) {
872 /* Ensure the FPGA entering config done */
873 status = fpgamgr_program_finish();
874 if (status)
875 return status;
876
877 config_pins(gd->fdt_blob, "fpga");
878 puts("FPGA: Enter user mode.\n");
879 }
880 } else if (fpga_loadfs.rbfinfo.section == core_section) {
881 /* Ensure the FPGA entering config done */
882 status = fpgamgr_program_finish();
883 if (status)
884 return status;
885
886 config_pins(gd->fdt_blob, "fpga");
887 puts("FPGA: Enter user mode.\n");
888 } else {
889 debug("FPGA: Config Error: Unsupported bitstream type.\n");
890 return -ENOEXEC;
891 }
892
893 return (int)total_sizeof_image;
894}
895
896void fpgamgr_program(const void *buf, size_t bsize, u32 offset)
897{
898 fpga_fs_info fpga_fsinfo;
899
900 fpga_fsinfo.filename = get_fpga_filename();
901
902 if (fpga_fsinfo.filename)
903 socfpga_loadfs(&fpga_fsinfo, buf, bsize, offset);
904}
905#endif
906
907/* This function is used to load the core bitstream from the OCRAM. */
2baa9972
TFC		 908int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
909{
0a42a132
TFC		 910 unsigned long status;
911 struct rbf_info rbfinfo;
912
913 memset(&rbfinfo, 0, sizeof(rbfinfo));
2baa9972 914
f4b53b24 915 /* Disable all signals from hps peripheral controller to fpga */
db5741f7 916 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
2baa9972 917
f4b53b24 918 /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
2baa9972
TFC		 919 socfpga_bridges_reset();
920
0a42a132
TFC		 921 /* Getting info about bitstream types */
922 get_rbf_image_info(&rbfinfo, (u16 *)rbf_data);
923
924 if (rbfinfo.section == periph_section) {
925 /* Initialize the FPGA Manager */
926 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
927 if (status)
928 return status;
929 }
2baa9972 930
0a42a132
TFC		 931 if (rbfinfo.section == core_section &&
932 !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
933 debug("FPGA : Must be in early release mode to program ");
934 debug("core bitstream.\n");
935 return -EPERM;
936 }
937
938 /* Write the bitstream to FPGA Manager */
2baa9972
TFC		 939 fpgamgr_program_write(rbf_data, rbf_size);
940
0a42a132 941 status = fpgamgr_program_finish();
a89c2adc
DW		 942 if (status)
943 return status;
944
945 config_pins(gd->fdt_blob, "fpga");
946 puts("FPGA: Enter user mode.\n");
0a42a132
TFC		 947
948 return status;
2baa9972 949}
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