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common: Move some board functions out of common.h
[J-u-boot.git] / board / freescale / t208xqds / t208xqds.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
c4d0e811
SL		 2/*
3 * Copyright 2009-2013 Freescale Semiconductor, Inc.
c4d0e811
SL		 4 */
5
6#include <common.h>
7#include <command.h>
7b51b576 8#include <env.h>
c4d0e811 9#include <i2c.h>
5255932f 10#include <init.h>
c4d0e811
SL		 11#include <netdev.h>
12#include <linux/compiler.h>
13#include <asm/mmu.h>
14#include <asm/processor.h>
15#include <asm/immap_85xx.h>
16#include <asm/fsl_law.h>
17#include <asm/fsl_serdes.h>
c4d0e811
SL		 18#include <asm/fsl_liodn.h>
19#include <fm_eth.h>
20
21#include "../common/qixis.h"
22#include "../common/vsc3316_3308.h"
3ad2737e 23#include "../common/vid.h"
254887a5
SL		 24#include "t208xqds.h"
25#include "t208xqds_qixis.h"
c4d0e811
SL		 26
27DECLARE_GLOBAL_DATA_PTR;
28
29int checkboard(void)
30{
31 char buf[64];
32 u8 sw;
33 struct cpu_type *cpu = gd->arch.cpu;
34 static const char *freq[4] = {
35 "100.00MHZ(from 8T49N222A)", "125.00MHz",
36 "156.25MHZ", "100.00MHz"
37 };
38
39 printf("Board: %sQDS, ", cpu->name);
40 sw = QIXIS_READ(arch);
41 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
42 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
43
1576b558
SL		 44#ifdef CONFIG_SDCARD
45 puts("SD/MMC\n");
46#elif CONFIG_SPIFLASH
47 puts("SPI\n");
48#else
c4d0e811
SL		 49 sw = QIXIS_READ(brdcfg[0]);
50 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
51
52 if (sw < 0x8)
53 printf("vBank%d\n", sw);
54 else if (sw == 0x8)
55 puts("Promjet\n");
56 else if (sw == 0x9)
57 puts("NAND\n");
58 else
59 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
1576b558 60#endif
c4d0e811
SL		 61
62 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
63 qixis_read_tag(buf), (int)qixis_read_minor());
64 /* the timestamp string contains "\n" at the end */
65 printf(" on %s", qixis_read_time(buf));
66
67 puts("SERDES Reference Clocks:\n");
68 sw = QIXIS_READ(brdcfg[2]);
69 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
70 freq[(sw >> 4) & 0x3]);
71 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
72 freq[sw & 0x3]);
73
74 return 0;
75}
76
77int select_i2c_ch_pca9547(u8 ch)
78{
79 int ret;
80
81 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
82 if (ret) {
83 puts("PCA: failed to select proper channel\n");
84 return ret;
85 }
86
87 return 0;
88}
89
3ad2737e
YZ		 90int i2c_multiplexer_select_vid_channel(u8 channel)
91{
92 return select_i2c_ch_pca9547(channel);
93}
94
c4d0e811
SL		 95int brd_mux_lane_to_slot(void)
96{
97 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
254887a5 98 u32 srds_prtcl_s1;
c4d0e811
SL		 99
100 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
101 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
102 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
80d26188 103#if defined(CONFIG_TARGET_T2080QDS)
254887a5 104 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
c4d0e811
SL		 105 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
106 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
254887a5 107#endif
c4d0e811
SL		 108
109 switch (srds_prtcl_s1) {
110 case 0:
111 /* SerDes1 is not enabled */
112 break;
80d26188 113#if defined(CONFIG_TARGET_T2080QDS)
9752eb64 114 case 0x1b:
c4d0e811 115 case 0x1c:
c4d0e811 116 case 0xa2:
c4d0e811
SL		 117 /* SD1(A:D) => SLOT3 SGMII
118 * SD1(G:H) => SLOT1 SGMII
119 */
1576b558
SL		 120 QIXIS_WRITE(brdcfg[12], 0x1a);
121 break;
122 case 0x94:
123 case 0x95:
124 /* SD1(A:B) => SLOT3 [email protected]
125 * SD1(C:D) => SFP Module, [email protected]
126 * SD1(E:H) => SLOT1 [email protected]
127 */
128 case 0x96:
129 /* SD1(A:B) => SLOT3 [email protected]
130 * SD1(C) => SFP Module, [email protected]
131 * SD1(D) => SFP Module, [email protected]
132 * SD1(E:H) => SLOT1 PCIe4 x4
133 */
134 QIXIS_WRITE(brdcfg[12], 0x3a);
c4d0e811 135 break;
9752eb64 136 case 0x50:
c4d0e811
SL		 137 case 0x51:
138 /* SD1(A:D) => SLOT3 XAUI
139 * SD1(E) => SLOT1 PCIe4
140 * SD1(F:H) => SLOT2 SGMII
141 */
142 QIXIS_WRITE(brdcfg[12], 0x15);
143 break;
144 case 0x66:
145 case 0x67:
146 /* SD1(A:D) => XFI cage
147 * SD1(E:H) => SLOT1 PCIe4
148 */
149 QIXIS_WRITE(brdcfg[12], 0xfe);
150 break;
9752eb64 151 case 0x6a:
c4d0e811
SL		 152 case 0x6b:
153 /* SD1(A:D) => XFI cage
154 * SD1(E) => SLOT1 PCIe4
155 * SD1(F:H) => SLOT2 SGMII
156 */
157 QIXIS_WRITE(brdcfg[12], 0xf1);
158 break;
159 case 0x6c:
160 case 0x6d:
161 /* SD1(A:B) => XFI cage
162 * SD1(C:D) => SLOT3 SGMII
163 * SD1(E:H) => SLOT1 PCIe4
164 */
165 QIXIS_WRITE(brdcfg[12], 0xda);
166 break;
1576b558
SL		 167 case 0x6e:
168 /* SD1(A:B) => SFP Module, XFI
169 * SD1(C:D) => SLOT3 SGMII
170 * SD1(E:F) => SLOT1 PCIe4 x2
171 * SD1(G:H) => SLOT2 SGMII
172 */
173 QIXIS_WRITE(brdcfg[12], 0xd9);
174 break;
175 case 0xda:
176 /* SD1(A:H) => SLOT3 PCIe3 x8
177 */
178 QIXIS_WRITE(brdcfg[12], 0x0);
179 break;
180 case 0xc8:
181 /* SD1(A) => SLOT3 PCIe3 x1
182 * SD1(B) => SFP Module, [email protected]
183 * SD1(C:D) => SFP Module, [email protected]
184 * SD1(E:F) => SLOT1 PCIe4 x2
185 * SD1(G:H) => SLOT2 SGMII
186 */
187 QIXIS_WRITE(brdcfg[12], 0x79);
188 break;
189 case 0xab:
190 /* SD1(A:D) => SLOT3 PCIe3 x4
191 * SD1(E:H) => SLOT1 PCIe4 x4
192 */
193 QIXIS_WRITE(brdcfg[12], 0x1a);
194 break;
146ded4d 195#elif defined(CONFIG_TARGET_T2081QDS)
9752eb64 196 case 0x50:
254887a5
SL		 197 case 0x51:
198 /* SD1(A:D) => SLOT2 XAUI
199 * SD1(E) => SLOT1 PCIe4 x1
200 * SD1(F:H) => SLOT3 SGMII
201 */
202 QIXIS_WRITE(brdcfg[12], 0x98);
203 QIXIS_WRITE(brdcfg[13], 0x70);
204 break;
9752eb64 205 case 0x6a:
254887a5
SL		 206 case 0x6b:
207 /* SD1(A:D) => XFI SFP Module
208 * SD1(E) => SLOT1 PCIe4 x1
209 * SD1(F:H) => SLOT3 SGMII
210 */
211 QIXIS_WRITE(brdcfg[12], 0x80);
212 QIXIS_WRITE(brdcfg[13], 0x70);
213 break;
214 case 0x6c:
254887a5
SL		 215 case 0x6d:
216 /* SD1(A:B) => XFI SFP Module
217 * SD1(C:D) => SLOT2 SGMII
218 * SD1(E:H) => SLOT1 PCIe4 x4
219 */
220 QIXIS_WRITE(brdcfg[12], 0xe8);
221 QIXIS_WRITE(brdcfg[13], 0x0);
222 break;
223 case 0xaa:
224 case 0xab:
225 /* SD1(A:D) => SLOT2 PCIe3 x4
226 * SD1(F:H) => SLOT1 SGMI4 x4
227 */
228 QIXIS_WRITE(brdcfg[12], 0xf8);
229 QIXIS_WRITE(brdcfg[13], 0x0);
230 break;
231 case 0xca:
232 case 0xcb:
233 /* SD1(A) => SLOT2 PCIe3 x1
234 * SD1(B) => SLOT7 SGMII
235 * SD1(C) => SLOT6 SGMII
236 * SD1(D) => SLOT5 SGMII
237 * SD1(E) => SLOT1 PCIe4 x1
238 * SD1(F:H) => SLOT3 SGMII
239 */
240 QIXIS_WRITE(brdcfg[12], 0x80);
241 QIXIS_WRITE(brdcfg[13], 0x70);
242 break;
243 case 0xde:
244 case 0xdf:
245 /* SD1(A:D) => SLOT2 PCIe3 x4
246 * SD1(E) => SLOT1 PCIe4 x1
247 * SD1(F) => SLOT4 PCIe1 x1
248 * SD1(G) => SLOT3 PCIe2 x1
249 * SD1(H) => SLOT7 SGMII
250 */
251 QIXIS_WRITE(brdcfg[12], 0x98);
252 QIXIS_WRITE(brdcfg[13], 0x25);
253 break;
254 case 0xf2:
255 /* SD1(A) => SLOT2 PCIe3 x1
256 * SD1(B:D) => SLOT7 SGMII
257 * SD1(E) => SLOT1 PCIe4 x1
258 * SD1(F) => SLOT4 PCIe1 x1
259 * SD1(G) => SLOT3 PCIe2 x1
260 * SD1(H) => SLOT7 SGMII
261 */
262 QIXIS_WRITE(brdcfg[12], 0x81);
263 QIXIS_WRITE(brdcfg[13], 0xa5);
264 break;
265#endif
c4d0e811
SL		 266 default:
267 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
268 srds_prtcl_s1);
269 return -1;
270 }
271
80d26188 272#ifdef CONFIG_TARGET_T2080QDS
c4d0e811
SL		 273 switch (srds_prtcl_s2) {
274 case 0:
275 /* SerDes2 is not enabled */
276 break;
277 case 0x01:
278 case 0x02:
279 /* SD2(A:H) => SLOT4 PCIe1 */
1576b558 280 QIXIS_WRITE(brdcfg[13], 0x10);
c4d0e811
SL		 281 break;
282 case 0x15:
283 case 0x16:
284 /*
285 * SD2(A:D) => SLOT4 PCIe1
286 * SD2(E:F) => SLOT5 PCIe2
287 * SD2(G:H) => SATA1,SATA2
288 */
289 QIXIS_WRITE(brdcfg[13], 0xb0);
290 break;
291 case 0x18:
292 /*
293 * SD2(A:D) => SLOT4 PCIe1
294 * SD2(E:F) => SLOT5 Aurora
295 * SD2(G:H) => SATA1,SATA2
296 */
1576b558 297 QIXIS_WRITE(brdcfg[13], 0x78);
c4d0e811
SL		 298 break;
299 case 0x1f:
300 /*
301 * SD2(A:D) => SLOT4 PCIe1
302 * SD2(E:H) => SLOT5 PCIe2
303 */
304 QIXIS_WRITE(brdcfg[13], 0xa0);
305 break;
306 case 0x29:
307 case 0x2d:
308 case 0x2e:
309 /*
310 * SD2(A:D) => SLOT4 SRIO2
311 * SD2(E:H) => SLOT5 SRIO1
312 */
1576b558
SL		 313 QIXIS_WRITE(brdcfg[13], 0xa0);
314 break;
315 case 0x36:
316 /*
317 * SD2(A:D) => SLOT4 SRIO2
318 * SD2(E:F) => Aurora
319 * SD2(G:H) => SATA1,SATA2
320 */
321 QIXIS_WRITE(brdcfg[13], 0x78);
c4d0e811
SL		 322 break;
323 default:
324 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
325 srds_prtcl_s2);
326 return -1;
327 }
254887a5 328#endif
c4d0e811
SL		 329 return 0;
330}
331
332int board_early_init_r(void)
333{
334 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682 335 int flash_esel = find_tlb_idx((void *)flashbase, 1);
c4d0e811
SL		 336
337 /*
338 * Remap Boot flash + PROMJET region to caching-inhibited
339 * so that flash can be erased properly.
340 */
341
342 /* Flush d-cache and invalidate i-cache of any FLASH data */
343 flush_dcache();
344 invalidate_icache();
345
9d045682
YS		 346 if (flash_esel == -1) {
347 /* very unlikely unless something is messed up */
348 puts("Error: Could not find TLB for FLASH BASE\n");
349 flash_esel = 2; /* give our best effort to continue */
350 } else {
351 /* invalidate existing TLB entry for flash + promjet */
352 disable_tlb(flash_esel);
353 }
c4d0e811
SL		 354
355 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
356 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
357 0, flash_esel, BOOKE_PAGESZ_256M, 1);
358
c4d0e811
SL		 359 /* Disable remote I2C connection to qixis fpga */
360 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
361
3ad2737e
YZ		 362 /*
363 * Adjust core voltage according to voltage ID
364 * This function changes I2C mux to channel 2.
365 */
366 if (adjust_vdd(0))
367 printf("Warning: Adjusting core voltage failed.\n");
368
c4d0e811
SL		 369 brd_mux_lane_to_slot();
370 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
371
372 return 0;
373}
374
375unsigned long get_board_sys_clk(void)
376{
377 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
378#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
379 /* use accurate clock measurement */
380 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
381 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
382 u32 val;
383
384 val = freq * base;
385 if (val) {
386 debug("SYS Clock measurement is: %d\n", val);
387 return val;
388 } else {
389 printf("Warning: SYS clock measurement is invalid, ");
390 printf("using value from brdcfg1.\n");
391 }
392#endif
393
394 switch (sysclk_conf & 0x0F) {
395 case QIXIS_SYSCLK_83:
396 return 83333333;
397 case QIXIS_SYSCLK_100:
398 return 100000000;
399 case QIXIS_SYSCLK_125:
400 return 125000000;
401 case QIXIS_SYSCLK_133:
402 return 133333333;
403 case QIXIS_SYSCLK_150:
404 return 150000000;
405 case QIXIS_SYSCLK_160:
406 return 160000000;
407 case QIXIS_SYSCLK_166:
408 return 166666666;
409 }
410 return 66666666;
411}
412
413unsigned long get_board_ddr_clk(void)
414{
415 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
416#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
417 /* use accurate clock measurement */
418 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
419 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
420 u32 val;
421
422 val = freq * base;
423 if (val) {
424 debug("DDR Clock measurement is: %d\n", val);
425 return val;
426 } else {
427 printf("Warning: DDR clock measurement is invalid, ");
428 printf("using value from brdcfg1.\n");
429 }
430#endif
431
432 switch ((ddrclk_conf & 0x30) >> 4) {
433 case QIXIS_DDRCLK_100:
434 return 100000000;
435 case QIXIS_DDRCLK_125:
436 return 125000000;
437 case QIXIS_DDRCLK_133:
438 return 133333333;
439 }
440 return 66666666;
441}
442
443int misc_init_r(void)
444{
445 return 0;
446}
447
e895a4b0 448int ft_board_setup(void *blob, bd_t *bd)
c4d0e811
SL		 449{
450 phys_addr_t base;
451 phys_size_t size;
452
453 ft_cpu_setup(blob, bd);
454
723806cc
SG		 455 base = env_get_bootm_low();
456 size = env_get_bootm_size();
c4d0e811
SL		 457
458 fdt_fixup_memory(blob, (u64)base, (u64)size);
459
460#ifdef CONFIG_PCI
461 pci_of_setup(blob, bd);
462#endif
463
464 fdt_fixup_liodn(blob);
a5c289b9 465 fsl_fdt_fixup_dr_usb(blob, bd);
c4d0e811
SL		 466
467#ifdef CONFIG_SYS_DPAA_FMAN
468 fdt_fixup_fman_ethernet(blob);
469 fdt_fixup_board_enet(blob);
470#endif
e895a4b0
SG		 471
472 return 0;
c4d0e811 473}
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