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Commit | Line | Data |
---|---|---|
54119882 | 1 | CONFIG_PPC=y |
278b90ce | 2 | CONFIG_SYS_TEXT_BASE=0xF0000000 |
05577fa5 | 3 | CONFIG_KM_DEF_NETDEV="eth1" |
a09fea1d | 4 | CONFIG_ENV_SIZE=0x4000 |
a09fea1d | 5 | CONFIG_ENV_SECT_SIZE=0x20000 |
2bba7807 | 6 | CONFIG_DEFAULT_DEVICE_TREE="kmtegr1" |
4244429f | 7 | CONFIG_BOOTCOUNT_BOOTLIMIT=3 |
ff3bb0c4 | 8 | CONFIG_SYS_CLK_FREQ=66000000 |
54119882 | 9 | CONFIG_MPC83xx=y |
93de2530 | 10 | CONFIG_HIGH_BATS=y |
0e0674fc | 11 | CONFIG_TARGET_KMTEGR1=y |
21c1502a MS |
12 | CONFIG_SYSTEM_PLL_VCO_DIV_2=y |
13 | CONFIG_CORE_PLL_RATIO_2_1=y | |
14 | CONFIG_QUICC_MULT_FACTOR_3=y | |
15 | CONFIG_BOOT_MEMORY_SPACE_LOW=y | |
16 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
30915ab9 MS |
17 | CONFIG_BAT0=y |
18 | CONFIG_BAT0_NAME="SDRAM" | |
19 | CONFIG_BAT0_BASE=0x00000000 | |
20 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
21 | CONFIG_BAT0_ACCESS_RW=y | |
22 | CONFIG_BAT0_ICACHE_INHIBITED=y | |
23 | CONFIG_BAT0_ICACHE_GUARDED=y | |
24 | CONFIG_BAT0_DCACHE_INHIBITED=y | |
25 | CONFIG_BAT0_DCACHE_GUARDED=y | |
26 | CONFIG_BAT0_USER_MODE_VALID=y | |
27 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
28 | CONFIG_BAT1=y | |
29 | CONFIG_BAT1_NAME="IMMR" | |
30 | CONFIG_BAT1_BASE=0xE0000000 | |
31 | CONFIG_BAT1_LENGTH_4_MBYTES=y | |
32 | CONFIG_BAT1_ACCESS_RW=y | |
33 | CONFIG_BAT1_ICACHE_INHIBITED=y | |
34 | CONFIG_BAT1_ICACHE_GUARDED=y | |
35 | CONFIG_BAT1_DCACHE_INHIBITED=y | |
36 | CONFIG_BAT1_DCACHE_GUARDED=y | |
37 | CONFIG_BAT1_USER_MODE_VALID=y | |
38 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
39 | CONFIG_BAT2=y | |
40 | CONFIG_BAT2_NAME="KMBEC_FPGA" | |
41 | CONFIG_BAT2_BASE=0xE8000000 | |
42 | CONFIG_BAT2_LENGTH_128_MBYTES=y | |
43 | CONFIG_BAT2_ACCESS_RW=y | |
44 | CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y | |
45 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
46 | CONFIG_BAT2_DCACHE_GUARDED=y | |
47 | CONFIG_BAT2_USER_MODE_VALID=y | |
48 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
49 | CONFIG_BAT3=y | |
50 | CONFIG_BAT3_NAME="FLASH" | |
51 | CONFIG_BAT3_BASE=0xF0000000 | |
52 | CONFIG_BAT3_LENGTH_256_MBYTES=y | |
53 | CONFIG_BAT3_ACCESS_RW=y | |
54 | CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y | |
55 | CONFIG_BAT3_DCACHE_INHIBITED=y | |
56 | CONFIG_BAT3_DCACHE_GUARDED=y | |
57 | CONFIG_BAT3_USER_MODE_VALID=y | |
58 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y | |
59 | CONFIG_BAT4=y | |
60 | CONFIG_BAT4_NAME="STACK_IN_DCACHE" | |
61 | CONFIG_BAT4_BASE=0xE6000000 | |
62 | CONFIG_BAT4_ACCESS_RW=y | |
63 | CONFIG_BAT4_USER_MODE_VALID=y | |
64 | CONFIG_BAT4_SUPERVISOR_MODE_VALID=y | |
65 | CONFIG_BAT6=y | |
66 | CONFIG_BAT6_NAME="APP2" | |
67 | CONFIG_BAT6_BASE=0xB0000000 | |
68 | CONFIG_BAT6_LENGTH_256_MBYTES=y | |
69 | CONFIG_BAT6_ACCESS_RW=y | |
70 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y | |
71 | CONFIG_BAT6_DCACHE_INHIBITED=y | |
72 | CONFIG_BAT6_DCACHE_GUARDED=y | |
73 | CONFIG_BAT6_USER_MODE_VALID=y | |
74 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y | |
9c5df7a2 MS |
75 | CONFIG_LBLAW0=y |
76 | CONFIG_LBLAW0_BASE=0xF0000000 | |
77 | CONFIG_LBLAW0_NAME="FLASH" | |
78 | CONFIG_LBLAW0_LENGTH_256_MBYTES=y | |
79 | CONFIG_LBLAW1=y | |
80 | CONFIG_LBLAW1_BASE=0xE8000000 | |
81 | CONFIG_LBLAW1_NAME="KMBEC_FPGA" | |
82 | CONFIG_LBLAW1_LENGTH_128_MBYTES=y | |
83 | CONFIG_LBLAW3=y | |
84 | CONFIG_LBLAW3_BASE=0xB0000000 | |
85 | CONFIG_LBLAW3_NAME="APP2" | |
86 | CONFIG_LBLAW3_LENGTH_256_MBYTES=y | |
344a0e43 TR |
87 | CONFIG_ELBC_BR0_OR0=y |
88 | CONFIG_BR0_OR0_NAME="FLASH" | |
89 | CONFIG_BR0_OR0_BASE=0xF0000000 | |
90 | CONFIG_BR0_PORTSIZE_16BIT=y | |
91 | CONFIG_OR0_AM_256_MBYTES=y | |
92 | CONFIG_OR0_SCY_5=y | |
93 | CONFIG_OR0_CSNT_EARLIER=y | |
94 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y | |
95 | CONFIG_OR0_TRLX_RELAXED=y | |
96 | CONFIG_OR0_EAD_EXTRA=y | |
97 | CONFIG_ELBC_BR1_OR1=y | |
98 | CONFIG_BR1_OR1_NAME="KMBEC_FPGA" | |
99 | CONFIG_BR1_OR1_BASE=0xE8000000 | |
100 | CONFIG_OR1_AM_128_MBYTES=y | |
101 | CONFIG_OR1_SCY_2=y | |
102 | CONFIG_OR1_CSNT_EARLIER=y | |
103 | CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y | |
104 | CONFIG_OR1_TRLX_RELAXED=y | |
105 | CONFIG_OR1_EAD_EXTRA=y | |
106 | CONFIG_ELBC_BR3_OR3=y | |
107 | CONFIG_BR3_OR3_NAME="APP2" | |
108 | CONFIG_BR3_OR3_BASE=0xB0000000 | |
109 | CONFIG_BR3_PORTSIZE_16BIT=y | |
110 | CONFIG_OR3_AM_256_MBYTES=y | |
111 | CONFIG_OR3_SCY_5=y | |
be5abb0a MS |
112 | CONFIG_HID0_FINAL_EMCP=y |
113 | CONFIG_HID0_FINAL_ICE=y | |
114 | CONFIG_HID2_HBE=y | |
73df96a3 MS |
115 | CONFIG_ACR_PIPE_DEP_4=y |
116 | CONFIG_ACR_RPTCNT_4=y | |
117 | CONFIG_ACR_APARK_MASTER=y | |
118 | CONFIG_ACR_PARKM_USB_I2C1_BOOT=y | |
344a0e43 TR |
119 | CONFIG_LCRR_EADC_1=y |
120 | CONFIG_LCRR_CLKDIV_2=y | |
49c8ef0e | 121 | CONFIG_SYS_LOAD_ADDR=0x100000 |
73223f0e SG |
122 | CONFIG_OF_BOARD_SETUP=y |
123 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
9e39003e | 124 | CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" |
78d1e1d0 TR |
125 | CONFIG_AUTOBOOT_KEYED=y |
126 | CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" | |
127 | CONFIG_AUTOBOOT_STOP_STR=" " | |
0817daa7 TR |
128 | CONFIG_BOARD_EARLY_INIT_R=y |
129 | CONFIG_LAST_STAGE_INIT=y | |
130 | CONFIG_MISC_INIT_R=y | |
131 | CONFIG_HUSH_PARSER=y | |
ad12dc18 | 132 | CONFIG_CMD_IMLS=y |
89cb2b5f TR |
133 | CONFIG_CMD_ASKENV=y |
134 | CONFIG_CMD_GREPENV=y | |
a1dc980d | 135 | CONFIG_CMD_EEPROM=y |
88cd7d0e TR |
136 | CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 |
137 | CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 | |
78d1e1d0 | 138 | CONFIG_CMD_I2C=y |
88663126 | 139 | CONFIG_CMD_NAND=y |
78d1e1d0 | 140 | CONFIG_CMD_DHCP=y |
89cb2b5f | 141 | CONFIG_CMD_MII=y |
78d1e1d0 | 142 | CONFIG_CMD_PING=y |
b8682a7f | 143 | CONFIG_CMD_JFFS2=y |
cbabe7f8 | 144 | CONFIG_CMD_MTDPARTS=y |
43ede0bc TR |
145 | CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app" |
146 | CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),256k(qe-fw),128k(env),128k(envred),-(ubi0);app:-(ubi1);" | |
3bd25cb5 | 147 | CONFIG_CMD_DIAG=y |
8f2fe0c8 | 148 | CONFIG_CMD_UBI=y |
d56b4b19 | 149 | # CONFIG_CMD_UBIFS is not set |
e91907a1 | 150 | CONFIG_ENV_OVERWRITE=y |
cb6617a7 | 151 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
a09fea1d TR |
152 | CONFIG_ENV_ADDR=0xF0100000 |
153 | CONFIG_ENV_ADDR_REDUND=0xF0120000 | |
0817daa7 | 154 | CONFIG_VERSION_VARIABLE=y |
d1ec9461 | 155 | CONFIG_BOOTCOUNT_LIMIT=y |
7bdfe859 HS |
156 | CONFIG_DM_BOOTCOUNT=y |
157 | CONFIG_BOOTCOUNT_MEM=y | |
55dabcc8 | 158 | CONFIG_SYS_I2C_LEGACY=y |
6d5d0c95 TR |
159 | CONFIG_SYS_I2C_FSL=y |
160 | CONFIG_SYS_FSL_I2C_OFFSET=0x3000 | |
161 | CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y | |
162 | CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 | |
163 | CONFIG_SYS_I2C_SLAVE=0x7F | |
164 | CONFIG_SYS_I2C_SPEED=200000 | |
8728c97e | 165 | # CONFIG_MMC is not set |
d4c2f6b7 | 166 | CONFIG_MTD=y |
e856bdcf | 167 | CONFIG_MTD_NOR_FLASH=y |
2fe88d45 AF |
168 | CONFIG_FLASH_CFI_DRIVER=y |
169 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
170 | CONFIG_FLASH_CFI_MTD=y | |
171 | CONFIG_SYS_FLASH_PROTECTION=y | |
172 | CONFIG_SYS_FLASH_CFI=y | |
0cfccb54 | 173 | CONFIG_MTD_RAW_NAND=y |
7bdfe859 HS |
174 | CONFIG_PHY_SMSC=y |
175 | CONFIG_PHY_FIXED=y | |
176 | CONFIG_DM_ETH_PHY=y | |
177 | CONFIG_QE_UEC=y | |
af27382e | 178 | # CONFIG_PCI is not set |
7bdfe859 | 179 | # CONFIG_PINCTRL_FULL is not set |
cc1e98b5 TR |
180 | CONFIG_QE=y |
181 | CONFIG_SYS_QE_FMAN_FW_IN_NOR=y | |
9e39003e | 182 | CONFIG_SYS_NS16550=y |
6ef2f901 | 183 | CONFIG_BCH=y |