projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ddc935fc MS |
1 | CONFIG_PPC=y |
| 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 | |
| a09fea1d TR |
3 | CONFIG_ENV_SIZE=0x2000 |
| 4 | CONFIG_ENV_SECT_SIZE=0x20000 | |
| 7cfbba36 | 5 | CONFIG_SYS_MALLOC_LEN=0x40000 |
| ff3bb0c4 | 6 | CONFIG_SYS_CLK_FREQ=66000000 |
| ddc935fc | 7 | CONFIG_MPC83xx=y |
| 93de2530 | 8 | CONFIG_HIGH_BATS=y |
| ddc935fc | 9 | CONFIG_TARGET_MPC8349EMDS_SDRAM=y |
| 21c1502a MS |
10 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y |
| 11 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y | |
| 12 | CONFIG_CORE_PLL_RATIO_2_1=y | |
| 13 | CONFIG_PCI_HOST_MODE_ENABLE=y | |
| 14 | CONFIG_PCI_INT_ARBITER1_ENABLE=y | |
| 15 | CONFIG_PCI_INT_ARBITER2_ENABLE=y | |
| 16 | CONFIG_BOOT_MEMORY_SPACE_LOW=y | |
| 17 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
| 18 | CONFIG_TSEC1_MODE_GMII=y | |
| 19 | CONFIG_TSEC2_MODE_GMII=y | |
| 30915ab9 MS |
20 | CONFIG_BAT0=y |
| 21 | CONFIG_BAT0_NAME="SDRAM" | |
| 22 | CONFIG_BAT0_BASE=0x00000000 | |
| 23 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
| 24 | CONFIG_BAT0_ACCESS_RW=y | |
| 25 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y | |
| 26 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y | |
| 27 | CONFIG_BAT0_USER_MODE_VALID=y | |
| 28 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
| 29 | CONFIG_BAT5=y | |
| 30 | CONFIG_BAT5_NAME="IMMR" | |
| 31 | CONFIG_BAT5_BASE=0xE0000000 | |
| 32 | CONFIG_BAT5_LENGTH_256_MBYTES=y | |
| 33 | CONFIG_BAT5_ACCESS_RW=y | |
| 34 | CONFIG_BAT5_ICACHE_INHIBITED=y | |
| 35 | CONFIG_BAT5_ICACHE_GUARDED=y | |
| 36 | CONFIG_BAT5_DCACHE_INHIBITED=y | |
| 37 | CONFIG_BAT5_DCACHE_GUARDED=y | |
| 38 | CONFIG_BAT5_USER_MODE_VALID=y | |
| 39 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y | |
| 40 | CONFIG_BAT6=y | |
| 41 | CONFIG_BAT6_NAME="STACK_IN_DCACHE" | |
| 42 | CONFIG_BAT6_BASE=0xF0000000 | |
| 43 | CONFIG_BAT6_LENGTH_256_MBYTES=y | |
| 44 | CONFIG_BAT6_ACCESS_RW=y | |
| 45 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y | |
| 46 | CONFIG_BAT6_ICACHE_GUARDED=y | |
| 47 | CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y | |
| 48 | CONFIG_BAT6_DCACHE_GUARDED=y | |
| 49 | CONFIG_BAT6_USER_MODE_VALID=y | |
| 50 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y | |
| 9c5df7a2 MS |
51 | CONFIG_LBLAW0=y |
| 52 | CONFIG_LBLAW0_BASE=0xFE000000 | |
| 53 | CONFIG_LBLAW0_NAME="FLASH" | |
| 54 | CONFIG_LBLAW0_LENGTH_32_MBYTES=y | |
| 55 | CONFIG_LBLAW1=y | |
| 56 | CONFIG_LBLAW1_BASE=0xE2400000 | |
| 57 | CONFIG_LBLAW1_NAME="BCSR" | |
| 58 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y | |
| 59 | CONFIG_LBLAW2=y | |
| 60 | CONFIG_LBLAW2_BASE=0xF0000000 | |
| 61 | CONFIG_LBLAW2_NAME="SDRAM" | |
| 62 | CONFIG_LBLAW2_LENGTH_64_MBYTES=y | |
| fe7d654d MS |
63 | CONFIG_ELBC_BR0_OR0=y |
| 64 | CONFIG_BR0_OR0_NAME="FLASH" | |
| 65 | CONFIG_BR0_OR0_BASE=0xFE000000 | |
| 66 | CONFIG_BR0_PORTSIZE_16BIT=y | |
| 67 | CONFIG_OR0_AM_32_MBYTES=y | |
| 68 | CONFIG_OR0_XAM_SET=y | |
| 69 | CONFIG_OR0_SCY_15=y | |
| 70 | CONFIG_OR0_CSNT_EARLIER=y | |
| 71 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y | |
| 72 | CONFIG_OR0_XACS_EXTENDED=y | |
| 73 | CONFIG_OR0_TRLX_RELAXED=y | |
| 74 | CONFIG_OR0_EHTR_8_CYCLE=y | |
| 75 | CONFIG_OR0_EAD_EXTRA=y | |
| 76 | CONFIG_ELBC_BR1_OR1=y | |
| 77 | CONFIG_BR1_OR1_NAME="BCSR" | |
| 78 | CONFIG_BR1_OR1_BASE=0xE2400000 | |
| 79 | CONFIG_OR1_XAM_SET=y | |
| 80 | CONFIG_OR1_SCY_15=y | |
| 81 | CONFIG_OR1_CSNT_EARLIER=y | |
| 82 | CONFIG_ELBC_BR2_OR2=y | |
| 83 | CONFIG_BR2_OR2_NAME="SDRAM" | |
| 84 | CONFIG_BR2_OR2_BASE=0xF0000000 | |
| 85 | CONFIG_BR2_PORTSIZE_32BIT=y | |
| 86 | CONFIG_BR2_MACHINE_SDRAM=y | |
| 87 | CONFIG_OR2_COLS_9=y | |
| 88 | CONFIG_OR2_ROWS_13=y | |
| 89 | CONFIG_OR2_EAD_EXTRA=y | |
| 344a0e43 TR |
90 | CONFIG_HID0_FINAL_EMCP=y |
| 91 | CONFIG_HID0_FINAL_ICE=y | |
| 92 | CONFIG_HID2_HBE=y | |
| 93 | CONFIG_ACR_PIPE_DEP_4=y | |
| 94 | CONFIG_ACR_RPTCNT_4=y | |
| 95 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y | |
| 96 | CONFIG_LCRR_CLKDIV_4=y | |
| 1cbc10c8 | 97 | CONFIG_PCI_ONE_PCI1=y |
| ddc935fc MS |
98 | CONFIG_OF_BOARD_SETUP=y |
| 99 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
| 100 | CONFIG_BOOTDELAY=6 | |
| 101 | CONFIG_HUSH_PARSER=y | |
| 102 | CONFIG_CMD_IMLS=y | |
| 103 | CONFIG_CMD_I2C=y | |
| 104 | # CONFIG_CMD_SETEXPR is not set | |
| 105 | CONFIG_CMD_MII=y | |
| 106 | CONFIG_CMD_PING=y | |
| 107 | CONFIG_CMD_DATE=y | |
| e91907a1 | 108 | CONFIG_ENV_OVERWRITE=y |
| cb6617a7 | 109 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
| a09fea1d TR |
110 | CONFIG_ENV_ADDR=0xFE080000 |
| 111 | CONFIG_ENV_ADDR_REDUND=0xFE0A0000 | |
| 95372165 TR |
112 | CONFIG_DDR_ECC=y |
| 113 | CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y | |
| 55dabcc8 | 114 | CONFIG_SYS_I2C_LEGACY=y |
| 6d5d0c95 TR |
115 | CONFIG_SYS_I2C_FSL=y |
| 116 | CONFIG_SYS_FSL_I2C_OFFSET=0x3000 | |
| 117 | CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y | |
| 118 | CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 | |
| 119 | CONFIG_SYS_I2C_SLAVE=0x7F | |
| 120 | CONFIG_SYS_I2C_SPEED=400000 | |
| ddc935fc MS |
121 | # CONFIG_MMC is not set |
| 122 | CONFIG_MTD_NOR_FLASH=y | |
| 123 | CONFIG_FLASH_CFI_DRIVER=y | |
| 124 | CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y | |
| 125 | CONFIG_SYS_FLASH_CFI=y | |
| 306881a0 TR |
126 | CONFIG_PHY_ATHEROS=y |
| 127 | CONFIG_PHY_BROADCOM=y | |
| 128 | CONFIG_PHY_DAVICOM=y | |
| 129 | CONFIG_PHY_LXT=y | |
| ddc935fc | 130 | CONFIG_PHY_MARVELL=y |
| 306881a0 TR |
131 | CONFIG_PHY_NATSEMI=y |
| 132 | CONFIG_PHY_REALTEK=y | |
| 133 | CONFIG_PHY_SMSC=y | |
| 134 | CONFIG_PHY_VITESSE=y | |
| ddc935fc | 135 | CONFIG_TSEC_ENET=y |
| ddc935fc MS |
136 | CONFIG_SYS_NS16550=y |
| 137 | CONFIG_SPI=y | |
| ddc935fc | 138 | CONFIG_OF_LIBFDT=y |