[J-u-boot.git] / drivers / i2c / imx_lpi2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016 Freescale Semiconductors, Inc.
 */

#include <errno.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <imx_lpi2c.h>
#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <fdtdec.h>
#include <i2c.h>
#include <dm/device_compat.h>

#define LPI2C_FIFO_SIZE 4
#define LPI2C_NACK_TOUT_MS 1
#define LPI2C_TIMEOUT_MS 100

#define LPI2C_CHUNK_DATA	256U
#define LPI2C_CHUNK_LEN_MIN	1U

static int bus_i2c_init(struct udevice *bus);

/* Weak linked function for overridden by some SoC power function */
int __weak init_i2c_power(unsigned i2c_num)
{
	return 0;
}

static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
{
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 status;

	status = readl(&regs->msr);

	if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
		result = LPI2C_BUSY;

	return result;
}

static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
{
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 val, status;

	status = readl(&regs->msr);
	/* errors to check for */
	status &= LPI2C_MSR_NDF_MASK | LPI2C_MSR_ALF_MASK |
		LPI2C_MSR_FEF_MASK | LPI2C_MSR_PLTF_MASK;

	if (status) {
		if (status & LPI2C_MSR_PLTF_MASK)
			result = LPI2C_PIN_LOW_TIMEOUT_ERR;
		else if (status & LPI2C_MSR_ALF_MASK)
			result = LPI2C_ARB_LOST_ERR;
		else if (status & LPI2C_MSR_NDF_MASK)
			result = LPI2C_NAK_ERR;
		else if (status & LPI2C_MSR_FEF_MASK)
			result = LPI2C_FIFO_ERR;

		/* clear status flags */
		writel(0x7f00, &regs->msr);
		/* reset fifos */
		val = readl(&regs->mcr);
		val |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
		writel(val, &regs->mcr);
	}

	return result;
}

static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
{
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 txcount = 0;
	ulong start_time = get_timer(0);

	do {
		txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
		txcount = LPI2C_FIFO_SIZE - txcount;
		result = imx_lpci2c_check_clear_error(regs);
		if (result) {
			debug("i2c: wait for tx ready: result 0x%x\n", result);
			return result;
		}
		if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
			debug("i2c: wait for tx ready: timeout\n");
			return -1;
		}
	} while (!txcount);

	return result;
}

static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	lpi2c_status_t result = LPI2C_SUCESS;

	/* empty tx */
	if (!len)
		return result;

	while (len--) {
		result = bus_i2c_wait_for_tx_ready(regs);
		if (result) {
			debug("i2c: send wait for tx ready: %d\n", result);
			return result;
		}
		writel(*txbuf++, &regs->mtdr);
	}

	return result;
}

static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len)
{
	struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	unsigned int chunk_len, rx_remain, timeout;
	lpi2c_status_t result = LPI2C_SUCESS;
	u32 val;
	ulong start_time = get_timer(0);

	/* empty read */
	if (!len)
		return result;

	/*
	 * Extend the timeout for a bulk read if needed.
	 * The calculated timeout is the result of multiplying the
	 * transfer length with 8 bit + ACK + one clock of extra time,
	 * considering the I2C bus frequency.
	 */
	timeout = max(len * 10 * 1000 / i2c->speed_hz, LPI2C_TIMEOUT_MS);

	rx_remain = len;
	while (rx_remain > 0) {
		chunk_len = clamp(rx_remain, LPI2C_CHUNK_LEN_MIN, LPI2C_CHUNK_DATA) - 1;

		result = bus_i2c_wait_for_tx_ready(regs);
		if (result) {
			debug("i2c: receive wait for tx ready: %d\n", result);
			return result;
		}

		/* clear all status flags */
		writel(0x7f00, &regs->msr);
		/* send receive command */
		writel(LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(chunk_len), &regs->mtdr);
		rx_remain = rx_remain - (chunk_len & 0xff) - 1;

		while (len--) {
			do {
				result = imx_lpci2c_check_clear_error(regs);
				if (result) {
					debug("i2c: receive check clear error: %d\n",
					      result);
					return result;
				}
				if (get_timer(start_time) > timeout) {
					debug("i2c: receive mrdr: timeout\n");
					return -1;
				}
				val = readl(&regs->mrdr);
			} while (val & LPI2C_MRDR_RXEMPTY_MASK);
			*rxbuf++ = LPI2C_MRDR_DATA(val);

			/* send next receive command before controller NACKs last byte */
			if ((len - rx_remain) < 2 && rx_remain > 0)
				break;
		}
	}

	return result;
}

static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
{
	lpi2c_status_t result;
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	u32 val;

	result = imx_lpci2c_check_busy_bus(regs);
	if (result) {
		debug("i2c: start check busy bus: 0x%x\n", result);

		/* Try to init the lpi2c then check the bus busy again */
		bus_i2c_init(bus);
		result = imx_lpci2c_check_busy_bus(regs);
		if (result) {
			printf("i2c: Error check busy bus: 0x%x\n", result);
			return result;
		}
	}
	/* clear all status flags */
	writel(0x7f00, &regs->msr);
	/* turn off auto-stop condition */
	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
	writel(val, &regs->mcfgr1);
	/* wait tx fifo ready */
	result = bus_i2c_wait_for_tx_ready(regs);
	if (result) {
		debug("i2c: start wait for tx ready: 0x%x\n", result);
		return result;
	}
	/* issue start command */
	val = LPI2C_MTDR_CMD(0x4) | (addr << 0x1) | dir;
	writel(val, &regs->mtdr);

	return result;
}

static int bus_i2c_stop(struct udevice *bus)
{
	lpi2c_status_t result;
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	u32 status;
	ulong start_time;

	result = bus_i2c_wait_for_tx_ready(regs);
	if (result) {
		debug("i2c: stop wait for tx ready: 0x%x\n", result);
		return result;
	}

	/* send stop command */
	writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);

	start_time = get_timer(0);
	while (1) {
		status = readl(&regs->msr);
		result = imx_lpci2c_check_clear_error(regs);
		/* stop detect flag */
		if (status & LPI2C_MSR_SDF_MASK) {
			/* clear stop flag */
			status &= LPI2C_MSR_SDF_MASK;
			writel(status, &regs->msr);
			break;
		}

		if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
			debug("stop timeout\n");
			return -ETIMEDOUT;
		}
	}

	return result;
}

static int bus_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
{
	lpi2c_status_t result;

	result = bus_i2c_start(bus, chip, 1);
	if (result)
		return result;
	result = bus_i2c_receive(bus, buf, len);
	if (result)
		return result;

	return result;
}

static int bus_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
{
	lpi2c_status_t result;

	result = bus_i2c_start(bus, chip, 0);
	if (result)
		return result;
	result = bus_i2c_send(bus, buf, len);
	if (result)
		return result;

	return result;
}

u32 __weak imx_get_i2cclk(u32 i2c_num)
{
	return 0;
}

static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	u32 val;
	u32 preescale = 0, best_pre = 0, clkhi = 0;
	u32 best_clkhi = 0, abs_error = 0, rate;
	u32 error = 0xffffffff;
	u32 clock_rate;
	bool mode;
	int i;

	if (CONFIG_IS_ENABLED(CLK)) {
		clock_rate = clk_get_rate(&i2c_bus->per_clk);
		if (clock_rate <= 0) {
			dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
			return clock_rate;
		}
	} else {
		clock_rate = imx_get_i2cclk(dev_seq(bus));
		if (!clock_rate)
			return -EPERM;
	}

	mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
	/* disable master mode */
	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	writel(val | LPI2C_MCR_MEN(0), &regs->mcr);

	for (preescale = 1; (preescale <= 128) &&
		(error != 0); preescale = 2 * preescale) {
		for (clkhi = 1; clkhi < 32; clkhi++) {
			if (clkhi == 1)
				rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
			else
				rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));

			abs_error = speed > rate ? speed - rate : rate - speed;

			if (abs_error < error) {
				best_pre = preescale;
				best_clkhi = clkhi;
				error = abs_error;
				if (abs_error == 0)
					break;
			}
		}
	}

	/* Standard, fast, fast mode plus and ultra-fast transfers. */
	val = LPI2C_MCCR0_CLKHI(best_clkhi);
	if (best_clkhi < 2)
		val |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
	else
		val |= LPI2C_MCCR0_CLKLO(2 * best_clkhi) | LPI2C_MCCR0_SETHOLD(best_clkhi) |
			LPI2C_MCCR0_DATAVD(best_clkhi / 2);
	writel(val, &regs->mccr0);

	for (i = 0; i < 8; i++) {
		if (best_pre == (1 << i)) {
			best_pre = i;
			break;
		}
	}

	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
	writel(val | LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);

	if (mode) {
		val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
		writel(val | LPI2C_MCR_MEN(1), &regs->mcr);
	}

	return 0;
}

static int bus_i2c_init(struct udevice *bus)
{
	u32 val;
	int ret;

	struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
	int speed = i2c->speed_hz;

	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base);
	/* reset peripheral */
	writel(LPI2C_MCR_RST_MASK, &regs->mcr);
	writel(0x0, &regs->mcr);
	/* Disable Dozen mode */
	writel(LPI2C_MCR_DBGEN(0) | LPI2C_MCR_DOZEN(1), &regs->mcr);
	/* host request disable, active high, external pin */
	val = readl(&regs->mcfgr0);
	val &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK |
				LPI2C_MCFGR0_HRSEL_MASK));
	val |= LPI2C_MCFGR0_HRPOL(0x1);
	writel(val, &regs->mcfgr0);
	/* pincfg and ignore ack */
	val = readl(&regs->mcfgr1);
	val &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
	val |= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
	val |= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
	writel(val, &regs->mcfgr1);

	ret = bus_i2c_set_bus_speed(bus, speed);

	/* enable lpi2c in master mode */
	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	writel(val | LPI2C_MCR_MEN(1), &regs->mcr);

	debug("i2c : controller bus %d, speed %d:\n", dev_seq(bus), speed);

	return ret;
}

static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
				u32 chip_flags)
{
	lpi2c_status_t result;

	result = bus_i2c_start(bus, chip, 0);
	if (result) {
		bus_i2c_stop(bus);
		bus_i2c_init(bus);
		return result;
	}

	result = bus_i2c_stop(bus);
	if (result)
		bus_i2c_init(bus);

	return result;
}

static int imx_lpi2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
	int ret = 0, ret_stop;

	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD)
			ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
		else {
			ret = bus_i2c_write(bus, msg->addr, msg->buf,
					    msg->len);
			if (ret)
				break;
		}
	}

	if (ret)
		debug("i2c_write: error sending\n");

	ret_stop = bus_i2c_stop(bus);
	if (ret_stop)
		debug("i2c_xfer: stop bus error\n");

	ret |= ret_stop;

	return ret;
}

static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	return bus_i2c_set_bus_speed(bus, speed);
}

__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
{
	return 0;
}

static int imx_lpi2c_probe(struct udevice *bus)
{
	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	fdt_addr_t addr;
	int ret;

	i2c_bus->driver_data = dev_get_driver_data(bus);

	addr = dev_read_addr(bus);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	i2c_bus->base = addr;
	i2c_bus->index = dev_seq(bus);
	i2c_bus->bus = bus;

	/* power up i2c resource */
	ret = init_i2c_power(dev_seq(bus));
	if (ret) {
		debug("init_i2c_power err = %d\n", ret);
		return ret;
	}

	if (CONFIG_IS_ENABLED(CLK)) {
		ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
		if (ret) {
			dev_err(bus, "Failed to get per clk\n");
			return ret;
		}
		ret = clk_enable(&i2c_bus->per_clk);
		if (ret) {
			dev_err(bus, "Failed to enable per clk\n");
			return ret;
		}

		ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
		if (ret) {
			dev_err(bus, "Failed to get ipg clk\n");
			return ret;
		}
		ret = clk_enable(&i2c_bus->ipg_clk);
		if (ret) {
			dev_err(bus, "Failed to enable ipg clk\n");
			return ret;
		}
	} else {
		/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
		ret = enable_i2c_clk(1, dev_seq(bus));
		if (ret < 0)
			return ret;
	}

	ret = bus_i2c_init(bus);
	if (ret < 0)
		return ret;

	debug("i2c : controller bus %d at 0x%lx , speed %d: ",
	      dev_seq(bus), i2c_bus->base,
	      i2c_bus->speed);

	return 0;
}

static const struct dm_i2c_ops imx_lpi2c_ops = {
	.xfer		= imx_lpi2c_xfer,
	.probe_chip	= imx_lpi2c_probe_chip,
	.set_bus_speed	= imx_lpi2c_set_bus_speed,
};

static const struct udevice_id imx_lpi2c_ids[] = {
	{ .compatible = "fsl,imx7ulp-lpi2c", },
	{ .compatible = "fsl,imx8qm-lpi2c", },
	{}
};

U_BOOT_DRIVER(imx_lpi2c) = {
	.name = "imx_lpi2c",
	.id = UCLASS_I2C,
	.of_match = imx_lpi2c_ids,
	.probe = imx_lpi2c_probe,
	.priv_auto	= sizeof(struct imx_lpi2c_bus),
	.ops = &imx_lpi2c_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
7ee3f149 PF	2	/*
7ee3f149 PF	3	* Copyright 2016 Freescale Semiconductors, Inc.
7ee3f149 PF	4	*/
7ee3f149 PF	5
7ee3f149	6	#include <errno.h>
f7ae49fc	7	#include <log.h>
7ee3f149 PF	8	#include <asm/io.h>
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/imx-regs.h>
9b2ebcc0	11	#include <imx_lpi2c.h>
7ee3f149 PF	12	#include <asm/arch/sys_proto.h>
	13	#include <dm.h>
	14	#include <fdtdec.h>
	15	#include <i2c.h>
336d4615	16	#include <dm/device_compat.h>
7ee3f149	17
7ee3f149	18	#define LPI2C_FIFO_SIZE 4
a32effd2	19	#define LPI2C_NACK_TOUT_MS 1
7ee3f149 PF	20	#define LPI2C_TIMEOUT_MS 100
7ee3f149 PF	21
ec07bcc8 FR	22	#define LPI2C_CHUNK_DATA 256U
	23	#define LPI2C_CHUNK_LEN_MIN 1U
	24
34c6731a	25	static int bus_i2c_init(struct udevice *bus);
971490c8	26
7ee3f149 PF	27	/* Weak linked function for overridden by some SoC power function */
	28	int __weak init_i2c_power(unsigned i2c_num)
	29	{
	30	return 0;
	31	}
	32
a821c4af	33	static int imx_lpci2c_check_busy_bus(const struct imx_lpi2c_reg *regs)
7ee3f149	34	{
7ee3f149 PF	35	lpi2c_status_t result = LPI2C_SUCESS;
	36	u32 status;
	37
	38	status = readl(&regs->msr);
	39
	40	if ((status & LPI2C_MSR_BBF_MASK) && !(status & LPI2C_MSR_MBF_MASK))
	41	result = LPI2C_BUSY;
	42
	43	return result;
	44	}
	45
a821c4af	46	static int imx_lpci2c_check_clear_error(struct imx_lpi2c_reg *regs)
7ee3f149	47	{
7ee3f149 PF	48	lpi2c_status_t result = LPI2C_SUCESS;
	49	u32 val, status;
	50
	51	status = readl(&regs->msr);
	52	/* errors to check for */
	53	status &= LPI2C_MSR_NDF_MASK \| LPI2C_MSR_ALF_MASK \|
	54	LPI2C_MSR_FEF_MASK \| LPI2C_MSR_PLTF_MASK;
	55
	56	if (status) {
	57	if (status & LPI2C_MSR_PLTF_MASK)
	58	result = LPI2C_PIN_LOW_TIMEOUT_ERR;
	59	else if (status & LPI2C_MSR_ALF_MASK)
	60	result = LPI2C_ARB_LOST_ERR;
	61	else if (status & LPI2C_MSR_NDF_MASK)
	62	result = LPI2C_NAK_ERR;
	63	else if (status & LPI2C_MSR_FEF_MASK)
	64	result = LPI2C_FIFO_ERR;
	65
	66	/* clear status flags */
	67	writel(0x7f00, &regs->msr);
	68	/* reset fifos */
	69	val = readl(&regs->mcr);
	70	val \|= LPI2C_MCR_RRF_MASK \| LPI2C_MCR_RTF_MASK;
	71	writel(val, &regs->mcr);
	72	}
	73
	74	return result;
	75	}
	76
a821c4af	77	static int bus_i2c_wait_for_tx_ready(struct imx_lpi2c_reg *regs)
7ee3f149	78	{
7ee3f149 PF	79	lpi2c_status_t result = LPI2C_SUCESS;
	80	u32 txcount = 0;
	81	ulong start_time = get_timer(0);
	82
	83	do {
	84	txcount = LPI2C_MFSR_TXCOUNT(readl(&regs->mfsr));
	85	txcount = LPI2C_FIFO_SIZE - txcount;
a821c4af	86	result = imx_lpci2c_check_clear_error(regs);
7ee3f149 PF	87	if (result) {
	88	debug("i2c: wait for tx ready: result 0x%x\n", result);
	89	return result;
	90	}
	91	if (get_timer(start_time) > LPI2C_TIMEOUT_MS) {
	92	debug("i2c: wait for tx ready: timeout\n");
	93	return -1;
	94	}
	95	} while (!txcount);
	96
	97	return result;
	98	}
	99
971490c8	100	static int bus_i2c_send(struct udevice bus, u8 txbuf, int len)
7ee3f149	101	{
35d3982e YL	102	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	103	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	104	lpi2c_status_t result = LPI2C_SUCESS;
	105
	106	/* empty tx */
	107	if (!len)
	108	return result;
	109
	110	while (len--) {
a821c4af	111	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149	112	if (result) {
7677c0de	113	debug("i2c: send wait for tx ready: %d\n", result);
7ee3f149 PF	114	return result;
	115	}
	116	writel(*txbuf++, &regs->mtdr);
	117	}
	118
	119	return result;
	120	}
	121
971490c8	122	static int bus_i2c_receive(struct udevice bus, u8 rxbuf, int len)
7ee3f149	123	{
ec07bcc8	124	struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
35d3982e YL	125	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	126	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
ec07bcc8	127	unsigned int chunk_len, rx_remain, timeout;
7ee3f149 PF	128	lpi2c_status_t result = LPI2C_SUCESS;
	129	u32 val;
	130	ulong start_time = get_timer(0);
	131
	132	/* empty read */
	133	if (!len)
	134	return result;
	135
ec07bcc8 FR	136	/*
	137	* Extend the timeout for a bulk read if needed.
	138	* The calculated timeout is the result of multiplying the
	139	* transfer length with 8 bit + ACK + one clock of extra time,
	140	* considering the I2C bus frequency.
	141	*/
	142	timeout = max(len * 10 * 1000 / i2c->speed_hz, LPI2C_TIMEOUT_MS);
7ee3f149	143
ec07bcc8 FR	144	rx_remain = len;
	145	while (rx_remain > 0) {
	146	chunk_len = clamp(rx_remain, LPI2C_CHUNK_LEN_MIN, LPI2C_CHUNK_DATA) - 1;
7ee3f149	147
ec07bcc8 FR	148	result = bus_i2c_wait_for_tx_ready(regs);
	149	if (result) {
	150	debug("i2c: receive wait for tx ready: %d\n", result);
	151	return result;
	152	}
	153
	154	/* clear all status flags */
	155	writel(0x7f00, &regs->msr);
	156	/* send receive command */
	157	writel(LPI2C_MTDR_CMD(0x1) \| LPI2C_MTDR_DATA(chunk_len), &regs->mtdr);
	158	rx_remain = rx_remain - (chunk_len & 0xff) - 1;
	159
	160	while (len--) {
	161	do {
	162	result = imx_lpci2c_check_clear_error(regs);
	163	if (result) {
	164	debug("i2c: receive check clear error: %d\n",
	165	result);
	166	return result;
	167	}
	168	if (get_timer(start_time) > timeout) {
	169	debug("i2c: receive mrdr: timeout\n");
	170	return -1;
	171	}
	172	val = readl(&regs->mrdr);
	173	} while (val & LPI2C_MRDR_RXEMPTY_MASK);
	174	*rxbuf++ = LPI2C_MRDR_DATA(val);
	175
	176	/* send next receive command before controller NACKs last byte */
	177	if ((len - rx_remain) < 2 && rx_remain > 0)
	178	break;
	179	}
7ee3f149 PF	180	}
	181
	182	return result;
	183	}
	184
971490c8	185	static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir)
7ee3f149	186	{
d45c2f39	187	lpi2c_status_t result;
35d3982e YL	188	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	189	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	190	u32 val;
7ee3f149 PF	191
a821c4af	192	result = imx_lpci2c_check_busy_bus(regs);
7ee3f149 PF	193	if (result) {
7ee3f149 PF	194	debug("i2c: start check busy bus: 0x%x\n", result);
971490c8 YL	195
971490c8 YL	196	/* Try to init the lpi2c then check the bus busy again */
34c6731a	197	bus_i2c_init(bus);
971490c8 YL	198	result = imx_lpci2c_check_busy_bus(regs);
	199	if (result) {
	200	printf("i2c: Error check busy bus: 0x%x\n", result);
	201	return result;
	202	}
7ee3f149 PF	203	}
	204	/* clear all status flags */
	205	writel(0x7f00, &regs->msr);
	206	/* turn off auto-stop condition */
	207	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_AUTOSTOP_MASK;
	208	writel(val, &regs->mcfgr1);
	209	/* wait tx fifo ready */
a821c4af	210	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149 PF	211	if (result) {
	212	debug("i2c: start wait for tx ready: 0x%x\n", result);
	213	return result;
	214	}
	215	/* issue start command */
	216	val = LPI2C_MTDR_CMD(0x4) \| (addr << 0x1) \| dir;
	217	writel(val, &regs->mtdr);
	218
	219	return result;
	220	}
a821c4af	221
971490c8	222	static int bus_i2c_stop(struct udevice *bus)
7ee3f149	223	{
d45c2f39	224	lpi2c_status_t result;
35d3982e YL	225	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	226	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149	227	u32 status;
a32effd2	228	ulong start_time;
7ee3f149	229
a821c4af	230	result = bus_i2c_wait_for_tx_ready(regs);
7ee3f149 PF	231	if (result) {
	232	debug("i2c: stop wait for tx ready: 0x%x\n", result);
	233	return result;
	234	}
	235
	236	/* send stop command */
	237	writel(LPI2C_MTDR_CMD(0x2), &regs->mtdr);
	238
a32effd2 GP	239	start_time = get_timer(0);
a32effd2 GP	240	while (1) {
7ee3f149	241	status = readl(&regs->msr);
a821c4af	242	result = imx_lpci2c_check_clear_error(regs);
7ee3f149 PF	243	/* stop detect flag */
	244	if (status & LPI2C_MSR_SDF_MASK) {
	245	/* clear stop flag */
	246	status &= LPI2C_MSR_SDF_MASK;
	247	writel(status, &regs->msr);
	248	break;
	249	}
a32effd2 GP	250
	251	if (get_timer(start_time) > LPI2C_NACK_TOUT_MS) {
	252	debug("stop timeout\n");
	253	return -ETIMEDOUT;
	254	}
7ee3f149 PF	255	}
	256
	257	return result;
	258	}
	259
971490c8	260	static int bus_i2c_read(struct udevice bus, u32 chip, u8 buf, int len)
7ee3f149	261	{
d45c2f39	262	lpi2c_status_t result;
7ee3f149	263
971490c8	264	result = bus_i2c_start(bus, chip, 1);
7ee3f149 PF	265	if (result)
7ee3f149 PF	266	return result;
971490c8	267	result = bus_i2c_receive(bus, buf, len);
7ee3f149 PF	268	if (result)
	269	return result;
	270
	271	return result;
	272	}
	273
971490c8	274	static int bus_i2c_write(struct udevice bus, u32 chip, u8 buf, int len)
7ee3f149	275	{
d45c2f39	276	lpi2c_status_t result;
7ee3f149	277
971490c8	278	result = bus_i2c_start(bus, chip, 0);
7ee3f149 PF	279	if (result)
7ee3f149 PF	280	return result;
971490c8	281	result = bus_i2c_send(bus, buf, len);
7ee3f149 PF	282	if (result)
	283	return result;
	284
	285	return result;
	286	}
	287
3d7690ae PF	288	u32 __weak imx_get_i2cclk(u32 i2c_num)
	289	{
	290	return 0;
	291	}
	292
7ee3f149 PF	293	static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
7ee3f149 PF	294	{
3d7690ae	295	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e	296	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	297	u32 val;
	298	u32 preescale = 0, best_pre = 0, clkhi = 0;
	299	u32 best_clkhi = 0, abs_error = 0, rate;
	300	u32 error = 0xffffffff;
	301	u32 clock_rate;
	302	bool mode;
	303	int i;
	304
b4004c29	305	if (CONFIG_IS_ENABLED(CLK)) {
3d7690ae PF	306	clock_rate = clk_get_rate(&i2c_bus->per_clk);
	307	if (clock_rate <= 0) {
	308	dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
	309	return clock_rate;
	310	}
	311	} else {
8b85dfc6	312	clock_rate = imx_get_i2cclk(dev_seq(bus));
3d7690ae PF	313	if (!clock_rate)
	314	return -EPERM;
	315	}
7ee3f149 PF	316
	317	mode = (readl(&regs->mcr) & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
	318	/* disable master mode */
	319	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	320	writel(val \| LPI2C_MCR_MEN(0), &regs->mcr);
	321
	322	for (preescale = 1; (preescale <= 128) &&
	323	(error != 0); preescale = 2 * preescale) {
	324	for (clkhi = 1; clkhi < 32; clkhi++) {
	325	if (clkhi == 1)
	326	rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
	327	else
	328	rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
	329
	330	abs_error = speed > rate ? speed - rate : rate - speed;
	331
	332	if (abs_error < error) {
	333	best_pre = preescale;
	334	best_clkhi = clkhi;
	335	error = abs_error;
	336	if (abs_error == 0)
	337	break;
	338	}
	339	}
	340	}
	341
	342	/* Standard, fast, fast mode plus and ultra-fast transfers. */
	343	val = LPI2C_MCCR0_CLKHI(best_clkhi);
	344	if (best_clkhi < 2)
	345	val \|= LPI2C_MCCR0_CLKLO(3) \| LPI2C_MCCR0_SETHOLD(2) \| LPI2C_MCCR0_DATAVD(1);
	346	else
	347	val \|= LPI2C_MCCR0_CLKLO(2 * best_clkhi) \| LPI2C_MCCR0_SETHOLD(best_clkhi) \|
	348	LPI2C_MCCR0_DATAVD(best_clkhi / 2);
	349	writel(val, &regs->mccr0);
	350
	351	for (i = 0; i < 8; i++) {
	352	if (best_pre == (1 << i)) {
	353	best_pre = i;
	354	break;
	355	}
	356	}
	357
	358	val = readl(&regs->mcfgr1) & ~LPI2C_MCFGR1_PRESCALE_MASK;
	359	writel(val \| LPI2C_MCFGR1_PRESCALE(best_pre), &regs->mcfgr1);
	360
	361	if (mode) {
	362	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	363	writel(val \| LPI2C_MCR_MEN(1), &regs->mcr);
	364	}
	365
	366	return 0;
	367	}
	368
34c6731a	369	static int bus_i2c_init(struct udevice *bus)
7ee3f149	370	{
7ee3f149 PF	371	u32 val;
	372	int ret;
	373
34c6731a FR	374	struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
	375	int speed = i2c->speed_hz;
	376
35d3982e YL	377	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
35d3982e YL	378	struct imx_lpi2c_reg regs = (struct imx_lpi2c_reg )(i2c_bus->base);
7ee3f149 PF	379	/* reset peripheral */
	380	writel(LPI2C_MCR_RST_MASK, &regs->mcr);
	381	writel(0x0, &regs->mcr);
	382	/* Disable Dozen mode */
	383	writel(LPI2C_MCR_DBGEN(0) \| LPI2C_MCR_DOZEN(1), &regs->mcr);
	384	/* host request disable, active high, external pin */
	385	val = readl(&regs->mcfgr0);
	386	val &= (~(LPI2C_MCFGR0_HREN_MASK \| LPI2C_MCFGR0_HRPOL_MASK \|
	387	LPI2C_MCFGR0_HRSEL_MASK));
	388	val \|= LPI2C_MCFGR0_HRPOL(0x1);
	389	writel(val, &regs->mcfgr0);
	390	/* pincfg and ignore ack */
	391	val = readl(&regs->mcfgr1);
	392	val &= ~(LPI2C_MCFGR1_PINCFG_MASK \| LPI2C_MCFGR1_IGNACK_MASK);
	393	val \|= LPI2C_MCFGR1_PINCFG(0x0); /* 2 pin open drain */
	394	val \|= LPI2C_MCFGR1_IGNACK(0x0); /* ignore nack */
	395	writel(val, &regs->mcfgr1);
	396
	397	ret = bus_i2c_set_bus_speed(bus, speed);
	398
	399	/* enable lpi2c in master mode */
	400	val = readl(&regs->mcr) & ~LPI2C_MCR_MEN_MASK;
	401	writel(val \| LPI2C_MCR_MEN(1), &regs->mcr);
	402
8b85dfc6	403	debug("i2c : controller bus %d, speed %d:\n", dev_seq(bus), speed);
7ee3f149 PF	404
	405	return ret;
	406	}
	407
	408	static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip,
	409	u32 chip_flags)
	410	{
d45c2f39	411	lpi2c_status_t result;
7ee3f149	412
971490c8	413	result = bus_i2c_start(bus, chip, 0);
7ee3f149	414	if (result) {
971490c8	415	bus_i2c_stop(bus);
34c6731a	416	bus_i2c_init(bus);
7ee3f149 PF	417	return result;
	418	}
	419
971490c8	420	result = bus_i2c_stop(bus);
a32effd2	421	if (result)
34c6731a	422	bus_i2c_init(bus);
7ee3f149 PF	423
	424	return result;
	425	}
	426
	427	static int imx_lpi2c_xfer(struct udevice bus, struct i2c_msg msg, int nmsgs)
	428	{
d144f61a	429	int ret = 0, ret_stop;
7ee3f149 PF	430
	431	for (; nmsgs > 0; nmsgs--, msg++) {
	432	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	433	if (msg->flags & I2C_M_RD)
971490c8	434	ret = bus_i2c_read(bus, msg->addr, msg->buf, msg->len);
7ee3f149	435	else {
971490c8	436	ret = bus_i2c_write(bus, msg->addr, msg->buf,
7ee3f149 PF	437	msg->len);
	438	if (ret)
	439	break;
	440	}
	441	}
	442
	443	if (ret)
	444	debug("i2c_write: error sending\n");
	445
971490c8	446	ret_stop = bus_i2c_stop(bus);
d144f61a YL	447	if (ret_stop)
	448	debug("i2c_xfer: stop bus error\n");
	449
	450	ret \|= ret_stop;
	451
7ee3f149 PF	452	return ret;
	453	}
	454
	455	static int imx_lpi2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	456	{
	457	return bus_i2c_set_bus_speed(bus, speed);
	458	}
	459
3d7690ae PF	460	__weak int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
	461	{
	462	return 0;
	463	}
	464
7ee3f149 PF	465	static int imx_lpi2c_probe(struct udevice *bus)
	466	{
	467	struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus);
	468	fdt_addr_t addr;
	469	int ret;
	470
	471	i2c_bus->driver_data = dev_get_driver_data(bus);
	472
2548493a	473	addr = dev_read_addr(bus);
7ee3f149	474	if (addr == FDT_ADDR_T_NONE)
7c84319a	475	return -EINVAL;
7ee3f149 PF	476
7ee3f149 PF	477	i2c_bus->base = addr;
8b85dfc6	478	i2c_bus->index = dev_seq(bus);
7ee3f149 PF	479	i2c_bus->bus = bus;
	480
	481	/* power up i2c resource */
8b85dfc6	482	ret = init_i2c_power(dev_seq(bus));
7ee3f149 PF	483	if (ret) {
	484	debug("init_i2c_power err = %d\n", ret);
	485	return ret;
	486	}
	487
b4004c29	488	if (CONFIG_IS_ENABLED(CLK)) {
3d7690ae PF	489	ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
	490	if (ret) {
	491	dev_err(bus, "Failed to get per clk\n");
	492	return ret;
	493	}
	494	ret = clk_enable(&i2c_bus->per_clk);
	495	if (ret) {
	496	dev_err(bus, "Failed to enable per clk\n");
	497	return ret;
	498	}
d02be21d PF	499
	500	ret = clk_get_by_name(bus, "ipg", &i2c_bus->ipg_clk);
	501	if (ret) {
	502	dev_err(bus, "Failed to get ipg clk\n");
	503	return ret;
	504	}
	505	ret = clk_enable(&i2c_bus->ipg_clk);
	506	if (ret) {
	507	dev_err(bus, "Failed to enable ipg clk\n");
	508	return ret;
	509	}
3d7690ae PF	510	} else {
3d7690ae PF	511	/* To i.MX7ULP, only i2c4-7 can be handled by A7 core */
8b85dfc6	512	ret = enable_i2c_clk(1, dev_seq(bus));
3d7690ae PF	513	if (ret < 0)
	514	return ret;
	515	}
7ee3f149	516
34c6731a	517	ret = bus_i2c_init(bus);
7ee3f149 PF	518	if (ret < 0)
	519	return ret;
	520
7677c0de	521	debug("i2c : controller bus %d at 0x%lx , speed %d: ",
8b85dfc6	522	dev_seq(bus), i2c_bus->base,
7ee3f149 PF	523	i2c_bus->speed);
	524
	525	return 0;
	526	}
	527
	528	static const struct dm_i2c_ops imx_lpi2c_ops = {
	529	.xfer = imx_lpi2c_xfer,
	530	.probe_chip = imx_lpi2c_probe_chip,
	531	.set_bus_speed = imx_lpi2c_set_bus_speed,
	532	};
	533
	534	static const struct udevice_id imx_lpi2c_ids[] = {
	535	{ .compatible = "fsl,imx7ulp-lpi2c", },
9b2ebcc0	536	{ .compatible = "fsl,imx8qm-lpi2c", },
7ee3f149 PF	537	{}
	538	};
	539
	540	U_BOOT_DRIVER(imx_lpi2c) = {
	541	.name = "imx_lpi2c",
	542	.id = UCLASS_I2C,
	543	.of_match = imx_lpi2c_ids,
	544	.probe = imx_lpi2c_probe,
41575d8e	545	.priv_auto = sizeof(struct imx_lpi2c_bus),
7ee3f149 PF	546	.ops = &imx_lpi2c_ops,
7ee3f149 PF	547	};