[J-u-boot.git] / drivers / spi / omap3_spi.h

/*
 * Register definitions for the OMAP3 McSPI Controller
 *
 * Copyright (C) 2010 Dirk Behme <[email protected]>
 *
 * Parts taken from linux/drivers/spi/omap2_mcspi.c
 * Copyright (C) 2005, 2006 Nokia Corporation
 *
 * Modified by Ruslan Araslanov <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _OMAP3_SPI_H_
#define _OMAP3_SPI_H_

#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
#define OMAP3_MCSPI1_BASE	0x48030100
#define OMAP3_MCSPI2_BASE	0x481A0100
#else
#define OMAP3_MCSPI1_BASE	0x48098000
#define OMAP3_MCSPI2_BASE	0x4809A000
#define OMAP3_MCSPI3_BASE	0x480B8000
#define OMAP3_MCSPI4_BASE	0x480BA000
#endif

#define OMAP3_MCSPI_MAX_FREQ	48000000

/* OMAP3 McSPI registers */
struct mcspi_channel {
	unsigned int chconf;		/* 0x2C, 0x40, 0x54, 0x68 */
	unsigned int chstat;		/* 0x30, 0x44, 0x58, 0x6C */
	unsigned int chctrl;		/* 0x34, 0x48, 0x5C, 0x70 */
	unsigned int tx;		/* 0x38, 0x4C, 0x60, 0x74 */
	unsigned int rx;		/* 0x3C, 0x50, 0x64, 0x78 */
};

struct mcspi {
	unsigned char res1[0x10];
	unsigned int sysconfig;		/* 0x10 */
	unsigned int sysstatus;		/* 0x14 */
	unsigned int irqstatus;		/* 0x18 */
	unsigned int irqenable;		/* 0x1C */
	unsigned int wakeupenable;	/* 0x20 */
	unsigned int syst;		/* 0x24 */
	unsigned int modulctrl;		/* 0x28 */
	struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
					/* channel1: 0x40 - 0x50, bus 0 & 1 */
					/* channel2: 0x54 - 0x64, bus 0 & 1 */
					/* channel3: 0x68 - 0x78, bus 0 */
};

/* per-register bitmasks */
#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)

#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)

#define OMAP3_MCSPI_MODULCTRL_SINGLE	BIT(0)
#define OMAP3_MCSPI_MODULCTRL_MS	BIT(2)
#define OMAP3_MCSPI_MODULCTRL_STEST	BIT(3)

#define OMAP3_MCSPI_CHCONF_PHA		BIT(0)
#define OMAP3_MCSPI_CHCONF_POL		BIT(1)
#define OMAP3_MCSPI_CHCONF_CLKD_MASK	GENMASK(5, 2)
#define OMAP3_MCSPI_CHCONF_EPOL		BIT(6)
#define OMAP3_MCSPI_CHCONF_WL_MASK	GENMASK(11, 7)
#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY	BIT(12)
#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY	BIT(13)
#define OMAP3_MCSPI_CHCONF_TRM_MASK	GENMASK(13, 12)
#define OMAP3_MCSPI_CHCONF_DMAW		BIT(14)
#define OMAP3_MCSPI_CHCONF_DMAR		BIT(15)
#define OMAP3_MCSPI_CHCONF_DPE0		BIT(16)
#define OMAP3_MCSPI_CHCONF_DPE1		BIT(17)
#define OMAP3_MCSPI_CHCONF_IS		BIT(18)
#define OMAP3_MCSPI_CHCONF_TURBO	BIT(19)
#define OMAP3_MCSPI_CHCONF_FORCE	BIT(20)

#define OMAP3_MCSPI_CHSTAT_RXS		BIT(0)
#define OMAP3_MCSPI_CHSTAT_TXS		BIT(1)
#define OMAP3_MCSPI_CHSTAT_EOT		BIT(2)

#define OMAP3_MCSPI_CHCTRL_EN		BIT(0)
#define OMAP3_MCSPI_CHCTRL_DIS		(0 << 0)

#define OMAP3_MCSPI_WAKEUPENABLE_WKEN	BIT(0)

struct omap3_spi_slave {
	struct spi_slave slave;
	struct mcspi *regs;
	unsigned int freq;
	unsigned int mode;
};

static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
{
	return container_of(slave, struct omap3_spi_slave, slave);
}

int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp,
			void *rxp, unsigned long flags);
int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
		    unsigned long flags);
int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
		   unsigned long flags);

#endif /* _OMAP3_SPI_H_ */
Commit	Line	Data
53736baa DB	1	/*
	2	* Register definitions for the OMAP3 McSPI Controller
	3	*
	4	* Copyright (C) 2010 Dirk Behme <[email protected]>
	5	*
	6	* Parts taken from linux/drivers/spi/omap2_mcspi.c
	7	* Copyright (C) 2005, 2006 Nokia Corporation
	8	*
	9	* Modified by Ruslan Araslanov <[email protected]>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
53736baa DB	12	*/
	13
	14	#ifndef _OMAP3_SPI_H_
	15	#define _OMAP3_SPI_H_
	16
2ff97625	17	#if defined(CONFIG_AM33XX) \|\| defined(CONFIG_AM43XX)
4c0620bf TR	18	#define OMAP3_MCSPI1_BASE 0x48030100
	19	#define OMAP3_MCSPI2_BASE 0x481A0100
	20	#else
53736baa DB	21	#define OMAP3_MCSPI1_BASE 0x48098000
	22	#define OMAP3_MCSPI2_BASE 0x4809A000
	23	#define OMAP3_MCSPI3_BASE 0x480B8000
	24	#define OMAP3_MCSPI4_BASE 0x480BA000
4c0620bf	25	#endif
53736baa DB	26
	27	#define OMAP3_MCSPI_MAX_FREQ 48000000
	28
	29	/* OMAP3 McSPI registers */
	30	struct mcspi_channel {
	31	unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
	32	unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
	33	unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
	34	unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
	35	unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
	36	};
	37
	38	struct mcspi {
	39	unsigned char res1[0x10];
	40	unsigned int sysconfig; /* 0x10 */
	41	unsigned int sysstatus; /* 0x14 */
	42	unsigned int irqstatus; /* 0x18 */
	43	unsigned int irqenable; /* 0x1C */
	44	unsigned int wakeupenable; /* 0x20 */
	45	unsigned int syst; /* 0x24 */
	46	unsigned int modulctrl; /* 0x28 */
	47	struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
	48	/* channel1: 0x40 - 0x50, bus 0 & 1 */
	49	/* channel2: 0x54 - 0x64, bus 0 & 1 */
	50	/* channel3: 0x68 - 0x78, bus 0 */
	51	};
	52
	53	/* per-register bitmasks */
	54	#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
3e1b4dcf JT	55	#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
	56	#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
	57	#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
53736baa	58
3e1b4dcf	59	#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
53736baa	60
3e1b4dcf JT	61	#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
	62	#define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
	63	#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
53736baa	64
3e1b4dcf JT	65	#define OMAP3_MCSPI_CHCONF_PHA BIT(0)
3e1b4dcf JT	66	#define OMAP3_MCSPI_CHCONF_POL BIT(1)
0ebc0ec6	67	#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
3e1b4dcf	68	#define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
0ebc0ec6 JT	69	#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
	70	#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
	71	#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
	72	#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
3e1b4dcf JT	73	#define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
	74	#define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
	75	#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
	76	#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
	77	#define OMAP3_MCSPI_CHCONF_IS BIT(18)
	78	#define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
	79	#define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
	80
	81	#define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
	82	#define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
	83	#define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
	84
	85	#define OMAP3_MCSPI_CHCTRL_EN BIT(0)
cc1182be	86	#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
53736baa	87
3e1b4dcf	88	#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
53736baa DB	89
	90	struct omap3_spi_slave {
	91	struct spi_slave slave;
	92	struct mcspi *regs;
	93	unsigned int freq;
	94	unsigned int mode;
	95	};
	96
	97	static inline struct omap3_spi_slave to_omap3_spi(struct spi_slave slave)
	98	{
	99	return container_of(slave, struct omap3_spi_slave, slave);
	100	}
	101
5753d09b NK	102	int omap3_spi_txrx(struct spi_slave slave, unsigned int len, const void txp,
	103	void *rxp, unsigned long flags);
	104	int omap3_spi_write(struct spi_slave slave, unsigned int len, const void txp,
53736baa	105	unsigned long flags);
5753d09b	106	int omap3_spi_read(struct spi_slave slave, unsigned int len, void rxp,
53736baa DB	107	unsigned long flags);
	108
	109	#endif /* _OMAP3_SPI_H_ */