[J-u-boot.git] / include / configs / CANBT.h

/*
 * (C) Copyright 2001
 * Matthias Fuchs, esd gmbh germany, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CANBT		1	/* ...on a CANBT board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
	"bootm ffe00000 ffe80000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/

#define CONFIG_PHY_ADDR		0	/* PHY address			*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IRQ
#define CONFIG_CMD_EEPROM

#undef CONFIG_CMD_NET


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFE0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* Use FLASH for environment variables */

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/

#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (CAN/USB) initialization					*/
#define CFG_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (CAN Features) initialization					*/
#define CFG_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
#define CFG_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in RAM)
 */
#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
#define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
ab255f26 WD	1	/*
	2	* (C) Copyright 2001
	3	* Matthias Fuchs, esd gmbh germany, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405CR 1 /* This is a PPC405CR CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_CANBT 1 /* ...on a CANBT board */
ab255f26	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
ab255f26	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
ab255f26 WD	43
	44	#define CONFIG_BAUDRATE 115200
	45	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND \
	49	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
	50	"bootm ffe00000 ffe80000"
	51
	52	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	53	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	54
c837dcb1	55	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
ab255f26	56
c837dcb1	57	#define CONFIG_PHY_ADDR 0 /* PHY address */
ab255f26	58
ab255f26	59
11799434 JL	60	/*
	61	* BOOTP options
	62	*/
	63	#define CONFIG_BOOTP_BOOTFILESIZE
	64	#define CONFIG_BOOTP_BOOTPATH
	65	#define CONFIG_BOOTP_GATEWAY
	66	#define CONFIG_BOOTP_HOSTNAME
	67
	68
49cf7e8e JL	69	/*
	70	* Command line configuration.
	71	*/
	72	#include <config_cmd_default.h>
	73
	74	#define CONFIG_CMD_IRQ
5728be38	75	#define CONFIG_CMD_EEPROM
49cf7e8e JL	76
	77	#undef CONFIG_CMD_NET
	78
ab255f26 WD	79
	80	#undef CONFIG_WATCHDOG /* watchdog disabled */
	81
c837dcb1	82	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
ab255f26 WD	83
	84	/*
	85	* Miscellaneous configurable options
	86	*/
	87	#define CFG_LONGHELP /* undef to save memory */
	88	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
49cf7e8e	89	#if defined(CONFIG_CMD_KGDB)
c837dcb1	90	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
ab255f26	91	#else
c837dcb1	92	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
ab255f26 WD	93	#endif
	94	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	95	#define CFG_MAXARGS 16 /* max number of command args */
	96	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	97
c837dcb1	98	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
ab255f26 WD	99
	100	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	101	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	102
c837dcb1	103	#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
ab255f26 WD	104
ab255f26 WD	105	/* The following table includes the supported baudrates */
c837dcb1	106	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	107	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	108	57600, 115200, 230400, 460800, 921600 }
ab255f26 WD	109
	110	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	111	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	112
c837dcb1	113	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
ab255f26 WD	114
	115	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	116
	117	/*-----------------------------------------------------------------------
	118	* Start addresses for the final memory configuration
	119	* (Set up by the startup code)
	120	* Please note that CFG_SDRAM_BASE _must_ start at 0
	121	*/
	122	#define CFG_SDRAM_BASE 0x00000000
	123	#define CFG_FLASH_BASE 0xFFFE0000
	124	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	125	#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128 kB for Monitor */
	126	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	127
	128	/*
	129	* For booting Linux, the board info and command line data
	130	* have to be in the first 8 MB of memory, since this is
	131	* the maximum mapped by the Linux kernel during initialization.
	132	*/
	133	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	134	/*-----------------------------------------------------------------------
	135	* FLASH organization
	136	*/
	137	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	138	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	139
	140	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	141	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	142
c837dcb1 WD	143	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	144	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	145	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
ab255f26 WD	146	/*
	147	* The following defines are added for buggy IOP480 byte interface.
	148	* All other boards should use the standard values (CPCI405 etc.)
	149	*/
c837dcb1 WD	150	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	151	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	152	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
ab255f26	153
c837dcb1	154	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
ab255f26 WD	155
	156	#if 0 /* Use FLASH for environment variables */
	157
5a1aceb0	158	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	159	#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
0e8d1586 JCPV	160	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
ab255f26	161
0e8d1586	162	#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
ab255f26 WD	163
	164	#else /* Use EEPROM for environment variables */
	165
bb1f8b4f	166	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	167	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	168	#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
8bde7f77	169	/* total size of a CAT24WC08 is 1024 bytes */
ab255f26 WD	170	#endif
	171
	172	/*-----------------------------------------------------------------------
	173	* I2C EEPROM (CAT24WC08) for environment
	174	*/
c837dcb1	175	#define CONFIG_HARD_I2C /* I2C with hardware support */
ab255f26 WD	176	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	177	#define CFG_I2C_SLAVE 0x7F
	178
	179	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1	180	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
ab255f26 WD	181	/* mask of address bits that overflow into the "EEPROM chip address" */
	182	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	183
ab255f26 WD	184	/*
	185	* Init Memory Controller:
	186	*
	187	* BR0/1 and OR0/1 (FLASH)
	188	*/
	189
	190	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	191	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	192
	193	/*-----------------------------------------------------------------------
	194	* External Bus Controller (EBC) Setup
	195	*/
	196
c837dcb1 WD	197	/* Memory Bank 0 (Flash Bank 0) initialization */
	198	#define CFG_EBC_PB0AP 0x92015480
	199	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
ab255f26	200
c837dcb1 WD	201	/* Memory Bank 1 (CAN/USB) initialization */
	202	#define CFG_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
	203	#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
ab255f26	204
c837dcb1 WD	205	/* Memory Bank 2 (Misc-IO/LEDs) initialization */
	206	#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
	207	#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
ab255f26	208
c837dcb1 WD	209	/* Memory Bank 3 (CAN Features) initialization */
	210	#define CFG_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
	211	#define CFG_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
ab255f26 WD	212
	213	/*-----------------------------------------------------------------------
	214	* Definitions for initial stack pointer and data area (in RAM)
	215	*/
c837dcb1	216	#define CFG_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
ab255f26 WD	217	#define CFG_INIT_RAM_END 0x0f00 /* End of used area in RAM */
	218	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	219	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	220	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	221
	222
	223	/*
	224	* Internal Definitions
	225	*
	226	* Boot Flags
	227	*/
	228	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	229	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	230
	231	#endif /* __CONFIG_H */