[J-u-boot.git] / arch / mips / Kconfig

menu "MIPS architecture"
	depends on MIPS

config SYS_ARCH
	default "mips"

config SYS_CPU
	default "mips32" if CPU_MIPS32
	default "mips64" if CPU_MIPS64

choice
	prompt "Target select"
	optional

config TARGET_QEMU_MIPS
	bool "Support qemu-mips"
	select ROM_EXCEPTION_VECTORS
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2
	select SUPPORTS_LITTLE_ENDIAN

config TARGET_MALTA
	bool "Support malta"
	select DM
	select DM_SERIAL
	select DYNAMIC_IO_PORT_BASE
	select MIPS_CM
	select MIPS_INSERT_BOOT_CONFIG
	select MIPS_L1_CACHE_SHIFT_6
	select MIPS_L2_CACHE
	select OF_CONTROL
	select OF_ISA_BUS
	select ROM_EXCEPTION_VECTORS
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS32_R6
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2
	select SUPPORTS_CPU_MIPS64_R6
	select SUPPORTS_LITTLE_ENDIAN
	select SWAP_IO_SPACE
	imply CMD_DM

config TARGET_VCT
	bool "Support vct"
	select ROM_EXCEPTION_VECTORS
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD

config ARCH_ATH79
	bool "Support QCA/Atheros ath79"
	select DM
	select OF_CONTROL
	imply CMD_DM

config ARCH_BMIPS
	bool "Support BMIPS SoCs"
	select CLK
	select CPU
	select DM
	select OF_CONTROL
	select RAM
	select SYSRESET
	imply CMD_DM

config MACH_PIC32
	bool "Support Microchip PIC32"
	select DM
	select OF_CONTROL
	imply CMD_DM

config TARGET_BOSTON
	bool "Support Boston"
	select DM
	select DM_SERIAL
	select MIPS_CM
	select MIPS_L1_CACHE_SHIFT_6
	select MIPS_L2_CACHE
	select OF_BOARD_SETUP
	select OF_CONTROL
	select ROM_EXCEPTION_VECTORS
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS32_R6
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2
	select SUPPORTS_CPU_MIPS64_R6
	select SUPPORTS_LITTLE_ENDIAN
	imply CMD_DM

config TARGET_XILFPGA
	bool "Support Imagination Xilfpga"
	select DM
	select DM_ETH
	select DM_GPIO
	select DM_SERIAL
	select MIPS_L1_CACHE_SHIFT_4
	select OF_CONTROL
	select ROM_EXCEPTION_VECTORS
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_LITTLE_ENDIAN
	imply CMD_DM
	help
	  This supports IMGTEC MIPSfpga platform

endchoice

source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"

if MIPS

choice
	prompt "Endianness selection"
	help
	  Some MIPS boards can be configured for either little or big endian
	  byte order. These modes require different U-Boot images. In general there
	  is one preferred byteorder for a particular system but some systems are
	  just as commonly used in the one or the other endianness.

config SYS_BIG_ENDIAN
	bool "Big endian"
	depends on SUPPORTS_BIG_ENDIAN

config SYS_LITTLE_ENDIAN
	bool "Little endian"
	depends on SUPPORTS_LITTLE_ENDIAN

endchoice

choice
	prompt "CPU selection"
	default CPU_MIPS32_R2

config CPU_MIPS32_R1
	bool "MIPS32 Release 1"
	depends on SUPPORTS_CPU_MIPS32_R1
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 1 through 5 of the
	  MIPS32 architecture.

config CPU_MIPS32_R2
	bool "MIPS32 Release 2"
	depends on SUPPORTS_CPU_MIPS32_R2
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 2 through 5 of the
	  MIPS32 architecture.

config CPU_MIPS32_R6
	bool "MIPS32 Release 6"
	depends on SUPPORTS_CPU_MIPS32_R6
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 6 or later of the
	  MIPS32 architecture.

config CPU_MIPS64_R1
	bool "MIPS64 Release 1"
	depends on SUPPORTS_CPU_MIPS64_R1
	select 64BIT
	help
	  Choose this option to build a kernel for release 1 through 5 of the
	  MIPS64 architecture.

config CPU_MIPS64_R2
	bool "MIPS64 Release 2"
	depends on SUPPORTS_CPU_MIPS64_R2
	select 64BIT
	help
	  Choose this option to build a kernel for release 2 through 5 of the
	  MIPS64 architecture.

config CPU_MIPS64_R6
	bool "MIPS64 Release 6"
	depends on SUPPORTS_CPU_MIPS64_R6
	select 64BIT
	help
	  Choose this option to build a kernel for release 6 or later of the
	  MIPS64 architecture.

endchoice

menu "General setup"

config ROM_EXCEPTION_VECTORS
	bool "Build U-Boot image with exception vectors"
	help
	  Enable this to include exception vectors in the U-Boot image. This is
	  required if the U-Boot entry point is equal to the address of the
	  CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
	  U-Boot booted from parallel NOR flash).
	  Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
	  In that case the image size will be reduced by 0x500 bytes.

config MIPS_CM_BASE
	hex "MIPS CM GCR Base Address"
	depends on MIPS_CM
	default 0x16100000 if TARGET_BOSTON
	default 0x1fbf8000
	help
	  The physical base address at which to map the MIPS Coherence Manager
	  Global Configuration Registers (GCRs). This should be set such that
	  the GCRs occupy a region of the physical address space which is
	  otherwise unused, or at minimum that software doesn't need to access.

config MIPS_CACHE_INDEX_BASE
	hex "Index base address for cache initialisation"
	default 0x80000000 if CPU_MIPS32
	default 0xffffffff80000000 if CPU_MIPS64
	help
	  This is the base address for a memory block, which is used for
	  initialising the cache lines. This is also the base address of a memory
	  block which is used for loading and filling cache lines when
	  SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
	  Normally this is CKSEG0. If the MIPS system needs to move this block
	  to some SRAM or ScratchPad RAM, adapt this option accordingly.

endmenu

menu "OS boot interface"

config MIPS_BOOT_CMDLINE_LEGACY
	bool "Hand over legacy command line to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  command line to the kernel. All bootargs will be prepared as argc/argv
	  compatible list. The argument count (argc) is stored in register $a0.
	  The address of the argument list (argv) is stored in register $a1.

config MIPS_BOOT_ENV_LEGACY
	bool "Hand over legacy environment to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  environment to the kernel. Information like memory size, initrd
	  address and size will be prepared as zero-terminated key/value list.
	  The address of the environment is stored in register $a2.

config MIPS_BOOT_FDT
	bool "Hand over a flattened device tree to Linux kernel"
	default n
	help
	  Enable this option if you want U-Boot to hand over a flattened
	  device tree to the kernel. According to UHI register $a0 will be set
	  to -2 and the FDT address is stored in $a1.

endmenu

config SUPPORTS_BIG_ENDIAN
	bool

config SUPPORTS_LITTLE_ENDIAN
	bool

config SUPPORTS_CPU_MIPS32_R1
	bool

config SUPPORTS_CPU_MIPS32_R2
	bool

config SUPPORTS_CPU_MIPS32_R6
	bool

config SUPPORTS_CPU_MIPS64_R1
	bool

config SUPPORTS_CPU_MIPS64_R2
	bool

config SUPPORTS_CPU_MIPS64_R6
	bool

config CPU_MIPS32
	bool
	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6

config CPU_MIPS64
	bool
	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6

config MIPS_TUNE_4KC
	bool

config MIPS_TUNE_14KC
	bool

config MIPS_TUNE_24KC
	bool

config MIPS_TUNE_34KC
	bool

config MIPS_TUNE_74KC
	bool

config 32BIT
	bool

config 64BIT
	bool

config SWAP_IO_SPACE
	bool

config SYS_MIPS_CACHE_INIT_RAM_LOAD
	bool

config MIPS_INIT_STACK_IN_SRAM
	bool
	default n
	help
	  Select this if the initial stack frame could be setup in SRAM.
	  Normally the initial stack frame is set up in DRAM which is often
	  only available after lowlevel_init. With this option the initial
	  stack frame and the early C environment is set up before
	  lowlevel_init. Thus lowlevel_init does not need to be implemented
	  in assembler.

config SYS_DCACHE_SIZE
	int
	default 0
	help
	  The total size of the L1 Dcache, if known at compile time.

config SYS_DCACHE_LINE_SIZE
	int
	default 0
	help
	  The size of L1 Dcache lines, if known at compile time.

config SYS_ICACHE_SIZE
	int
	default 0
	help
	  The total size of the L1 ICache, if known at compile time.

config SYS_ICACHE_LINE_SIZE
	int
	default 0
	help
	  The size of L1 Icache lines, if known at compile time.

config SYS_CACHE_SIZE_AUTO
	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
	help
	  Select this (or let it be auto-selected by not defining any cache
	  sizes) in order to allow U-Boot to automatically detect the sizes
	  of caches at runtime. This has a small cost in code size & runtime
	  so if you know the cache configuration for your system at compile
	  time it would be beneficial to configure it.

config MIPS_L1_CACHE_SHIFT_4
	bool

config MIPS_L1_CACHE_SHIFT_5
	bool

config MIPS_L1_CACHE_SHIFT_6
	bool

config MIPS_L1_CACHE_SHIFT_7
	bool

config MIPS_L1_CACHE_SHIFT
	int
	default "7" if MIPS_L1_CACHE_SHIFT_7
	default "6" if MIPS_L1_CACHE_SHIFT_6
	default "5" if MIPS_L1_CACHE_SHIFT_5
	default "4" if MIPS_L1_CACHE_SHIFT_4
	default "5"

config MIPS_L2_CACHE
	bool
	help
	  Select this if your system includes an L2 cache and you want U-Boot
	  to initialise & maintain it.

config DYNAMIC_IO_PORT_BASE
	bool

config MIPS_CM
	bool
	help
	  Select this if your system contains a MIPS Coherence Manager and you
	  wish U-Boot to configure it or make use of it to retrieve system
	  information such as cache configuration.

config MIPS_INSERT_BOOT_CONFIG
	bool
	default n
	help
	  Enable this to insert some board-specific boot configuration in
	  the U-Boot binary at offset 0x10.

config MIPS_BOOT_CONFIG_WORD0
	hex
	depends on MIPS_INSERT_BOOT_CONFIG
	default 0x420 if TARGET_MALTA
	default 0x0
	help
	  Value which is inserted as boot config word 0.

config MIPS_BOOT_CONFIG_WORD1
	hex
	depends on MIPS_INSERT_BOOT_CONFIG
	default 0x0
	help
	  Value which is inserted as boot config word 1.

endif

endmenu
Commit	Line	Data
dd84058d MY	1	menu "MIPS architecture"
	2	depends on MIPS
	3
	4	config SYS_ARCH
dd84058d MY	5	default "mips"
dd84058d MY	6
b9863b6d	7	config SYS_CPU
20286cdf PB	8	default "mips32" if CPU_MIPS32
20286cdf PB	9	default "mips64" if CPU_MIPS64
b9863b6d	10
dd84058d MY	11	choice
dd84058d MY	12	prompt "Target select"
a26cd049	13	optional
dd84058d MY	14
	15	config TARGET_QEMU_MIPS
	16	bool "Support qemu-mips"
5ed063d1	17	select ROM_EXCEPTION_VECTORS
0e1dc345	18	select SUPPORTS_BIG_ENDIAN
02611cbb DS	19	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	20	select SUPPORTS_CPU_MIPS32_R2
aa45f75e DS	21	select SUPPORTS_CPU_MIPS64_R1
aa45f75e DS	22	select SUPPORTS_CPU_MIPS64_R2
5ed063d1	23	select SUPPORTS_LITTLE_ENDIAN
dd84058d MY	24
	25	config TARGET_MALTA
	26	bool "Support malta"
6242aa13 PB	27	select DM
6242aa13 PB	28	select DM_SERIAL
05e34255	29	select DYNAMIC_IO_PORT_BASE
566ce04d	30	select MIPS_CM
d1c3d8bd	31	select MIPS_INSERT_BOOT_CONFIG
5ed063d1	32	select MIPS_L1_CACHE_SHIFT_6
566ce04d	33	select MIPS_L2_CACHE
6242aa13 PB	34	select OF_CONTROL
6242aa13 PB	35	select OF_ISA_BUS
5ed063d1	36	select ROM_EXCEPTION_VECTORS
0e1dc345	37	select SUPPORTS_BIG_ENDIAN
02611cbb DS	38	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	39	select SUPPORTS_CPU_MIPS32_R2
40ba13c9	40	select SUPPORTS_CPU_MIPS32_R6
0f832b9c PB	41	select SUPPORTS_CPU_MIPS64_R1
	42	select SUPPORTS_CPU_MIPS64_R2
	43	select SUPPORTS_CPU_MIPS64_R6
5ed063d1	44	select SUPPORTS_LITTLE_ENDIAN
9d638eea	45	select SWAP_IO_SPACE
08a00cba	46	imply CMD_DM
dd84058d MY	47
	48	config TARGET_VCT
	49	bool "Support vct"
5ed063d1	50	select ROM_EXCEPTION_VECTORS
0e1dc345	51	select SUPPORTS_BIG_ENDIAN
02611cbb DS	52	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	53	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	54	select SYS_MIPS_CACHE_INIT_RAM_LOAD
dd84058d	55
1d3d0f1f WW	56	config ARCH_ATH79
1d3d0f1f WW	57	bool "Support QCA/Atheros ath79"
1d3d0f1f	58	select DM
5ed063d1	59	select OF_CONTROL
08a00cba	60	imply CMD_DM
1d3d0f1f	61
ee422142 ÁFR	62	config ARCH_BMIPS
ee422142 ÁFR	63	bool "Support BMIPS SoCs"
ee422142 ÁFR	64	select CLK
ee422142 ÁFR	65	select CPU
5ed063d1 MS	66	select DM
5ed063d1 MS	67	select OF_CONTROL
ee422142 ÁFR	68	select RAM
ee422142 ÁFR	69	select SYSRESET
08a00cba	70	imply CMD_DM
ee422142	71
32c1a6ee PCM	72	config MACH_PIC32
32c1a6ee PCM	73	bool "Support Microchip PIC32"
32c1a6ee	74	select DM
5ed063d1	75	select OF_CONTROL
08a00cba	76	imply CMD_DM
32c1a6ee	77
ad8783cb PB	78	config TARGET_BOSTON
	79	bool "Support Boston"
	80	select DM
	81	select DM_SERIAL
ad8783cb PB	82	select MIPS_CM
	83	select MIPS_L1_CACHE_SHIFT_6
	84	select MIPS_L2_CACHE
d2b12a57	85	select OF_BOARD_SETUP
5ed063d1 MS	86	select OF_CONTROL
5ed063d1 MS	87	select ROM_EXCEPTION_VECTORS
ad8783cb	88	select SUPPORTS_BIG_ENDIAN
ad8783cb PB	89	select SUPPORTS_CPU_MIPS32_R1
	90	select SUPPORTS_CPU_MIPS32_R2
	91	select SUPPORTS_CPU_MIPS32_R6
	92	select SUPPORTS_CPU_MIPS64_R1
	93	select SUPPORTS_CPU_MIPS64_R2
	94	select SUPPORTS_CPU_MIPS64_R6
5ed063d1	95	select SUPPORTS_LITTLE_ENDIAN
08a00cba	96	imply CMD_DM
ad8783cb	97
ebf2b9e3 ZLK	98	config TARGET_XILFPGA
ebf2b9e3 ZLK	99	bool "Support Imagination Xilfpga"
ebf2b9e3	100	select DM
ebf2b9e3	101	select DM_ETH
5ed063d1 MS	102	select DM_GPIO
5ed063d1 MS	103	select DM_SERIAL
ebf2b9e3	104	select MIPS_L1_CACHE_SHIFT_4
5ed063d1	105	select OF_CONTROL
af3971f8	106	select ROM_EXCEPTION_VECTORS
5ed063d1 MS	107	select SUPPORTS_CPU_MIPS32_R1
	108	select SUPPORTS_CPU_MIPS32_R2
	109	select SUPPORTS_LITTLE_ENDIAN
08a00cba	110	imply CMD_DM
ebf2b9e3 ZLK	111	help
	112	This supports IMGTEC MIPSfpga platform
	113
dd84058d MY	114	endchoice
dd84058d MY	115
ad8783cb	116	source "board/imgtec/boston/Kconfig"
dd84058d	117	source "board/imgtec/malta/Kconfig"
ebf2b9e3	118	source "board/imgtec/xilfpga/Kconfig"
dd84058d	119	source "board/micronas/vct/Kconfig"
dd84058d	120	source "board/qemu-mips/Kconfig"
1d3d0f1f	121	source "arch/mips/mach-ath79/Kconfig"
ee422142	122	source "arch/mips/mach-bmips/Kconfig"
32c1a6ee	123	source "arch/mips/mach-pic32/Kconfig"
dd84058d	124
0e1dc345 DS	125	if MIPS
	126
	127	choice
	128	prompt "Endianness selection"
	129	help
	130	Some MIPS boards can be configured for either little or big endian
	131	byte order. These modes require different U-Boot images. In general there
	132	is one preferred byteorder for a particular system but some systems are
	133	just as commonly used in the one or the other endianness.
	134
	135	config SYS_BIG_ENDIAN
	136	bool "Big endian"
	137	depends on SUPPORTS_BIG_ENDIAN
	138
	139	config SYS_LITTLE_ENDIAN
	140	bool "Little endian"
	141	depends on SUPPORTS_LITTLE_ENDIAN
	142
	143	endchoice
	144
02611cbb DS	145	choice
	146	prompt "CPU selection"
	147	default CPU_MIPS32_R2
	148
	149	config CPU_MIPS32_R1
	150	bool "MIPS32 Release 1"
	151	depends on SUPPORTS_CPU_MIPS32_R1
	152	select 32BIT
	153	help
c52ebea1	154	Choose this option to build an U-Boot for release 1 through 5 of the
02611cbb DS	155	MIPS32 architecture.
	156
	157	config CPU_MIPS32_R2
	158	bool "MIPS32 Release 2"
	159	depends on SUPPORTS_CPU_MIPS32_R2
	160	select 32BIT
	161	help
c52ebea1 PB	162	Choose this option to build an U-Boot for release 2 through 5 of the
	163	MIPS32 architecture.
	164
	165	config CPU_MIPS32_R6
	166	bool "MIPS32 Release 6"
	167	depends on SUPPORTS_CPU_MIPS32_R6
	168	select 32BIT
	169	help
	170	Choose this option to build an U-Boot for release 6 or later of the
02611cbb DS	171	MIPS32 architecture.
	172
	173	config CPU_MIPS64_R1
	174	bool "MIPS64 Release 1"
	175	depends on SUPPORTS_CPU_MIPS64_R1
	176	select 64BIT
	177	help
c52ebea1	178	Choose this option to build a kernel for release 1 through 5 of the
02611cbb DS	179	MIPS64 architecture.
	180
	181	config CPU_MIPS64_R2
	182	bool "MIPS64 Release 2"
	183	depends on SUPPORTS_CPU_MIPS64_R2
	184	select 64BIT
	185	help
c52ebea1 PB	186	Choose this option to build a kernel for release 2 through 5 of the
	187	MIPS64 architecture.
	188
	189	config CPU_MIPS64_R6
	190	bool "MIPS64 Release 6"
	191	depends on SUPPORTS_CPU_MIPS64_R6
	192	select 64BIT
	193	help
	194	Choose this option to build a kernel for release 6 or later of the
02611cbb DS	195	MIPS64 architecture.
	196
	197	endchoice
	198
af3971f8 DS	199	menu "General setup"
	200
	201	config ROM_EXCEPTION_VECTORS
	202	bool "Build U-Boot image with exception vectors"
	203	help
	204	Enable this to include exception vectors in the U-Boot image. This is
	205	required if the U-Boot entry point is equal to the address of the
	206	CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
	207	U-Boot booted from parallel NOR flash).
	208	Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
	209	In that case the image size will be reduced by 0x500 bytes.
	210
939a255a PB	211	config MIPS_CM_BASE
	212	hex "MIPS CM GCR Base Address"
	213	depends on MIPS_CM
ed048e7c	214	default 0x16100000 if TARGET_BOSTON
939a255a PB	215	default 0x1fbf8000
	216	help
	217	The physical base address at which to map the MIPS Coherence Manager
	218	Global Configuration Registers (GCRs). This should be set such that
	219	the GCRs occupy a region of the physical address space which is
	220	otherwise unused, or at minimum that software doesn't need to access.
	221
5ef337a0 DS	222	config MIPS_CACHE_INDEX_BASE
	223	hex "Index base address for cache initialisation"
	224	default 0x80000000 if CPU_MIPS32
	225	default 0xffffffff80000000 if CPU_MIPS64
	226	help
	227	This is the base address for a memory block, which is used for
	228	initialising the cache lines. This is also the base address of a memory
	229	block which is used for loading and filling cache lines when
	230	SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
	231	Normally this is CKSEG0. If the MIPS system needs to move this block
	232	to some SRAM or ScratchPad RAM, adapt this option accordingly.
	233
af3971f8 DS	234	endmenu
af3971f8 DS	235
25fc664f DS	236	menu "OS boot interface"
	237
	238	config MIPS_BOOT_CMDLINE_LEGACY
	239	bool "Hand over legacy command line to Linux kernel"
	240	default y
	241	help
	242	Enable this option if you want U-Boot to hand over the Yamon-style
	243	command line to the kernel. All bootargs will be prepared as argc/argv
	244	compatible list. The argument count (argc) is stored in register $a0.
	245	The address of the argument list (argv) is stored in register $a1.
	246
ca65e585 DS	247	config MIPS_BOOT_ENV_LEGACY
	248	bool "Hand over legacy environment to Linux kernel"
	249	default y
	250	help
	251	Enable this option if you want U-Boot to hand over the Yamon-style
	252	environment to the kernel. Information like memory size, initrd
	253	address and size will be prepared as zero-terminated key/value list.
1cc0a9f4	254	The address of the environment is stored in register $a2.
ca65e585	255
5002d8cc	256	config MIPS_BOOT_FDT
90b1c9fa	257	bool "Hand over a flattened device tree to Linux kernel"
5002d8cc DS	258	default n
	259	help
	260	Enable this option if you want U-Boot to hand over a flattened
90b1c9fa DS	261	device tree to the kernel. According to UHI register $a0 will be set
90b1c9fa DS	262	to -2 and the FDT address is stored in $a1.
5002d8cc	263
25fc664f DS	264	endmenu
25fc664f DS	265
0e1dc345 DS	266	config SUPPORTS_BIG_ENDIAN
	267	bool
	268
	269	config SUPPORTS_LITTLE_ENDIAN
	270	bool
	271
02611cbb DS	272	config SUPPORTS_CPU_MIPS32_R1
	273	bool
	274
	275	config SUPPORTS_CPU_MIPS32_R2
	276	bool
	277
c52ebea1 PB	278	config SUPPORTS_CPU_MIPS32_R6
	279	bool
	280
02611cbb DS	281	config SUPPORTS_CPU_MIPS64_R1
	282	bool
	283
	284	config SUPPORTS_CPU_MIPS64_R2
	285	bool
	286
c52ebea1 PB	287	config SUPPORTS_CPU_MIPS64_R6
	288	bool
	289
c57dafb5 DS	290	config CPU_MIPS32
c57dafb5 DS	291	bool
c52ebea1	292	default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2 \|\| CPU_MIPS32_R6
c57dafb5 DS	293
	294	config CPU_MIPS64
	295	bool
c52ebea1	296	default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS64_R6
c57dafb5	297
0315a289 DS	298	config MIPS_TUNE_4KC
	299	bool
	300
	301	config MIPS_TUNE_14KC
	302	bool
	303
	304	config MIPS_TUNE_24KC
	305	bool
	306
5f9cc363 DS	307	config MIPS_TUNE_34KC
	308	bool
	309
0a0a958b MV	310	config MIPS_TUNE_74KC
	311	bool
	312
02611cbb DS	313	config 32BIT
	314	bool
	315
	316	config 64BIT
	317	bool
	318
9d638eea DS	319	config SWAP_IO_SPACE
	320	bool
	321
dd7c7200 PB	322	config SYS_MIPS_CACHE_INIT_RAM_LOAD
	323	bool
	324
924ad866 DS	325	config MIPS_INIT_STACK_IN_SRAM
	326	bool
	327	default n
	328	help
	329	Select this if the initial stack frame could be setup in SRAM.
	330	Normally the initial stack frame is set up in DRAM which is often
	331	only available after lowlevel_init. With this option the initial
	332	stack frame and the early C environment is set up before
	333	lowlevel_init. Thus lowlevel_init does not need to be implemented
	334	in assembler.
	335
ace3be4f PB	336	config SYS_DCACHE_SIZE
	337	int
	338	default 0
	339	help
	340	The total size of the L1 Dcache, if known at compile time.
	341
37228621	342	config SYS_DCACHE_LINE_SIZE
4b7b0a0f	343	int
37228621 PB	344	default 0
	345	help
	346	The size of L1 Dcache lines, if known at compile time.
	347
ace3be4f PB	348	config SYS_ICACHE_SIZE
	349	int
	350	default 0
	351	help
	352	The total size of the L1 ICache, if known at compile time.
	353
37228621	354	config SYS_ICACHE_LINE_SIZE
ace3be4f PB	355	int
	356	default 0
	357	help
37228621	358	The size of L1 Icache lines, if known at compile time.
ace3be4f PB	359
	360	config SYS_CACHE_SIZE_AUTO
	361	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
37228621	362	SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
ace3be4f PB	363	help
	364	Select this (or let it be auto-selected by not defining any cache
	365	sizes) in order to allow U-Boot to automatically detect the sizes
	366	of caches at runtime. This has a small cost in code size & runtime
	367	so if you know the cache configuration for your system at compile
	368	time it would be beneficial to configure it.
	369
f53830e7 DS	370	config MIPS_L1_CACHE_SHIFT_4
	371	bool
	372
	373	config MIPS_L1_CACHE_SHIFT_5
	374	bool
	375
	376	config MIPS_L1_CACHE_SHIFT_6
	377	bool
	378
	379	config MIPS_L1_CACHE_SHIFT_7
	380	bool
	381
	382	config MIPS_L1_CACHE_SHIFT
	383	int
	384	default "7" if MIPS_L1_CACHE_SHIFT_7
	385	default "6" if MIPS_L1_CACHE_SHIFT_6
	386	default "5" if MIPS_L1_CACHE_SHIFT_5
	387	default "4" if MIPS_L1_CACHE_SHIFT_4
	388	default "5"
	389
4baa0ab6 PB	390	config MIPS_L2_CACHE
	391	bool
	392	help
	393	Select this if your system includes an L2 cache and you want U-Boot
	394	to initialise & maintain it.
	395
05e34255 PB	396	config DYNAMIC_IO_PORT_BASE
	397	bool
	398
b2b135d9 PB	399	config MIPS_CM
	400	bool
	401	help
	402	Select this if your system contains a MIPS Coherence Manager and you
	403	wish U-Boot to configure it or make use of it to retrieve system
	404	information such as cache configuration.
	405
d1c3d8bd DS	406	config MIPS_INSERT_BOOT_CONFIG
	407	bool
	408	default n
	409	help
	410	Enable this to insert some board-specific boot configuration in
	411	the U-Boot binary at offset 0x10.
	412
	413	config MIPS_BOOT_CONFIG_WORD0
	414	hex
	415	depends on MIPS_INSERT_BOOT_CONFIG
	416	default 0x420 if TARGET_MALTA
	417	default 0x0
	418	help
	419	Value which is inserted as boot config word 0.
	420
	421	config MIPS_BOOT_CONFIG_WORD1
	422	hex
	423	depends on MIPS_INSERT_BOOT_CONFIG
	424	default 0x0
	425	help
	426	Value which is inserted as boot config word 1.
	427
0e1dc345 DS	428	endif
0e1dc345 DS	429
dd84058d	430	endmenu