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Commit | Line | Data |
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39aa1a73 JL |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
39aa1a73 JL |
5 | */ |
6 | ||
7 | #include <common.h> | |
39aa1a73 | 8 | |
5614e71b YS |
9 | #include <fsl_ddr_sdram.h> |
10 | #include <fsl_ddr_dimm_params.h> | |
39aa1a73 | 11 | |
dfb49108 HW |
12 | void fsl_ddr_board_options(memctl_options_t *popts, |
13 | dimm_params_t *pdimm, | |
14 | unsigned int ctrl_num) | |
39aa1a73 JL |
15 | { |
16 | /* | |
17 | * Factors to consider for clock adjust: | |
18 | * - number of chips on bus | |
19 | * - position of slot | |
20 | * - DDR1 vs. DDR2? | |
21 | * - ??? | |
22 | * | |
23 | * This needs to be determined on a board-by-board basis. | |
24 | * 0110 3/4 cycle late | |
25 | * 0111 7/8 cycle late | |
26 | */ | |
27 | popts->clk_adjust = 7; | |
28 | ||
29 | /* | |
30 | * Factors to consider for CPO: | |
31 | * - frequency | |
32 | * - ddr1 vs. ddr2 | |
33 | */ | |
34 | popts->cpo_override = 10; | |
35 | ||
36 | /* | |
37 | * Factors to consider for write data delay: | |
38 | * - number of DIMMs | |
39 | * | |
40 | * 1 = 1/4 clock delay | |
41 | * 2 = 1/2 clock delay | |
42 | * 3 = 3/4 clock delay | |
43 | * 4 = 1 clock delay | |
44 | * 5 = 5/4 clock delay | |
45 | * 6 = 3/2 clock delay | |
46 | */ | |
47 | popts->write_data_delay = 3; | |
48 | ||
b4983e16 | 49 | /* 2T timing enable */ |
0dd38a35 | 50 | popts->twot_en = 1; |
b4983e16 | 51 | |
39aa1a73 JL |
52 | /* |
53 | * Factors to consider for half-strength driver enable: | |
54 | * - number of DIMMs installed | |
55 | */ | |
56 | popts->half_strength_driver_enable = 0; | |
57 | } |