[J-u-boot.git] / drivers / net / higmacv300.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2019, Linaro Limited
 */

#include <cpu_func.h>
#include <log.h>
#include <malloc.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <common.h>
#include <console.h>
#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <miiphy.h>
#include <net.h>
#include <reset.h>
#include <wait_bit.h>

#define STATION_ADDR_LOW		0x0000
#define STATION_ADDR_HIGH		0x0004
#define MAC_DUPLEX_HALF_CTRL		0x0008
#define PORT_MODE			0x0040
#define PORT_EN				0x0044
#define BIT_TX_EN			BIT(2)
#define BIT_RX_EN			BIT(1)
#define MODE_CHANGE_EN			0x01b4
#define BIT_MODE_CHANGE_EN		BIT(0)
#define MDIO_SINGLE_CMD			0x03c0
#define BIT_MDIO_BUSY			BIT(20)
#define MDIO_READ			(BIT(17) | BIT_MDIO_BUSY)
#define MDIO_WRITE			(BIT(16) | BIT_MDIO_BUSY)
#define MDIO_SINGLE_DATA		0x03c4
#define MDIO_RDATA_STATUS		0x03d0
#define BIT_MDIO_RDATA_INVALID		BIT(0)
#define RX_FQ_START_ADDR		0x0500
#define RX_FQ_DEPTH			0x0504
#define RX_FQ_WR_ADDR			0x0508
#define RX_FQ_RD_ADDR			0x050c
#define RX_FQ_REG_EN			0x0518
#define RX_BQ_START_ADDR		0x0520
#define RX_BQ_DEPTH			0x0524
#define RX_BQ_WR_ADDR			0x0528
#define RX_BQ_RD_ADDR			0x052c
#define RX_BQ_REG_EN			0x0538
#define TX_BQ_START_ADDR		0x0580
#define TX_BQ_DEPTH			0x0584
#define TX_BQ_WR_ADDR			0x0588
#define TX_BQ_RD_ADDR			0x058c
#define TX_BQ_REG_EN			0x0598
#define TX_RQ_START_ADDR		0x05a0
#define TX_RQ_DEPTH			0x05a4
#define TX_RQ_WR_ADDR			0x05a8
#define TX_RQ_RD_ADDR			0x05ac
#define TX_RQ_REG_EN			0x05b8
#define BIT_START_ADDR_EN		BIT(2)
#define BIT_DEPTH_EN			BIT(1)
#define DESC_WR_RD_ENA			0x05cc
#define BIT_RX_OUTCFF_WR		BIT(3)
#define BIT_RX_CFF_RD			BIT(2)
#define BIT_TX_OUTCFF_WR		BIT(1)
#define BIT_TX_CFF_RD			BIT(0)
#define BITS_DESC_ENA			(BIT_RX_OUTCFF_WR | BIT_RX_CFF_RD | \
					 BIT_TX_OUTCFF_WR | BIT_TX_CFF_RD)

/* MACIF_CTRL */
#define RGMII_SPEED_1000		0x2c
#define RGMII_SPEED_100			0x2f
#define RGMII_SPEED_10			0x2d
#define MII_SPEED_100			0x0f
#define MII_SPEED_10			0x0d
#define GMAC_SPEED_1000			0x05
#define GMAC_SPEED_100			0x01
#define GMAC_SPEED_10			0x00
#define GMAC_FULL_DUPLEX		BIT(4)

#define RX_DESC_NUM			64
#define TX_DESC_NUM			2
#define DESC_SIZE			32
#define DESC_WORD_SHIFT			3
#define DESC_BYTE_SHIFT			5
#define DESC_CNT(n)			((n) >> DESC_BYTE_SHIFT)
#define DESC_BYTE(n)			((n) << DESC_BYTE_SHIFT)
#define DESC_VLD_FREE			0
#define DESC_VLD_BUSY			1

#define MAC_MAX_FRAME_SIZE		1600

enum higmac_queue {
	RX_FQ,
	RX_BQ,
	TX_BQ,
	TX_RQ,
};

struct higmac_desc {
	unsigned int buf_addr;
	unsigned int buf_len:11;
	unsigned int reserve0:5;
	unsigned int data_len:11;
	unsigned int reserve1:2;
	unsigned int fl:2;
	unsigned int descvid:1;
	unsigned int reserve2[6];
};

struct higmac_priv {
	void __iomem *base;
	void __iomem *macif_ctrl;
	struct reset_ctl rst_phy;
	struct higmac_desc *rxfq;
	struct higmac_desc *rxbq;
	struct higmac_desc *txbq;
	struct higmac_desc *txrq;
	int rxdesc_in_use;
	struct mii_dev *bus;
	struct phy_device *phydev;
	int phyintf;
	int phyaddr;
};

#define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
#define invalidate_desc(d) \
	invalidate_dcache_range((unsigned long)(d), \
				(unsigned long)(d) + sizeof(*(d)))

static int higmac_write_hwaddr(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct higmac_priv *priv = dev_get_priv(dev);
	unsigned char *mac = pdata->enetaddr;
	u32 val;

	val = mac[1] | (mac[0] << 8);
	writel(val, priv->base + STATION_ADDR_HIGH);

	val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24);
	writel(val, priv->base + STATION_ADDR_LOW);

	return 0;
}

static int higmac_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct higmac_priv *priv = dev_get_priv(dev);

	/* Inform GMAC that the RX descriptor is no longer in use */
	writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);

	return 0;
}

static int higmac_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct higmac_priv *priv = dev_get_priv(dev);
	struct higmac_desc *fqd = priv->rxfq;
	struct higmac_desc *bqd = priv->rxbq;
	int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
	int timeout = 100000;
	int len = 0;
	int space;
	int i;

	fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
	fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));

	if (fqw_pos >= fqr_pos)
		space = RX_DESC_NUM - (fqw_pos - fqr_pos);
	else
		space = fqr_pos - fqw_pos;

	/* Leave one free to distinguish full filled from empty buffer */
	for (i = 0; i < space - 1; i++) {
		fqd = priv->rxfq + fqw_pos;
		invalidate_dcache_range(fqd->buf_addr,
					fqd->buf_addr + MAC_MAX_FRAME_SIZE);

		if (++fqw_pos >= RX_DESC_NUM)
			fqw_pos = 0;

		writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
	}

	bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
	bqd += bqr_pos;
	/* BQ is only ever written by GMAC */
	invalidate_desc(bqd);

	do {
		bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
		udelay(1);
	} while (--timeout && bqw_pos == bqr_pos);

	if (!timeout)
		return -ETIMEDOUT;

	if (++bqr_pos >= RX_DESC_NUM)
		bqr_pos = 0;

	len = bqd->data_len;

	/* CPU should not have touched this buffer since we added it to FQ */
	invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
	*packetp = (void *)(unsigned long)bqd->buf_addr;

	/* Record the RX_BQ descriptor that is holding RX data */
	priv->rxdesc_in_use = bqr_pos;

	return len;
}

static int higmac_send(struct udevice *dev, void *packet, int length)
{
	struct higmac_priv *priv = dev_get_priv(dev);
	struct higmac_desc *bqd = priv->txbq;
	int bqw_pos, rqw_pos, rqr_pos;
	int timeout = 1000;

	flush_cache((unsigned long)packet, length);

	bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
	bqd += bqw_pos;
	bqd->buf_addr = (unsigned long)packet;
	bqd->descvid = DESC_VLD_BUSY;
	bqd->data_len = length;
	flush_desc(bqd);

	if (++bqw_pos >= TX_DESC_NUM)
		bqw_pos = 0;

	writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);

	rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
	if (++rqr_pos >= TX_DESC_NUM)
		rqr_pos = 0;

	do {
		rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
		udelay(1);
	} while (--timeout && rqr_pos != rqw_pos);

	if (!timeout)
		return -ETIMEDOUT;

	writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);

	return 0;
}

static int higmac_adjust_link(struct higmac_priv *priv)
{
	struct phy_device *phydev = priv->phydev;
	int interface = priv->phyintf;
	u32 val;

	switch (interface) {
	case PHY_INTERFACE_MODE_RGMII:
		if (phydev->speed == SPEED_1000)
			val = RGMII_SPEED_1000;
		else if (phydev->speed == SPEED_100)
			val = RGMII_SPEED_100;
		else
			val = RGMII_SPEED_10;
		break;
	case PHY_INTERFACE_MODE_MII:
		if (phydev->speed == SPEED_100)
			val = MII_SPEED_100;
		else
			val = MII_SPEED_10;
		break;
	default:
		debug("unsupported mode: %d\n", interface);
		return -EINVAL;
	}

	if (phydev->duplex)
		val |= GMAC_FULL_DUPLEX;

	writel(val, priv->macif_ctrl);

	if (phydev->speed == SPEED_1000)
		val = GMAC_SPEED_1000;
	else if (phydev->speed == SPEED_100)
		val = GMAC_SPEED_100;
	else
		val = GMAC_SPEED_10;

	writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
	writel(val, priv->base + PORT_MODE);
	writel(0, priv->base + MODE_CHANGE_EN);
	writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);

	return 0;
}

static int higmac_start(struct udevice *dev)
{
	struct higmac_priv *priv = dev_get_priv(dev);
	struct phy_device *phydev = priv->phydev;
	int ret;

	ret = phy_startup(phydev);
	if (ret)
		return ret;

	if (!phydev->link) {
		debug("%s: link down\n", phydev->dev->name);
		return -ENODEV;
	}

	ret = higmac_adjust_link(priv);
	if (ret)
		return ret;

	/* Enable port */
	writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
	writel(BIT_TX_EN | BIT_RX_EN, priv->base + PORT_EN);

	return 0;
}

static void higmac_stop(struct udevice *dev)
{
	struct higmac_priv *priv = dev_get_priv(dev);

	/* Disable port */
	writel(0, priv->base + PORT_EN);
	writel(0, priv->base + DESC_WR_RD_ENA);
}

static const struct eth_ops higmac_ops = {
	.start		= higmac_start,
	.send		= higmac_send,
	.recv		= higmac_recv,
	.free_pkt	= higmac_free_pkt,
	.stop		= higmac_stop,
	.write_hwaddr	= higmac_write_hwaddr,
};

static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
	struct higmac_priv *priv = bus->priv;
	int ret;

	ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
				false, 1000, false);
	if (ret)
		return ret;

	writel(MDIO_READ | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);

	ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
				false, 1000, false);
	if (ret)
		return ret;

	if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
		return -EINVAL;

	return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
}

static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
			     int reg, u16 value)
{
	struct higmac_priv *priv = bus->priv;
	int ret;

	ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
				false, 1000, false);
	if (ret)
		return ret;

	writel(value, priv->base + MDIO_SINGLE_DATA);
	writel(MDIO_WRITE | addr << 8 | reg, priv->base + MDIO_SINGLE_CMD);

	return 0;
}

static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
{
	int i;

	for (i = 0; i < num; i++) {
		struct higmac_desc *desc = &descs[i];

		desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
							 MAC_MAX_FRAME_SIZE);
		if (!desc->buf_addr)
			goto free_bufs;

		desc->descvid = DESC_VLD_FREE;
		desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
		flush_desc(desc);
	}

	return 0;

free_bufs:
	while (--i > 0)
		free((void *)(unsigned long)descs[i].buf_addr);
	return -ENOMEM;
}

static int higmac_init_hw_queue(struct higmac_priv *priv,
				enum higmac_queue queue)
{
	struct higmac_desc *desc, **pdesc;
	u32 regaddr, regen, regdep;
	int depth;
	int len;

	switch (queue) {
	case RX_FQ:
		regaddr = RX_FQ_START_ADDR;
		regen = RX_FQ_REG_EN;
		regdep = RX_FQ_DEPTH;
		depth = RX_DESC_NUM;
		pdesc = &priv->rxfq;
		break;
	case RX_BQ:
		regaddr = RX_BQ_START_ADDR;
		regen = RX_BQ_REG_EN;
		regdep = RX_BQ_DEPTH;
		depth = RX_DESC_NUM;
		pdesc = &priv->rxbq;
		break;
	case TX_BQ:
		regaddr = TX_BQ_START_ADDR;
		regen = TX_BQ_REG_EN;
		regdep = TX_BQ_DEPTH;
		depth = TX_DESC_NUM;
		pdesc = &priv->txbq;
		break;
	case TX_RQ:
		regaddr = TX_RQ_START_ADDR;
		regen = TX_RQ_REG_EN;
		regdep = TX_RQ_DEPTH;
		depth = TX_DESC_NUM;
		pdesc = &priv->txrq;
		break;
	}

	/* Enable depth */
	writel(BIT_DEPTH_EN, priv->base + regen);
	writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
	writel(0, priv->base + regen);

	len = depth * sizeof(*desc);
	desc = memalign(ARCH_DMA_MINALIGN, len);
	if (!desc)
		return -ENOMEM;
	memset(desc, 0, len);
	flush_cache((unsigned long)desc, len);
	*pdesc = desc;

	/* Set up RX_FQ descriptors */
	if (queue == RX_FQ)
		higmac_init_rx_descs(desc, depth);

	/* Enable start address */
	writel(BIT_START_ADDR_EN, priv->base + regen);
	writel((unsigned long)desc, priv->base + regaddr);
	writel(0, priv->base + regen);

	return 0;
}

static int higmac_hw_init(struct higmac_priv *priv)
{
	int ret;

	/* Initialize hardware queues */
	ret = higmac_init_hw_queue(priv, RX_FQ);
	if (ret)
		return ret;

	ret = higmac_init_hw_queue(priv, RX_BQ);
	if (ret)
		goto free_rx_fq;

	ret = higmac_init_hw_queue(priv, TX_BQ);
	if (ret)
		goto free_rx_bq;

	ret = higmac_init_hw_queue(priv, TX_RQ);
	if (ret)
		goto free_tx_bq;

	/* Reset phy */
	reset_deassert(&priv->rst_phy);
	mdelay(10);
	reset_assert(&priv->rst_phy);
	mdelay(30);
	reset_deassert(&priv->rst_phy);
	mdelay(30);

	return 0;

free_tx_bq:
	free(priv->txbq);
free_rx_bq:
	free(priv->rxbq);
free_rx_fq:
	free(priv->rxfq);
	return ret;
}

static int higmac_probe(struct udevice *dev)
{
	struct higmac_priv *priv = dev_get_priv(dev);
	struct phy_device *phydev;
	struct mii_dev *bus;
	int ret;

	ret = higmac_hw_init(priv);
	if (ret)
		return ret;

	bus = mdio_alloc();
	if (!bus)
		return -ENOMEM;

	bus->read = higmac_mdio_read;
	bus->write = higmac_mdio_write;
	bus->priv = priv;
	priv->bus = bus;

	ret = mdio_register_seq(bus, dev->seq);
	if (ret)
		return ret;

	phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
	if (!phydev)
		return -ENODEV;

	phydev->supported &= PHY_GBIT_FEATURES;
	phydev->advertising = phydev->supported;
	priv->phydev = phydev;

	return phy_config(phydev);
}

static int higmac_remove(struct udevice *dev)
{
	struct higmac_priv *priv = dev_get_priv(dev);
	int i;

	mdio_unregister(priv->bus);
	mdio_free(priv->bus);

	/* Free RX packet buffers */
	for (i = 0; i < RX_DESC_NUM; i++)
		free((void *)(unsigned long)priv->rxfq[i].buf_addr);

	return 0;
}

static int higmac_ofdata_to_platdata(struct udevice *dev)
{
	struct higmac_priv *priv = dev_get_priv(dev);
	int phyintf = PHY_INTERFACE_MODE_NONE;
	const char *phy_mode;
	ofnode phy_node;

	priv->base = dev_remap_addr_index(dev, 0);
	priv->macif_ctrl = dev_remap_addr_index(dev, 1);

	phy_mode = dev_read_string(dev, "phy-mode");
	if (phy_mode)
		phyintf = phy_get_interface_by_name(phy_mode);
	if (phyintf == PHY_INTERFACE_MODE_NONE)
		return -ENODEV;
	priv->phyintf = phyintf;

	phy_node = dev_read_subnode(dev, "phy");
	if (!ofnode_valid(phy_node)) {
		debug("failed to find phy node\n");
		return -ENODEV;
	}
	priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);

	return reset_get_by_name(dev, "phy", &priv->rst_phy);
}

static const struct udevice_id higmac_ids[] = {
	{ .compatible = "hisilicon,hi3798cv200-gmac" },
	{ }
};

U_BOOT_DRIVER(eth_higmac) = {
	.name	= "eth_higmac",
	.id	= UCLASS_ETH,
	.of_match = higmac_ids,
	.ofdata_to_platdata = higmac_ofdata_to_platdata,
	.probe	= higmac_probe,
	.remove	= higmac_remove,
	.ops	= &higmac_ops,
	.priv_auto	= sizeof(struct higmac_priv),
	.plat_auto	= sizeof(struct eth_pdata),
};
Commit	Line	Data
1d5b5d2f SG	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2019, Linaro Limited
	4	*/
	5
1eb69ae4	6	#include <cpu_func.h>
f7ae49fc	7	#include <log.h>
336d4615	8	#include <malloc.h>
90526e9f	9	#include <asm/cache.h>
1d5b5d2f SG	10	#include <asm/io.h>
	11	#include <common.h>
	12	#include <console.h>
cd93d625	13	#include <linux/bitops.h>
1d5b5d2f	14	#include <linux/bug.h>
c05ed00a	15	#include <linux/delay.h>
1d5b5d2f SG	16	#include <linux/mii.h>
	17	#include <miiphy.h>
	18	#include <net.h>
	19	#include <reset.h>
	20	#include <wait_bit.h>
	21
	22	#define STATION_ADDR_LOW 0x0000
	23	#define STATION_ADDR_HIGH 0x0004
	24	#define MAC_DUPLEX_HALF_CTRL 0x0008
	25	#define PORT_MODE 0x0040
	26	#define PORT_EN 0x0044
	27	#define BIT_TX_EN BIT(2)
	28	#define BIT_RX_EN BIT(1)
	29	#define MODE_CHANGE_EN 0x01b4
	30	#define BIT_MODE_CHANGE_EN BIT(0)
	31	#define MDIO_SINGLE_CMD 0x03c0
	32	#define BIT_MDIO_BUSY BIT(20)
	33	#define MDIO_READ (BIT(17) \| BIT_MDIO_BUSY)
	34	#define MDIO_WRITE (BIT(16) \| BIT_MDIO_BUSY)
	35	#define MDIO_SINGLE_DATA 0x03c4
	36	#define MDIO_RDATA_STATUS 0x03d0
	37	#define BIT_MDIO_RDATA_INVALID BIT(0)
	38	#define RX_FQ_START_ADDR 0x0500
	39	#define RX_FQ_DEPTH 0x0504
	40	#define RX_FQ_WR_ADDR 0x0508
	41	#define RX_FQ_RD_ADDR 0x050c
	42	#define RX_FQ_REG_EN 0x0518
	43	#define RX_BQ_START_ADDR 0x0520
	44	#define RX_BQ_DEPTH 0x0524
	45	#define RX_BQ_WR_ADDR 0x0528
	46	#define RX_BQ_RD_ADDR 0x052c
	47	#define RX_BQ_REG_EN 0x0538
	48	#define TX_BQ_START_ADDR 0x0580
	49	#define TX_BQ_DEPTH 0x0584
	50	#define TX_BQ_WR_ADDR 0x0588
	51	#define TX_BQ_RD_ADDR 0x058c
	52	#define TX_BQ_REG_EN 0x0598
	53	#define TX_RQ_START_ADDR 0x05a0
	54	#define TX_RQ_DEPTH 0x05a4
	55	#define TX_RQ_WR_ADDR 0x05a8
	56	#define TX_RQ_RD_ADDR 0x05ac
	57	#define TX_RQ_REG_EN 0x05b8
	58	#define BIT_START_ADDR_EN BIT(2)
	59	#define BIT_DEPTH_EN BIT(1)
	60	#define DESC_WR_RD_ENA 0x05cc
	61	#define BIT_RX_OUTCFF_WR BIT(3)
	62	#define BIT_RX_CFF_RD BIT(2)
	63	#define BIT_TX_OUTCFF_WR BIT(1)
	64	#define BIT_TX_CFF_RD BIT(0)
	65	#define BITS_DESC_ENA (BIT_RX_OUTCFF_WR \| BIT_RX_CFF_RD \| \
	66	BIT_TX_OUTCFF_WR \| BIT_TX_CFF_RD)
	67
	68	/* MACIF_CTRL */
	69	#define RGMII_SPEED_1000 0x2c
	70	#define RGMII_SPEED_100 0x2f
	71	#define RGMII_SPEED_10 0x2d
	72	#define MII_SPEED_100 0x0f
	73	#define MII_SPEED_10 0x0d
	74	#define GMAC_SPEED_1000 0x05
	75	#define GMAC_SPEED_100 0x01
	76	#define GMAC_SPEED_10 0x00
	77	#define GMAC_FULL_DUPLEX BIT(4)
	78
	79	#define RX_DESC_NUM 64
80	#define TX_DESC_NUM 2
81	#define DESC_SIZE 32
82	#define DESC_WORD_SHIFT 3
83	#define DESC_BYTE_SHIFT 5
84	#define DESC_CNT(n) ((n) >> DESC_BYTE_SHIFT)
85	#define DESC_BYTE(n) ((n) << DESC_BYTE_SHIFT)
86	#define DESC_VLD_FREE 0
87	#define DESC_VLD_BUSY 1
88
89	#define MAC_MAX_FRAME_SIZE 1600
90
91	enum higmac_queue {
92	RX_FQ,
93	RX_BQ,
94	TX_BQ,
95	TX_RQ,
96	};
97
98	struct higmac_desc {
99	unsigned int buf_addr;
100	unsigned int buf_len:11;
101	unsigned int reserve0:5;
102	unsigned int data_len:11;
103	unsigned int reserve1:2;
104	unsigned int fl:2;
105	unsigned int descvid:1;
106	unsigned int reserve2[6];
107	};
108
109	struct higmac_priv {
110	void __iomem *base;
111	void __iomem *macif_ctrl;
112	struct reset_ctl rst_phy;
113	struct higmac_desc *rxfq;
114	struct higmac_desc *rxbq;
115	struct higmac_desc *txbq;
116	struct higmac_desc *txrq;
117	int rxdesc_in_use;
118	struct mii_dev *bus;
119	struct phy_device *phydev;
120	int phyintf;
121	int phyaddr;
122	};
123
124	#define flush_desc(d) flush_cache((unsigned long)(d), sizeof(*(d)))
125	#define invalidate_desc(d) \
126	invalidate_dcache_range((unsigned long)(d), \
127	(unsigned long)(d) + sizeof(*(d)))
128
129	static int higmac_write_hwaddr(struct udevice *dev)
130	{
131	struct eth_pdata *pdata = dev_get_platdata(dev);
132	struct higmac_priv *priv = dev_get_priv(dev);
133	unsigned char *mac = pdata->enetaddr;
134	u32 val;
135
136	val = mac[1] \| (mac[0] << 8);
137	writel(val, priv->base + STATION_ADDR_HIGH);
138
139	val = mac[5] \| (mac[4] << 8) \| (mac[3] << 16) \| (mac[2] << 24);
140	writel(val, priv->base + STATION_ADDR_LOW);
141
142	return 0;
143	}
144
145	static int higmac_free_pkt(struct udevice dev, uchar packet, int length)
146	{
147	struct higmac_priv *priv = dev_get_priv(dev);
148
149	/* Inform GMAC that the RX descriptor is no longer in use */
150	writel(DESC_BYTE(priv->rxdesc_in_use), priv->base + RX_BQ_RD_ADDR);
151
152	return 0;
153	}
154
155	static int higmac_recv(struct udevice dev, int flags, uchar *packetp)
156	{
157	struct higmac_priv *priv = dev_get_priv(dev);
158	struct higmac_desc *fqd = priv->rxfq;
159	struct higmac_desc *bqd = priv->rxbq;
160	int fqw_pos, fqr_pos, bqw_pos, bqr_pos;
161	int timeout = 100000;
162	int len = 0;
163	int space;
164	int i;
165
166	fqw_pos = DESC_CNT(readl(priv->base + RX_FQ_WR_ADDR));
167	fqr_pos = DESC_CNT(readl(priv->base + RX_FQ_RD_ADDR));
168
169	if (fqw_pos >= fqr_pos)
170	space = RX_DESC_NUM - (fqw_pos - fqr_pos);
171	else
172	space = fqr_pos - fqw_pos;
173
174	/* Leave one free to distinguish full filled from empty buffer */
175	for (i = 0; i < space - 1; i++) {
176	fqd = priv->rxfq + fqw_pos;
177	invalidate_dcache_range(fqd->buf_addr,
178	fqd->buf_addr + MAC_MAX_FRAME_SIZE);
179
180	if (++fqw_pos >= RX_DESC_NUM)
181	fqw_pos = 0;
182
183	writel(DESC_BYTE(fqw_pos), priv->base + RX_FQ_WR_ADDR);
184	}
185
186	bqr_pos = DESC_CNT(readl(priv->base + RX_BQ_RD_ADDR));
187	bqd += bqr_pos;
188	/* BQ is only ever written by GMAC */
189	invalidate_desc(bqd);
190
191	do {
192	bqw_pos = DESC_CNT(readl(priv->base + RX_BQ_WR_ADDR));
193	udelay(1);
194	} while (--timeout && bqw_pos == bqr_pos);
195
196	if (!timeout)
197	return -ETIMEDOUT;
198
199	if (++bqr_pos >= RX_DESC_NUM)
200	bqr_pos = 0;
201
202	len = bqd->data_len;
203
204	/* CPU should not have touched this buffer since we added it to FQ */
205	invalidate_dcache_range(bqd->buf_addr, bqd->buf_addr + len);
206	packetp = (void )(unsigned long)bqd->buf_addr;
207
208	/* Record the RX_BQ descriptor that is holding RX data */
209	priv->rxdesc_in_use = bqr_pos;
210
211	return len;
212	}
213
214	static int higmac_send(struct udevice dev, void packet, int length)
215	{
216	struct higmac_priv *priv = dev_get_priv(dev);
217	struct higmac_desc *bqd = priv->txbq;
218	int bqw_pos, rqw_pos, rqr_pos;
219	int timeout = 1000;
220
221	flush_cache((unsigned long)packet, length);
222
223	bqw_pos = DESC_CNT(readl(priv->base + TX_BQ_WR_ADDR));
224	bqd += bqw_pos;
225	bqd->buf_addr = (unsigned long)packet;
226	bqd->descvid = DESC_VLD_BUSY;
227	bqd->data_len = length;
228	flush_desc(bqd);
229
230	if (++bqw_pos >= TX_DESC_NUM)
231	bqw_pos = 0;
232
233	writel(DESC_BYTE(bqw_pos), priv->base + TX_BQ_WR_ADDR);
234
235	rqr_pos = DESC_CNT(readl(priv->base + TX_RQ_RD_ADDR));
236	if (++rqr_pos >= TX_DESC_NUM)
237	rqr_pos = 0;
238
239	do {
240	rqw_pos = DESC_CNT(readl(priv->base + TX_RQ_WR_ADDR));
241	udelay(1);
242	} while (--timeout && rqr_pos != rqw_pos);
243
244	if (!timeout)
245	return -ETIMEDOUT;
246
247	writel(DESC_BYTE(rqr_pos), priv->base + TX_RQ_RD_ADDR);
248
249	return 0;
250	}
251
252	static int higmac_adjust_link(struct higmac_priv *priv)
253	{
254	struct phy_device *phydev = priv->phydev;
255	int interface = priv->phyintf;
256	u32 val;
257
258	switch (interface) {
259	case PHY_INTERFACE_MODE_RGMII:
260	if (phydev->speed == SPEED_1000)
261	val = RGMII_SPEED_1000;
262	else if (phydev->speed == SPEED_100)
263	val = RGMII_SPEED_100;
264	else
265	val = RGMII_SPEED_10;
266	break;
267	case PHY_INTERFACE_MODE_MII:
268	if (phydev->speed == SPEED_100)
269	val = MII_SPEED_100;
270	else
271	val = MII_SPEED_10;
272	break;
273	default:
274	debug("unsupported mode: %d\n", interface);
275	return -EINVAL;
276	}
277
278	if (phydev->duplex)
279	val \|= GMAC_FULL_DUPLEX;
280
281	writel(val, priv->macif_ctrl);
282
283	if (phydev->speed == SPEED_1000)
284	val = GMAC_SPEED_1000;
285	else if (phydev->speed == SPEED_100)
286	val = GMAC_SPEED_100;
287	else
288	val = GMAC_SPEED_10;
289
290	writel(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);
291	writel(val, priv->base + PORT_MODE);
292	writel(0, priv->base + MODE_CHANGE_EN);
293	writel(phydev->duplex, priv->base + MAC_DUPLEX_HALF_CTRL);
294
295	return 0;
296	}
297
298	static int higmac_start(struct udevice *dev)
299	{
300	struct higmac_priv *priv = dev_get_priv(dev);
301	struct phy_device *phydev = priv->phydev;
302	int ret;
303
304	ret = phy_startup(phydev);
305	if (ret)
306	return ret;
307
308	if (!phydev->link) {
309	debug("%s: link down\n", phydev->dev->name);
310	return -ENODEV;
311	}
312
313	ret = higmac_adjust_link(priv);
314	if (ret)
315	return ret;
316
317	/* Enable port */
318	writel(BITS_DESC_ENA, priv->base + DESC_WR_RD_ENA);
319	writel(BIT_TX_EN \| BIT_RX_EN, priv->base + PORT_EN);
320
321	return 0;
322	}
323
324	static void higmac_stop(struct udevice *dev)
325	{
326	struct higmac_priv *priv = dev_get_priv(dev);
327
328	/* Disable port */
329	writel(0, priv->base + PORT_EN);
330	writel(0, priv->base + DESC_WR_RD_ENA);
331	}
332
333	static const struct eth_ops higmac_ops = {
334	.start = higmac_start,
335	.send = higmac_send,
336	.recv = higmac_recv,
337	.free_pkt = higmac_free_pkt,
338	.stop = higmac_stop,
339	.write_hwaddr = higmac_write_hwaddr,
340	};
341
342	static int higmac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
343	{
344	struct higmac_priv *priv = bus->priv;
345	int ret;
346
347	ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
348	false, 1000, false);
349	if (ret)
350	return ret;
351
352	writel(MDIO_READ \| addr << 8 \| reg, priv->base + MDIO_SINGLE_CMD);
353
354	ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
355	false, 1000, false);
356	if (ret)
357	return ret;
358
359	if (readl(priv->base + MDIO_RDATA_STATUS) & BIT_MDIO_RDATA_INVALID)
360	return -EINVAL;
361
362	return readl(priv->base + MDIO_SINGLE_DATA) >> 16;
363	}
364
365	static int higmac_mdio_write(struct mii_dev *bus, int addr, int devad,
366	int reg, u16 value)
367	{
368	struct higmac_priv *priv = bus->priv;
369	int ret;
370
371	ret = wait_for_bit_le32(priv->base + MDIO_SINGLE_CMD, BIT_MDIO_BUSY,
372	false, 1000, false);
373	if (ret)
374	return ret;
375
376	writel(value, priv->base + MDIO_SINGLE_DATA);
377	writel(MDIO_WRITE \| addr << 8 \| reg, priv->base + MDIO_SINGLE_CMD);
378
379	return 0;
380	}
381
382	static int higmac_init_rx_descs(struct higmac_desc *descs, int num)
383	{
384	int i;
385
386	for (i = 0; i < num; i++) {
387	struct higmac_desc *desc = &descs[i];
388
389	desc->buf_addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
390	MAC_MAX_FRAME_SIZE);
391	if (!desc->buf_addr)
392	goto free_bufs;
393
394	desc->descvid = DESC_VLD_FREE;
395	desc->buf_len = MAC_MAX_FRAME_SIZE - 1;
396	flush_desc(desc);
397	}
398
399	return 0;
400
401	free_bufs:
402	while (--i > 0)
403	free((void *)(unsigned long)descs[i].buf_addr);
404	return -ENOMEM;
405	}
406
407	static int higmac_init_hw_queue(struct higmac_priv *priv,
408	enum higmac_queue queue)
409	{
410	struct higmac_desc desc, *pdesc;
411	u32 regaddr, regen, regdep;
412	int depth;
413	int len;
414
415	switch (queue) {
416	case RX_FQ:
417	regaddr = RX_FQ_START_ADDR;
418	regen = RX_FQ_REG_EN;
419	regdep = RX_FQ_DEPTH;
420	depth = RX_DESC_NUM;
421	pdesc = &priv->rxfq;
422	break;
423	case RX_BQ:
424	regaddr = RX_BQ_START_ADDR;
425	regen = RX_BQ_REG_EN;
426	regdep = RX_BQ_DEPTH;
427	depth = RX_DESC_NUM;
428	pdesc = &priv->rxbq;
429	break;
430	case TX_BQ:
431	regaddr = TX_BQ_START_ADDR;
432	regen = TX_BQ_REG_EN;
433	regdep = TX_BQ_DEPTH;
434	depth = TX_DESC_NUM;
435	pdesc = &priv->txbq;
436	break;
437	case TX_RQ:
438	regaddr = TX_RQ_START_ADDR;
439	regen = TX_RQ_REG_EN;
440	regdep = TX_RQ_DEPTH;
441	depth = TX_DESC_NUM;
442	pdesc = &priv->txrq;
443	break;
444	}
445
446	/* Enable depth */
447	writel(BIT_DEPTH_EN, priv->base + regen);
448	writel(depth << DESC_WORD_SHIFT, priv->base + regdep);
449	writel(0, priv->base + regen);
450
451	len = depth * sizeof(*desc);
452	desc = memalign(ARCH_DMA_MINALIGN, len);
453	if (!desc)
454	return -ENOMEM;
455	memset(desc, 0, len);
456	flush_cache((unsigned long)desc, len);
457	*pdesc = desc;
458
459	/* Set up RX_FQ descriptors */
460	if (queue == RX_FQ)
461	higmac_init_rx_descs(desc, depth);
462
463	/* Enable start address */
464	writel(BIT_START_ADDR_EN, priv->base + regen);
465	writel((unsigned long)desc, priv->base + regaddr);
466	writel(0, priv->base + regen);
467
468	return 0;
469	}
470
471	static int higmac_hw_init(struct higmac_priv *priv)
472	{
473	int ret;
474
475	/* Initialize hardware queues */
476	ret = higmac_init_hw_queue(priv, RX_FQ);
477	if (ret)
478	return ret;
479
480	ret = higmac_init_hw_queue(priv, RX_BQ);
481	if (ret)
482	goto free_rx_fq;
483
484	ret = higmac_init_hw_queue(priv, TX_BQ);
485	if (ret)
486	goto free_rx_bq;
487
488	ret = higmac_init_hw_queue(priv, TX_RQ);
489	if (ret)
490	goto free_tx_bq;
491
492	/* Reset phy */
493	reset_deassert(&priv->rst_phy);
494	mdelay(10);
495	reset_assert(&priv->rst_phy);
496	mdelay(30);
497	reset_deassert(&priv->rst_phy);
498	mdelay(30);
499
500	return 0;
501
502	free_tx_bq:
503	free(priv->txbq);
504	free_rx_bq:
505	free(priv->rxbq);
506	free_rx_fq:
507	free(priv->rxfq);
508	return ret;
509	}
510
511	static int higmac_probe(struct udevice *dev)
512	{
513	struct higmac_priv *priv = dev_get_priv(dev);
514	struct phy_device *phydev;
515	struct mii_dev *bus;
516	int ret;
517
518	ret = higmac_hw_init(priv);
519	if (ret)
520	return ret;
521
522	bus = mdio_alloc();
523	if (!bus)
524	return -ENOMEM;
525
526	bus->read = higmac_mdio_read;
527	bus->write = higmac_mdio_write;
528	bus->priv = priv;
529	priv->bus = bus;
530
531	ret = mdio_register_seq(bus, dev->seq);
532	if (ret)
533	return ret;
534
535	phydev = phy_connect(bus, priv->phyaddr, dev, priv->phyintf);
536	if (!phydev)
537	return -ENODEV;
538
539	phydev->supported &= PHY_GBIT_FEATURES;
540	phydev->advertising = phydev->supported;
541	priv->phydev = phydev;
542
543	return phy_config(phydev);
544	}
545
546	static int higmac_remove(struct udevice *dev)
547	{
548	struct higmac_priv *priv = dev_get_priv(dev);
549	int i;
550
551	mdio_unregister(priv->bus);
552	mdio_free(priv->bus);
553
554	/* Free RX packet buffers */
555	for (i = 0; i < RX_DESC_NUM; i++)
556	free((void *)(unsigned long)priv->rxfq[i].buf_addr);
557
558	return 0;
559	}
560
561	static int higmac_ofdata_to_platdata(struct udevice *dev)
562	{
563	struct higmac_priv *priv = dev_get_priv(dev);
564	int phyintf = PHY_INTERFACE_MODE_NONE;
565	const char *phy_mode;
566	ofnode phy_node;
567
568	priv->base = dev_remap_addr_index(dev, 0);
569	priv->macif_ctrl = dev_remap_addr_index(dev, 1);
570
571	phy_mode = dev_read_string(dev, "phy-mode");
572	if (phy_mode)
573	phyintf = phy_get_interface_by_name(phy_mode);
574	if (phyintf == PHY_INTERFACE_MODE_NONE)
575	return -ENODEV;
576	priv->phyintf = phyintf;
577
578	phy_node = dev_read_subnode(dev, "phy");
579	if (!ofnode_valid(phy_node)) {
580	debug("failed to find phy node\n");
581	return -ENODEV;
582	}
583	priv->phyaddr = ofnode_read_u32_default(phy_node, "reg", 0);
584
585	return reset_get_by_name(dev, "phy", &priv->rst_phy);
586	}
587
588	static const struct udevice_id higmac_ids[] = {
589	{ .compatible = "hisilicon,hi3798cv200-gmac" },
590	{ }
591	};
592
593	U_BOOT_DRIVER(eth_higmac) = {
594	.name = "eth_higmac",
595	.id = UCLASS_ETH,
596	.of_match = higmac_ids,
597	.ofdata_to_platdata = higmac_ofdata_to_platdata,
598	.probe = higmac_probe,
599	.remove = higmac_remove,
600	.ops = &higmac_ops,
41575d8e	601	.priv_auto = sizeof(struct higmac_priv),
caa4daa2	602	.plat_auto = sizeof(struct eth_pdata),
1d5b5d2f	603	};