[J-u-boot.git] / drivers / net / ftmac110.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Faraday 10/100Mbps Ethernet Controller
 *
 * (C) Copyright 2013 Faraday Technology
 * Dante Su <[email protected]>
 */

#include <common.h>
#include <command.h>
#include <log.h>
#include <malloc.h>
#include <net.h>
#include <asm/cache.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/dma-mapping.h>

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
#endif

#include "ftmac110.h"

#define CFG_RXDES_NUM   8
#define CFG_TXDES_NUM   2
#define CFG_XBUF_SIZE   1536

#define CFG_MDIORD_TIMEOUT  (CONFIG_SYS_HZ >> 1) /* 500 ms */
#define CFG_MDIOWR_TIMEOUT  (CONFIG_SYS_HZ >> 1) /* 500 ms */
#define CFG_LINKUP_TIMEOUT  (CONFIG_SYS_HZ << 2) /* 4 sec */

/*
 * FTMAC110 DMA design issue
 *
 * Its DMA engine has a weird restriction that its Rx DMA engine
 * accepts only 16-bits aligned address, 32-bits aligned is not
 * acceptable. However this restriction does not apply to Tx DMA.
 *
 * Conclusion:
 * (1) Tx DMA Buffer Address:
 *     1 bytes aligned: Invalid
 *     2 bytes aligned: O.K
 *     4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
 * (2) Rx DMA Buffer Address:
 *     1 bytes aligned: Invalid
 *     2 bytes aligned: O.K
 *     4 bytes aligned: Invalid
 */

struct ftmac110_chip {
	void __iomem *regs;
	uint32_t imr;
	uint32_t maccr;
	uint32_t lnkup;
	uint32_t phy_addr;

	struct ftmac110_desc *rxd;
	ulong                rxd_dma;
	uint32_t             rxd_idx;

	struct ftmac110_desc *txd;
	ulong                txd_dma;
	uint32_t             txd_idx;
};

static int ftmac110_reset(struct eth_device *dev);

static uint16_t mdio_read(struct eth_device *dev,
	uint8_t phyaddr, uint8_t phyreg)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs *regs = chip->regs;
	uint32_t tmp, ts;
	uint16_t ret = 0xffff;

	tmp = PHYCR_READ
		| (phyaddr << PHYCR_ADDR_SHIFT)
		| (phyreg  << PHYCR_REG_SHIFT);

	writel(tmp, &regs->phycr);

	for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
		tmp = readl(&regs->phycr);
		if (tmp & PHYCR_READ)
			continue;
		break;
	}

	if (tmp & PHYCR_READ)
		printf("ftmac110: mdio read timeout\n");
	else
		ret = (uint16_t)(tmp & 0xffff);

	return ret;
}

static void mdio_write(struct eth_device *dev,
	uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs *regs = chip->regs;
	uint32_t tmp, ts;

	tmp = PHYCR_WRITE
		| (phyaddr << PHYCR_ADDR_SHIFT)
		| (phyreg  << PHYCR_REG_SHIFT);

	writel(phydata, &regs->phydr);
	writel(tmp, &regs->phycr);

	for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
		if (readl(&regs->phycr) & PHYCR_WRITE)
			continue;
		break;
	}

	if (readl(&regs->phycr) & PHYCR_WRITE)
		printf("ftmac110: mdio write timeout\n");
}

static uint32_t ftmac110_phyqry(struct eth_device *dev)
{
	ulong ts;
	uint32_t maccr;
	uint16_t pa, tmp, bmsr, bmcr;
	struct ftmac110_chip *chip = dev->priv;

	/* Default = 100Mbps Full */
	maccr = MACCR_100M | MACCR_FD;

	/* 1. find the phy device  */
	for (pa = 0; pa < 32; ++pa) {
		tmp = mdio_read(dev, pa, MII_PHYSID1);
		if (tmp == 0xFFFF || tmp == 0x0000)
			continue;
		chip->phy_addr = pa;
		break;
	}
	if (pa >= 32) {
		puts("ftmac110: phy device not found!\n");
		goto exit;
	}

	/* 2. wait until link-up & auto-negotiation complete */
	chip->lnkup = 0;
	bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
	ts = get_timer(0);
	do {
		bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
		chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
		if (!chip->lnkup)
			continue;
		if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
			break;
	} while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
	if (!chip->lnkup) {
		puts("ftmac110: link down\n");
		goto exit;
	}
	if (!(bmcr & BMCR_ANENABLE))
		puts("ftmac110: auto negotiation disabled\n");
	else if (!(bmsr & BMSR_ANEGCOMPLETE))
		puts("ftmac110: auto negotiation timeout\n");

	/* 3. derive MACCR */
	if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
		tmp  = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
		tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
		if (tmp & LPA_100FULL)      /* 100Mbps full-duplex */
			maccr = MACCR_100M | MACCR_FD;
		else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
			maccr = MACCR_100M;
		else if (tmp & LPA_10FULL)  /* 10Mbps full-duplex */
			maccr = MACCR_FD;
		else if (tmp & LPA_10HALF)  /* 10Mbps half-duplex */
			maccr = 0;
	} else {
		if (bmcr & BMCR_SPEED100)
			maccr = MACCR_100M;
		else
			maccr = 0;
		if (bmcr & BMCR_FULLDPLX)
			maccr |= MACCR_FD;
	}

exit:
	printf("ftmac110: %d Mbps, %s\n",
	       (maccr & MACCR_100M) ? 100 : 10,
	       (maccr & MACCR_FD) ? "Full" : "half");
	return maccr;
}

static int ftmac110_reset(struct eth_device *dev)
{
	uint8_t *a;
	uint32_t i, maccr;
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs *regs = chip->regs;

	/* 1. MAC reset */
	writel(MACCR_RESET, &regs->maccr);
	for (i = get_timer(0); get_timer(i) < 1000; ) {
		if (readl(&regs->maccr) & MACCR_RESET)
			continue;
		break;
	}
	if (readl(&regs->maccr) & MACCR_RESET) {
		printf("ftmac110: reset failed\n");
		return -ENXIO;
	}

	/* 1-1. Init tx ring */
	for (i = 0; i < CFG_TXDES_NUM; ++i) {
		/* owned by SW */
		chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
	}
	chip->txd_idx = 0;

	/* 1-2. Init rx ring */
	for (i = 0; i < CFG_RXDES_NUM; ++i) {
		/* owned by HW */
		chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
		chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
	}
	chip->rxd_idx = 0;

	/* 2. PHY status query */
	maccr = ftmac110_phyqry(dev);

	/* 3. Fix up the MACCR value */
	chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
		| MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;

	/* 4. MAC address setup */
	a = dev->enetaddr;
	writel(a[1] | (a[0] << 8), &regs->mac[0]);
	writel(a[5] | (a[4] << 8) | (a[3] << 16)
		| (a[2] << 24), &regs->mac[1]);

	/* 5. MAC registers setup */
	writel(chip->rxd_dma, &regs->rxba);
	writel(chip->txd_dma, &regs->txba);
	/* interrupt at each tx/rx */
	writel(ITC_DEFAULT, &regs->itc);
	/* no tx pool, rx poll = 1 normal cycle */
	writel(APTC_DEFAULT, &regs->aptc);
	/* rx threshold = [6/8 fifo, 2/8 fifo] */
	writel(DBLAC_DEFAULT, &regs->dblac);
	/* disable & clear all interrupt status */
	chip->imr = 0;
	writel(ISR_ALL, &regs->isr);
	writel(chip->imr, &regs->imr);
	/* enable mac */
	writel(chip->maccr, &regs->maccr);

	return 0;
}

static int ftmac110_probe(struct eth_device *dev, struct bd_info *bis)
{
	debug("ftmac110: probe\n");

	if (ftmac110_reset(dev))
		return -1;

	return 0;
}

static void ftmac110_halt(struct eth_device *dev)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs *regs = chip->regs;

	writel(0, &regs->imr);
	writel(0, &regs->maccr);

	debug("ftmac110: halt\n");
}

static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_regs *regs = chip->regs;
	struct ftmac110_desc *txd;
	uint64_t ctrl;

	if (!chip->lnkup)
		return 0;

	if (len <= 0 || len > CFG_XBUF_SIZE) {
		printf("ftmac110: bad tx pkt len(%d)\n", len);
		return 0;
	}

	len = max(60, len);

	txd = &chip->txd[chip->txd_idx];
	ctrl = le64_to_cpu(txd->ctrl);
	if (ctrl & FTMAC110_TXD_OWNER) {
		/* kick-off Tx DMA */
		writel(0xffffffff, &regs->txpd);
		printf("ftmac110: out of txd\n");
		return 0;
	}

	memcpy(txd->vbuf, (void *)pkt, len);
	dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);

	/* clear control bits */
	ctrl &= FTMAC110_TXD_CLRMASK;
	/* set len, fts and lts */
	ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
	/* set owner bit */
	ctrl |= FTMAC110_TXD_OWNER;
	/* write back to descriptor */
	txd->ctrl = cpu_to_le64(ctrl);

	/* kick-off Tx DMA */
	writel(0xffffffff, &regs->txpd);

	chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;

	return len;
}

static int ftmac110_recv(struct eth_device *dev)
{
	struct ftmac110_chip *chip = dev->priv;
	struct ftmac110_desc *rxd;
	uint32_t len, rlen = 0;
	uint64_t ctrl;
	uint8_t *buf;

	if (!chip->lnkup)
		return 0;

	do {
		rxd = &chip->rxd[chip->rxd_idx];
		ctrl = le64_to_cpu(rxd->ctrl);
		if (ctrl & FTMAC110_RXD_OWNER)
			break;

		len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
		buf = rxd->vbuf;

		if (ctrl & FTMAC110_RXD_ERRMASK) {
			printf("ftmac110: rx error\n");
		} else {
			dma_map_single(buf, len, DMA_FROM_DEVICE);
			net_process_received_packet(buf, len);
			rlen += len;
		}

		/* owned by hardware */
		ctrl &= FTMAC110_RXD_CLRMASK;
		ctrl |= FTMAC110_RXD_OWNER;
		rxd->ctrl |= cpu_to_le64(ctrl);

		chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
	} while (0);

	return rlen;
}

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)

static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
			      int reg)
{
	uint16_t value = 0;
	int ret = 0;
	struct eth_device *dev;

	dev = eth_get_dev_by_name(bus->name);
	if (dev == NULL) {
		printf("%s: no such device\n", bus->name);
		ret = -1;
	} else {
		value = mdio_read(dev, addr, reg);
	}

	if (ret < 0)
		return ret;
	return value;
}

static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
			       int reg, u16 value)
{
	int ret = 0;
	struct eth_device *dev;

	dev = eth_get_dev_by_name(bus->name);
	if (dev == NULL) {
		printf("%s: no such device\n", bus->name);
		ret = -1;
	} else {
		mdio_write(dev, addr, reg, value);
	}

	return ret;
}

#endif    /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */

int ftmac110_initialize(struct bd_info *bis)
{
	int i, card_nr = 0;
	struct eth_device *dev;
	struct ftmac110_chip *chip;

	dev = malloc(sizeof(*dev) + sizeof(*chip));
	if (dev == NULL) {
		panic("ftmac110: out of memory 1\n");
		return -1;
	}
	chip = (struct ftmac110_chip *)(dev + 1);
	memset(dev, 0, sizeof(*dev) + sizeof(*chip));

	sprintf(dev->name, "FTMAC110#%d", card_nr);

	dev->iobase = CONFIG_FTMAC110_BASE;
	chip->regs = (void __iomem *)dev->iobase;
	dev->priv = chip;
	dev->init = ftmac110_probe;
	dev->halt = ftmac110_halt;
	dev->send = ftmac110_send;
	dev->recv = ftmac110_recv;

	/* allocate tx descriptors (it must be 16 bytes aligned) */
	chip->txd = dma_alloc_coherent(
		sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
	if (!chip->txd)
		panic("ftmac110: out of memory 3\n");
	memset(chip->txd, 0,
	       sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
	for (i = 0; i < CFG_TXDES_NUM; ++i) {
		void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);

		if (!va)
			panic("ftmac110: out of memory 4\n");
		chip->txd[i].vbuf = va;
		chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
		chip->txd[i].ctrl = 0;	/* owned by SW */
	}
	chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
	chip->txd_idx = 0;

	/* allocate rx descriptors (it must be 16 bytes aligned) */
	chip->rxd = dma_alloc_coherent(
		sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
	if (!chip->rxd)
		panic("ftmac110: out of memory 4\n");
	memset((void *)chip->rxd, 0,
	       sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
	for (i = 0; i < CFG_RXDES_NUM; ++i) {
		void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);

		if (!va)
			panic("ftmac110: out of memory 5\n");
		/* it needs to be exactly 2 bytes aligned */
		va = ((uint8_t *)va + 2);
		chip->rxd[i].vbuf = va;
		chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
		chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
			| FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
	}
	chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
	chip->rxd_idx = 0;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	int retval;
	struct mii_dev *mdiodev = mdio_alloc();
	if (!mdiodev)
		return -ENOMEM;
	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
	mdiodev->read = ftmac110_mdio_read;
	mdiodev->write = ftmac110_mdio_write;

	retval = mdio_register(mdiodev);
	if (retval < 0)
		return retval;
#endif

	card_nr++;

	return card_nr;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c4775476 KJS	2	/*
	3	* Faraday 10/100Mbps Ethernet Controller
	4	*
102a8cd3	5	* (C) Copyright 2013 Faraday Technology
c4775476	6	* Dante Su <[email protected]>
c4775476 KJS	7	*/
	8
	9	#include <common.h>
	10	#include <command.h>
f7ae49fc	11	#include <log.h>
c4775476 KJS	12	#include <malloc.h>
c4775476 KJS	13	#include <net.h>
90526e9f	14	#include <asm/cache.h>
1221ce45	15	#include <linux/errno.h>
c4775476	16	#include <asm/io.h>
9d86b89c	17	#include <linux/dma-mapping.h>
c4775476 KJS	18
	19	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	20	#include <miiphy.h>
	21	#endif
	22
	23	#include "ftmac110.h"
	24
	25	#define CFG_RXDES_NUM 8
	26	#define CFG_TXDES_NUM 2
	27	#define CFG_XBUF_SIZE 1536
	28
	29	#define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
	30	#define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
	31	#define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
	32
	33	/*
	34	* FTMAC110 DMA design issue
	35	*
	36	* Its DMA engine has a weird restriction that its Rx DMA engine
	37	* accepts only 16-bits aligned address, 32-bits aligned is not
	38	* acceptable. However this restriction does not apply to Tx DMA.
	39	*
	40	* Conclusion:
	41	* (1) Tx DMA Buffer Address:
	42	* 1 bytes aligned: Invalid
	43	* 2 bytes aligned: O.K
	44	* 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
	45	* (2) Rx DMA Buffer Address:
	46	* 1 bytes aligned: Invalid
	47	* 2 bytes aligned: O.K
	48	* 4 bytes aligned: Invalid
	49	*/
	50
	51	struct ftmac110_chip {
	52	void __iomem *regs;
	53	uint32_t imr;
	54	uint32_t maccr;
	55	uint32_t lnkup;
	56	uint32_t phy_addr;
	57
0628cb26	58	struct ftmac110_desc *rxd;
c4775476 KJS	59	ulong rxd_dma;
	60	uint32_t rxd_idx;
	61
0628cb26	62	struct ftmac110_desc *txd;
c4775476 KJS	63	ulong txd_dma;
	64	uint32_t txd_idx;
	65	};
	66
	67	static int ftmac110_reset(struct eth_device *dev);
	68
	69	static uint16_t mdio_read(struct eth_device *dev,
	70	uint8_t phyaddr, uint8_t phyreg)
	71	{
	72	struct ftmac110_chip *chip = dev->priv;
4b7be199	73	struct ftmac110_regs *regs = chip->regs;
c4775476 KJS	74	uint32_t tmp, ts;
	75	uint16_t ret = 0xffff;
	76
	77	tmp = PHYCR_READ
	78	\| (phyaddr << PHYCR_ADDR_SHIFT)
	79	\| (phyreg << PHYCR_REG_SHIFT);
	80
	81	writel(tmp, &regs->phycr);
	82
	83	for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
	84	tmp = readl(&regs->phycr);
	85	if (tmp & PHYCR_READ)
	86	continue;
	87	break;
	88	}
	89
	90	if (tmp & PHYCR_READ)
	91	printf("ftmac110: mdio read timeout\n");
	92	else
	93	ret = (uint16_t)(tmp & 0xffff);
	94
	95	return ret;
	96	}
	97
	98	static void mdio_write(struct eth_device *dev,
	99	uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
	100	{
	101	struct ftmac110_chip *chip = dev->priv;
4b7be199	102	struct ftmac110_regs *regs = chip->regs;
c4775476 KJS	103	uint32_t tmp, ts;
	104
	105	tmp = PHYCR_WRITE
	106	\| (phyaddr << PHYCR_ADDR_SHIFT)
	107	\| (phyreg << PHYCR_REG_SHIFT);
	108
	109	writel(phydata, &regs->phydr);
	110	writel(tmp, &regs->phycr);
	111
	112	for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
	113	if (readl(&regs->phycr) & PHYCR_WRITE)
	114	continue;
	115	break;
	116	}
	117
	118	if (readl(&regs->phycr) & PHYCR_WRITE)
	119	printf("ftmac110: mdio write timeout\n");
	120	}
	121
	122	static uint32_t ftmac110_phyqry(struct eth_device *dev)
	123	{
	124	ulong ts;
	125	uint32_t maccr;
	126	uint16_t pa, tmp, bmsr, bmcr;
	127	struct ftmac110_chip *chip = dev->priv;
	128
	129	/* Default = 100Mbps Full */
	130	maccr = MACCR_100M \| MACCR_FD;
	131
	132	/* 1. find the phy device */
	133	for (pa = 0; pa < 32; ++pa) {
	134	tmp = mdio_read(dev, pa, MII_PHYSID1);
	135	if (tmp == 0xFFFF \|\| tmp == 0x0000)
	136	continue;
	137	chip->phy_addr = pa;
	138	break;
	139	}
	140	if (pa >= 32) {
	141	puts("ftmac110: phy device not found!\n");
	142	goto exit;
	143	}
	144
	145	/* 2. wait until link-up & auto-negotiation complete */
	146	chip->lnkup = 0;
	147	bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
	148	ts = get_timer(0);
	149	do {
	150	bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
	151	chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
	152	if (!chip->lnkup)
	153	continue;
	154	if (!(bmcr & BMCR_ANENABLE) \|\| (bmsr & BMSR_ANEGCOMPLETE))
	155	break;
	156	} while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
	157	if (!chip->lnkup) {
	158	puts("ftmac110: link down\n");
	159	goto exit;
	160	}
	161	if (!(bmcr & BMCR_ANENABLE))
	162	puts("ftmac110: auto negotiation disabled\n");
	163	else if (!(bmsr & BMSR_ANEGCOMPLETE))
	164	puts("ftmac110: auto negotiation timeout\n");
	165
	166	/* 3. derive MACCR */
167	if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
168	tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
169	tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
170	if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
171	maccr = MACCR_100M \| MACCR_FD;
172	else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
173	maccr = MACCR_100M;
174	else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
175	maccr = MACCR_FD;
176	else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
177	maccr = 0;
178	} else {
179	if (bmcr & BMCR_SPEED100)
180	maccr = MACCR_100M;
181	else
182	maccr = 0;
183	if (bmcr & BMCR_FULLDPLX)
184	maccr \|= MACCR_FD;
185	}
186
187	exit:
188	printf("ftmac110: %d Mbps, %s\n",
189	(maccr & MACCR_100M) ? 100 : 10,
190	(maccr & MACCR_FD) ? "Full" : "half");
191	return maccr;
192	}
193
194	static int ftmac110_reset(struct eth_device *dev)
195	{
196	uint8_t *a;
197	uint32_t i, maccr;
198	struct ftmac110_chip *chip = dev->priv;
4b7be199	199	struct ftmac110_regs *regs = chip->regs;
c4775476 KJS	200
	201	/* 1. MAC reset */
	202	writel(MACCR_RESET, &regs->maccr);
	203	for (i = get_timer(0); get_timer(i) < 1000; ) {
	204	if (readl(&regs->maccr) & MACCR_RESET)
	205	continue;
	206	break;
	207	}
	208	if (readl(&regs->maccr) & MACCR_RESET) {
	209	printf("ftmac110: reset failed\n");
	210	return -ENXIO;
	211	}
	212
	213	/* 1-1. Init tx ring */
	214	for (i = 0; i < CFG_TXDES_NUM; ++i) {
	215	/* owned by SW */
0628cb26	216	chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
c4775476 KJS	217	}
	218	chip->txd_idx = 0;
	219
	220	/* 1-2. Init rx ring */
	221	for (i = 0; i < CFG_RXDES_NUM; ++i) {
	222	/* owned by HW */
0628cb26 KJS	223	chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
0628cb26 KJS	224	chip->rxd[i].ctrl \|= cpu_to_le64(FTMAC110_RXD_OWNER);
c4775476 KJS	225	}
	226	chip->rxd_idx = 0;
	227
	228	/* 2. PHY status query */
	229	maccr = ftmac110_phyqry(dev);
	230
	231	/* 3. Fix up the MACCR value */
	232	chip->maccr = maccr \| MACCR_CRCAPD \| MACCR_RXALL \| MACCR_RXRUNT
	233	\| MACCR_RXEN \| MACCR_TXEN \| MACCR_RXDMAEN \| MACCR_TXDMAEN;
	234
	235	/* 4. MAC address setup */
	236	a = dev->enetaddr;
	237	writel(a[1] \| (a[0] << 8), &regs->mac[0]);
	238	writel(a[5] \| (a[4] << 8) \| (a[3] << 16)
	239	\| (a[2] << 24), &regs->mac[1]);
	240
	241	/* 5. MAC registers setup */
	242	writel(chip->rxd_dma, &regs->rxba);
	243	writel(chip->txd_dma, &regs->txba);
	244	/* interrupt at each tx/rx */
	245	writel(ITC_DEFAULT, &regs->itc);
	246	/* no tx pool, rx poll = 1 normal cycle */
	247	writel(APTC_DEFAULT, &regs->aptc);
	248	/* rx threshold = [6/8 fifo, 2/8 fifo] */
	249	writel(DBLAC_DEFAULT, &regs->dblac);
	250	/* disable & clear all interrupt status */
	251	chip->imr = 0;
	252	writel(ISR_ALL, &regs->isr);
	253	writel(chip->imr, &regs->imr);
	254	/* enable mac */
	255	writel(chip->maccr, &regs->maccr);
	256
	257	return 0;
	258	}
	259
b75d8dc5	260	static int ftmac110_probe(struct eth_device dev, struct bd_info bis)
c4775476 KJS	261	{
	262	debug("ftmac110: probe\n");
	263
	264	if (ftmac110_reset(dev))
	265	return -1;
	266
	267	return 0;
	268	}
	269
	270	static void ftmac110_halt(struct eth_device *dev)
	271	{
	272	struct ftmac110_chip *chip = dev->priv;
4b7be199	273	struct ftmac110_regs *regs = chip->regs;
c4775476 KJS	274
	275	writel(0, &regs->imr);
	276	writel(0, &regs->maccr);
	277
	278	debug("ftmac110: halt\n");
	279	}
	280
	281	static int ftmac110_send(struct eth_device dev, void pkt, int len)
	282	{
	283	struct ftmac110_chip *chip = dev->priv;
4b7be199	284	struct ftmac110_regs *regs = chip->regs;
0628cb26 KJS	285	struct ftmac110_desc *txd;
0628cb26 KJS	286	uint64_t ctrl;
c4775476 KJS	287
	288	if (!chip->lnkup)
	289	return 0;
	290
	291	if (len <= 0 \|\| len > CFG_XBUF_SIZE) {
	292	printf("ftmac110: bad tx pkt len(%d)\n", len);
	293	return 0;
	294	}
	295
	296	len = max(60, len);
	297
0628cb26 KJS	298	txd = &chip->txd[chip->txd_idx];
	299	ctrl = le64_to_cpu(txd->ctrl);
	300	if (ctrl & FTMAC110_TXD_OWNER) {
c4775476 KJS	301	/* kick-off Tx DMA */
	302	writel(0xffffffff, &regs->txpd);
	303	printf("ftmac110: out of txd\n");
	304	return 0;
	305	}
	306
0628cb26 KJS	307	memcpy(txd->vbuf, (void *)pkt, len);
0628cb26 KJS	308	dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
c4775476	309
0628cb26 KJS	310	/* clear control bits */
	311	ctrl &= FTMAC110_TXD_CLRMASK;
	312	/* set len, fts and lts */
	313	ctrl \|= FTMAC110_TXD_LEN(len) \| FTMAC110_TXD_FTS \| FTMAC110_TXD_LTS;
	314	/* set owner bit */
	315	ctrl \|= FTMAC110_TXD_OWNER;
	316	/* write back to descriptor */
	317	txd->ctrl = cpu_to_le64(ctrl);
c4775476 KJS	318
	319	/* kick-off Tx DMA */
	320	writel(0xffffffff, &regs->txpd);
	321
	322	chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
	323
	324	return len;
	325	}
	326
	327	static int ftmac110_recv(struct eth_device *dev)
	328	{
	329	struct ftmac110_chip *chip = dev->priv;
0628cb26 KJS	330	struct ftmac110_desc *rxd;
	331	uint32_t len, rlen = 0;
	332	uint64_t ctrl;
c4775476 KJS	333	uint8_t *buf;
	334
	335	if (!chip->lnkup)
	336	return 0;
	337
	338	do {
0628cb26 KJS	339	rxd = &chip->rxd[chip->rxd_idx];
	340	ctrl = le64_to_cpu(rxd->ctrl);
	341	if (ctrl & FTMAC110_RXD_OWNER)
c4775476 KJS	342	break;
c4775476 KJS	343
0628cb26 KJS	344	len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
0628cb26 KJS	345	buf = rxd->vbuf;
c4775476	346
0628cb26	347	if (ctrl & FTMAC110_RXD_ERRMASK) {
c4775476 KJS	348	printf("ftmac110: rx error\n");
	349	} else {
	350	dma_map_single(buf, len, DMA_FROM_DEVICE);
1fd92db8	351	net_process_received_packet(buf, len);
c4775476 KJS	352	rlen += len;
	353	}
	354
	355	/* owned by hardware */
0628cb26 KJS	356	ctrl &= FTMAC110_RXD_CLRMASK;
	357	ctrl \|= FTMAC110_RXD_OWNER;
	358	rxd->ctrl \|= cpu_to_le64(ctrl);
c4775476 KJS	359
	360	chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
	361	} while (0);
	362
	363	return rlen;
	364	}
	365
	366	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	367
5a49f174 JH	368	static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
5a49f174 JH	369	int reg)
c4775476	370	{
5a49f174	371	uint16_t value = 0;
c4775476 KJS	372	int ret = 0;
	373	struct eth_device *dev;
	374
5a49f174	375	dev = eth_get_dev_by_name(bus->name);
c4775476	376	if (dev == NULL) {
5a49f174	377	printf("%s: no such device\n", bus->name);
c4775476 KJS	378	ret = -1;
c4775476 KJS	379	} else {
5a49f174	380	value = mdio_read(dev, addr, reg);
c4775476 KJS	381	}
c4775476 KJS	382
5a49f174 JH	383	if (ret < 0)
	384	return ret;
	385	return value;
c4775476 KJS	386	}
c4775476 KJS	387
5a49f174 JH	388	static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
5a49f174 JH	389	int reg, u16 value)
c4775476 KJS	390	{
	391	int ret = 0;
	392	struct eth_device *dev;
	393
5a49f174	394	dev = eth_get_dev_by_name(bus->name);
c4775476	395	if (dev == NULL) {
5a49f174	396	printf("%s: no such device\n", bus->name);
c4775476 KJS	397	ret = -1;
	398	} else {
	399	mdio_write(dev, addr, reg, value);
	400	}
	401
	402	return ret;
	403	}
	404
	405	#endif /* #if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) */
	406
b75d8dc5	407	int ftmac110_initialize(struct bd_info *bis)
c4775476 KJS	408	{
	409	int i, card_nr = 0;
	410	struct eth_device *dev;
	411	struct ftmac110_chip *chip;
	412
	413	dev = malloc(sizeof(dev) + sizeof(chip));
	414	if (dev == NULL) {
	415	panic("ftmac110: out of memory 1\n");
	416	return -1;
	417	}
	418	chip = (struct ftmac110_chip *)(dev + 1);
	419	memset(dev, 0, sizeof(dev) + sizeof(chip));
	420
	421	sprintf(dev->name, "FTMAC110#%d", card_nr);
	422
	423	dev->iobase = CONFIG_FTMAC110_BASE;
	424	chip->regs = (void __iomem *)dev->iobase;
	425	dev->priv = chip;
	426	dev->init = ftmac110_probe;
	427	dev->halt = ftmac110_halt;
	428	dev->send = ftmac110_send;
	429	dev->recv = ftmac110_recv;
	430
c4775476 KJS	431	/* allocate tx descriptors (it must be 16 bytes aligned) */
c4775476 KJS	432	chip->txd = dma_alloc_coherent(
0628cb26	433	sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
c4775476 KJS	434	if (!chip->txd)
	435	panic("ftmac110: out of memory 3\n");
	436	memset(chip->txd, 0,
0628cb26	437	sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
c4775476 KJS	438	for (i = 0; i < CFG_TXDES_NUM; ++i) {
c4775476 KJS	439	void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
0628cb26	440
c4775476 KJS	441	if (!va)
c4775476 KJS	442	panic("ftmac110: out of memory 4\n");
0628cb26 KJS	443	chip->txd[i].vbuf = va;
	444	chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
	445	chip->txd[i].ctrl = 0; /* owned by SW */
c4775476	446	}
0628cb26	447	chip->txd[i - 1].ctrl \|= cpu_to_le64(FTMAC110_TXD_END);
c4775476 KJS	448	chip->txd_idx = 0;
	449
	450	/* allocate rx descriptors (it must be 16 bytes aligned) */
	451	chip->rxd = dma_alloc_coherent(
0628cb26	452	sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
c4775476 KJS	453	if (!chip->rxd)
	454	panic("ftmac110: out of memory 4\n");
	455	memset((void *)chip->rxd, 0,
0628cb26	456	sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
c4775476 KJS	457	for (i = 0; i < CFG_RXDES_NUM; ++i) {
c4775476 KJS	458	void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
0628cb26	459
c4775476 KJS	460	if (!va)
	461	panic("ftmac110: out of memory 5\n");
	462	/* it needs to be exactly 2 bytes aligned */
	463	va = ((uint8_t *)va + 2);
0628cb26 KJS	464	chip->rxd[i].vbuf = va;
	465	chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
	466	chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
	467	\| FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
c4775476	468	}
0628cb26	469	chip->rxd[i - 1].ctrl \|= cpu_to_le64(FTMAC110_RXD_END);
c4775476 KJS	470	chip->rxd_idx = 0;
	471
	472	eth_register(dev);
	473
	474	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
5a49f174 JH	475	int retval;
	476	struct mii_dev *mdiodev = mdio_alloc();
	477	if (!mdiodev)
	478	return -ENOMEM;
1a5d3e9a	479	strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
5a49f174 JH	480	mdiodev->read = ftmac110_mdio_read;
	481	mdiodev->write = ftmac110_mdio_write;
	482
	483	retval = mdio_register(mdiodev);
	484	if (retval < 0)
	485	return retval;
c4775476 KJS	486	#endif
	487
	488	card_nr++;
	489
	490	return card_nr;
	491	}