projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 728ece34 | 1 | /* |
| 7c57f3e8 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
| 728ece34 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 728ece34 PA |
5 | */ |
| 6 | ||
| 7 | /* | |
| 8 | * P1 P2 RDB board configuration file | |
| 9 | * This file is intended to address a set of Low End and Ultra Low End | |
| 10 | * Freescale SOCs of QorIQ series(RDB platforms). | |
| 11 | * Currently only P2020RDB | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __CONFIG_H | |
| 15 | #define __CONFIG_H | |
| 16 | ||
| e0082f7c PA |
17 | #ifdef CONFIG_36BIT |
| 18 | #define CONFIG_PHYS_64BIT | |
| 19 | #endif | |
| 20 | ||
| d24f2d32 | 21 | #ifdef CONFIG_P1011RDB |
| 62ca21c4 | 22 | #define CONFIG_P1011 |
| bc2d40ca | 23 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 62ca21c4 | 24 | #endif |
| d24f2d32 | 25 | #ifdef CONFIG_P1020RDB |
| 62ca21c4 | 26 | #define CONFIG_P1020 |
| bc2d40ca | 27 | #define CONFIG_SYS_L2_SIZE (256 << 10) |
| 62ca21c4 | 28 | #endif |
| d24f2d32 | 29 | #ifdef CONFIG_P2010RDB |
| 62ca21c4 | 30 | #define CONFIG_P2010 |
| bc2d40ca | 31 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 62ca21c4 | 32 | #endif |
| d24f2d32 | 33 | #ifdef CONFIG_P2020RDB |
| 62ca21c4 | 34 | #define CONFIG_P2020 |
| bc2d40ca | 35 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| f7780ec9 DD |
36 | #endif |
| 37 | ||
| d24f2d32 | 38 | #ifdef CONFIG_SDCARD |
| 4ce99570 | 39 | #define CONFIG_SPL 1 |
| bc2d40ca PK |
40 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
| 41 | #define CONFIG_SPL_ENV_SUPPORT | |
| 42 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 43 | #define CONFIG_SPL_MMC_SUPPORT | |
| 44 | #define CONFIG_SPL_MMC_MINIMAL | |
| 45 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 46 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 47 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 48 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 49 | #define CONFIG_SPL_I2C_SUPPORT | |
| 50 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
| 51 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
| 52 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 53 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
| 54 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) | |
| 55 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
| 56 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
| 57 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (129 << 10) | |
| 58 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 59 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 60 | #define CONFIG_SPL_MMC_BOOT | |
| 61 | #ifdef CONFIG_SPL_BUILD | |
| 62 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 63 | #endif | |
| fad15096 DD |
64 | #endif |
| 65 | ||
| d24f2d32 | 66 | #ifdef CONFIG_SPIFLASH |
| 4ce99570 | 67 | #define CONFIG_SPL 1 |
| bc2d40ca PK |
68 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT |
| 69 | #define CONFIG_SPL_ENV_SUPPORT | |
| 70 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 71 | #define CONFIG_SPL_SPI_SUPPORT | |
| 72 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
| 73 | #define CONFIG_SPL_SPI_FLASH_MINIMAL | |
| 74 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 75 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 76 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 77 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 78 | #define CONFIG_SPL_I2C_SUPPORT | |
| 79 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
| 80 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
| 81 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 82 | #define CONFIG_SPL_MAX_SIZE (128 * 1024) | |
| 83 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) | |
| 84 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
| 85 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
| 86 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) | |
| 87 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 88 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
| 89 | #define CONFIG_SPL_SPI_BOOT | |
| 90 | #ifdef CONFIG_SPL_BUILD | |
| 91 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 92 | #endif | |
| 93 | #endif | |
| 94 | ||
| 95 | #ifdef CONFIG_NAND | |
| 4ce99570 MY |
96 | #define CONFIG_SPL 1 |
| 97 | #define CONFIG_TPL 1 | |
| bc2d40ca PK |
98 | #ifdef CONFIG_TPL_BUILD |
| 99 | #define CONFIG_SPL_NAND_BOOT | |
| 100 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 101 | #define CONFIG_SPL_ENV_SUPPORT | |
| 102 | #define CONFIG_SPL_NAND_INIT | |
| 103 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 104 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
| 105 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
| 106 | #define CONFIG_SPL_I2C_SUPPORT | |
| 107 | #define CONFIG_SPL_NAND_SUPPORT | |
| 108 | #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT | |
| 109 | #define CONFIG_SPL_COMMON_INIT_DDR | |
| 110 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
| 111 | #define CONFIG_SPL_TEXT_BASE 0xf8f81000 | |
| 112 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
| 113 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) | |
| 114 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
| 115 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
| 116 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
| 117 | #elif defined(CONFIG_SPL_BUILD) | |
| 118 | #define CONFIG_SPL_INIT_MINIMAL | |
| 119 | #define CONFIG_SPL_SERIAL_SUPPORT | |
| 120 | #define CONFIG_SPL_NAND_SUPPORT | |
| 121 | #define CONFIG_SPL_FLUSH_IMAGE | |
| 122 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 123 | #define CONFIG_SPL_TEXT_BASE 0xff800000 | |
| 124 | #define CONFIG_SPL_MAX_SIZE 4096 | |
| 125 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
| 126 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 | |
| 127 | #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 | |
| 128 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
| 129 | #endif /* not CONFIG_TPL_BUILD */ | |
| 130 | ||
| 131 | #define CONFIG_SPL_PAD_TO 0x20000 | |
| 132 | #define CONFIG_TPL_PAD_TO 0x20000 | |
| 133 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
| 134 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
| 135 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
| 2ae18241 WD |
136 | #endif |
| 137 | ||
| 138 | #ifndef CONFIG_SYS_TEXT_BASE | |
| e222b1f3 | 139 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
| fad15096 DD |
140 | #endif |
| 141 | ||
| 7a577fda KG |
142 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 143 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
| 144 | #endif | |
| 145 | ||
| 96196a1f | 146 | #ifndef CONFIG_SYS_MONITOR_BASE |
| bc2d40ca PK |
147 | #ifdef CONFIG_SPL_BUILD |
| 148 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
| 149 | #else | |
| 96196a1f HW |
150 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 151 | #endif | |
| bc2d40ca | 152 | #endif |
| 96196a1f | 153 | |
| 728ece34 PA |
154 | /* High Level Configuration Options */ |
| 155 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 156 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 728ece34 | 157 | #define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */ |
| b7070904 | 158 | |
| 33f3f342 | 159 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| b7070904 | 160 | #if defined(CONFIG_PCI) |
| 33f3f342 PA |
161 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 162 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 163 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 842033e6 | 164 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
| 33f3f342 PA |
165 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 166 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
| b7070904 | 167 | #endif /* #if defined(CONFIG_PCI) */ |
| 728ece34 PA |
168 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 169 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 170 | #define CONFIG_ENV_OVERWRITE | |
| 171 | ||
| b7070904 | 172 | #if defined(CONFIG_PCI) |
| ddac6f08 | 173 | #define CONFIG_E1000 1 /* E1000 pci Ethernet card*/ |
| b7070904 PK |
174 | #endif |
| 175 | ||
| 728ece34 PA |
176 | #ifndef __ASSEMBLY__ |
| 177 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 178 | #endif | |
| 179 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */ | |
| 180 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */ | |
| 181 | ||
| 182 | #if defined(CONFIG_P2020) || defined(CONFIG_P1020) | |
| 183 | #define CONFIG_MP | |
| 184 | #endif | |
| 185 | ||
| 525f6c3a PA |
186 | #define CONFIG_HWCONFIG |
| 187 | ||
| 728ece34 PA |
188 | /* |
| 189 | * These can be toggled for performance analysis, otherwise use default. | |
| 190 | */ | |
| 191 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 192 | #define CONFIG_BTB /* toggle branch predition */ | |
| 193 | ||
| 194 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
| 195 | ||
| 196 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 197 | ||
| e0082f7c PA |
198 | #ifdef CONFIG_PHYS_64BIT |
| 199 | #define CONFIG_ADDR_MAP 1 | |
| 200 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 201 | #endif | |
| 202 | ||
| 728ece34 PA |
203 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 204 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
| 205 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
| 206 | ||
| bc2d40ca PK |
207 | /* |
| 208 | * Config the L2 Cache as L2 SRAM | |
| 209 | */ | |
| 210 | #if defined(CONFIG_SPL_BUILD) | |
| 211 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
| f7780ec9 | 212 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| bc2d40ca PK |
213 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 214 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 215 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
| 216 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
| 217 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) | |
| 218 | #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) | |
| 219 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) | |
| 220 | #if defined(CONFIG_P2020RDB) | |
| 221 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) | |
| 222 | #else | |
| 223 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) | |
| 224 | #endif | |
| 225 | #elif defined(CONFIG_NAND) | |
| 226 | #ifdef CONFIG_TPL_BUILD | |
| 227 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 228 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 229 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 230 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 | |
| 231 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
| 232 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
| 233 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
| 234 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
| f7780ec9 | 235 | #else |
| bc2d40ca | 236 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| f7780ec9 | 237 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| bc2d40ca PK |
238 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 239 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 240 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 241 | #endif /* CONFIG_TPL_BUILD */ | |
| 242 | #endif | |
| f7780ec9 | 243 | #endif |
| f7780ec9 | 244 | |
| bc2d40ca | 245 | #ifdef CONFIG_SPL_BUILD |
| e46fedfe | 246 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
| f7780ec9 DD |
247 | #endif |
| 248 | ||
| 728ece34 | 249 | /* DDR Setup */ |
| 5614e71b | 250 | #define CONFIG_SYS_FSL_DDR2 |
| 728ece34 PA |
251 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 252 | #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 728ece34 PA |
253 | |
| 254 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 255 | ||
| bc2d40ca PK |
256 | #if defined(CONFIG_P1011RDB) || defined(CONFIG_P1020RDB) |
| 257 | /* | |
| 258 | * P1020 and it's derivatives support max 32bit DDR width | |
| 259 | * So Reduce available DDR size | |
| 260 | */ | |
| 261 | #define CONFIG_SYS_SDRAM_SIZE 512 | |
| 262 | #else | |
| 263 | #define CONFIG_SYS_SDRAM_SIZE 1024 | |
| 264 | #endif | |
| 728ece34 PA |
265 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 266 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 267 | ||
| 268 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 269 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 270 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
| 271 | ||
| 272 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 273 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 274 | #define CONFIG_SYS_DDR_SBE 0x00FF0000 | |
| 275 | ||
| 728ece34 PA |
276 | /* |
| 277 | * Memory map | |
| 278 | * | |
| 279 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen | |
| b0c5ceb3 PK |
280 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 281 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
| 728ece34 PA |
282 | * |
| 283 | * Localbus cacheable (TBD) | |
| 284 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 285 | * | |
| 286 | * Localbus non-cacheable | |
| 287 | * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable | |
| 288 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable | |
| 289 | * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable | |
| 290 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 291 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 292 | */ | |
| 293 | ||
| 294 | /* | |
| 295 | * Local Bus Definitions | |
| 296 | */ | |
| 297 | #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ | |
| 298 | ||
| e0082f7c PA |
299 | #ifdef CONFIG_PHYS_64BIT |
| 300 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull | |
| 301 | #else | |
| 728ece34 | 302 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| e0082f7c | 303 | #endif |
| 728ece34 PA |
304 | |
| 305 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
| 306 | BR_PS_16 | BR_V) | |
| 307 | #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 | |
| 308 | ||
| e0082f7c | 309 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| 728ece34 PA |
310 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 311 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
| 312 | ||
| 313 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 314 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
| 315 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 316 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 317 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 318 | ||
| 728ece34 PA |
319 | #define CONFIG_FLASH_CFI_DRIVER |
| 320 | #define CONFIG_SYS_FLASH_CFI | |
| 321 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 322 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 323 | ||
| 324 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 2bad42a0 | 325 | #define CONFIG_MISC_INIT_R |
| 66e821eb | 326 | #define CONFIG_HWCONFIG |
| 728ece34 PA |
327 | |
| 328 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
| 329 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
| e0082f7c PA |
330 | #ifdef CONFIG_PHYS_64BIT |
| 331 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
| 332 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
| 333 | /* The assembler doesn't like typecast */ | |
| 334 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
| 335 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
| 336 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
| 337 | #else | |
| 338 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
| 339 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
| 340 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
| 341 | #endif | |
| 553f0982 | 342 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
| 728ece34 | 343 | |
| 553f0982 | 344 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
| 25ddd1fb | 345 | - GENERATED_GBL_DATA_SIZE) |
| 728ece34 PA |
346 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 347 | ||
| 9307cbab | 348 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
| 728ece34 PA |
349 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
| 350 | ||
| bc2d40ca | 351 | #define CONFIG_SYS_NAND_BASE 0xff800000 |
| e0082f7c | 352 | #ifdef CONFIG_PHYS_64BIT |
| bc2d40ca | 353 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull |
| f7780ec9 | 354 | #else |
| e0082f7c | 355 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| f7780ec9 | 356 | #endif |
| e0082f7c | 357 | |
| 6bbb3e93 | 358 | #define CONFIG_CMD_NAND |
| 728ece34 PA |
359 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} |
| 360 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
| 728ece34 | 361 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 728ece34 PA |
362 | #define CONFIG_NAND_FSL_ELBC 1 |
| 363 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
| 364 | ||
| 365 | /* NAND flash config */ | |
| a3055c58 | 366 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 728ece34 PA |
367 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 368 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 369 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 370 | | BR_V) /* valid */ | |
| 371 | ||
| a3055c58 | 372 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \ |
| 728ece34 PA |
373 | | OR_FCM_CSCT \ |
| 374 | | OR_FCM_CST \ | |
| 375 | | OR_FCM_CHT \ | |
| 376 | | OR_FCM_SCY_1 \ | |
| 377 | | OR_FCM_TRLX \ | |
| 378 | | OR_FCM_EHTR) | |
| 379 | ||
| bc2d40ca | 380 | #ifdef CONFIG_NAND |
| a3055c58 MM |
381 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 382 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| f7780ec9 DD |
383 | #define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 384 | #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 385 | #else | |
| 728ece34 PA |
386 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 387 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| a3055c58 MM |
388 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 389 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
| f7780ec9 | 390 | #endif |
| 728ece34 PA |
391 | |
| 392 | #define CONFIG_SYS_VSC7385_BASE 0xffb00000 | |
| 393 | ||
| e0082f7c PA |
394 | #ifdef CONFIG_PHYS_64BIT |
| 395 | #define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull | |
| 396 | #else | |
| 728ece34 | 397 | #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE |
| e0082f7c | 398 | #endif |
| 728ece34 | 399 | |
| 09f9ee16 PA |
400 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ |
| 401 | | BR_PS_8 | BR_V) | |
| 728ece34 PA |
402 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ |
| 403 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ | |
| 404 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
| 405 | ||
| 406 | /* Serial Port - controlled on board with jumper J8 | |
| 407 | * open - index 2 | |
| 408 | * shorted - index 1 | |
| 409 | */ | |
| 410 | #define CONFIG_CONS_INDEX 1 | |
| 728ece34 PA |
411 | #define CONFIG_SYS_NS16550 |
| 412 | #define CONFIG_SYS_NS16550_SERIAL | |
| 413 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 414 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| bc2d40ca | 415 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
| 93341909 KG |
416 | #define CONFIG_NS16550_MIN_FUNCTIONS |
| 417 | #endif | |
| 728ece34 | 418 | |
| 728ece34 PA |
419 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
| 420 | ||
| 421 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
| 422 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 423 | ||
| 424 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
| 425 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| 426 | ||
| 427 | /* Use the HUSH parser */ | |
| 428 | #define CONFIG_SYS_HUSH_PARSER | |
| 728ece34 PA |
429 | |
| 430 | /* | |
| 431 | * Pass open firmware flat tree | |
| 432 | */ | |
| 433 | #define CONFIG_OF_LIBFDT 1 | |
| 434 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 435 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 436 | ||
| 728ece34 PA |
437 | /* new uImage format support */ |
| 438 | #define CONFIG_FIT 1 | |
| 439 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
| 440 | ||
| 441 | /* I2C */ | |
| 00f792e0 HS |
442 | #define CONFIG_SYS_I2C |
| 443 | #define CONFIG_SYS_I2C_FSL | |
| 444 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 445 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 446 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 447 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 448 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 449 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 450 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
| 728ece34 PA |
451 | |
| 452 | /* | |
| 453 | * I2C2 EEPROM | |
| 454 | */ | |
| 455 | #define CONFIG_ID_EEPROM | |
| 456 | #ifdef CONFIG_ID_EEPROM | |
| 457 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
| 458 | #endif | |
| b1d67857 | 459 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
| 728ece34 PA |
460 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 461 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 462 | ||
| cac29f25 PJ |
463 | #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 |
| 464 | ||
| 728ece34 | 465 | #define CONFIG_RTC_DS1337 |
| 39c2a6eb | 466 | #define CONFIG_SYS_RTC_DS1337_NOOSC |
| 728ece34 | 467 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| c62a6cfb PJ |
468 | |
| 469 | /* eSPI - Enhanced SPI */ | |
| 470 | #define CONFIG_FSL_ESPI | |
| 471 | #define CONFIG_SPI_FLASH | |
| 472 | #define CONFIG_SPI_FLASH_SPANSION | |
| 473 | #define CONFIG_CMD_SF | |
| 474 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
| 475 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
| 476 | ||
| 728ece34 PA |
477 | /* |
| 478 | * General PCI | |
| 479 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 480 | */ | |
| 481 | ||
| b7070904 | 482 | #if defined(CONFIG_PCI) |
| b0c5ceb3 | 483 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ |
| 06eb4d8c | 484 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
| 728ece34 | 485 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| e0082f7c PA |
486 | #ifdef CONFIG_PHYS_64BIT |
| 487 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
| 488 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
| 489 | #else | |
| 728ece34 PA |
490 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 491 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
| e0082f7c | 492 | #endif |
| 728ece34 | 493 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| b0c5ceb3 PK |
494 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 495 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| e0082f7c PA |
496 | #ifdef CONFIG_PHYS_64BIT |
| 497 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
| 498 | #else | |
| b0c5ceb3 | 499 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| e0082f7c | 500 | #endif |
| 728ece34 PA |
501 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 502 | ||
| 503 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 06eb4d8c | 504 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
| b0c5ceb3 | 505 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| e0082f7c PA |
506 | #ifdef CONFIG_PHYS_64BIT |
| 507 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
| 508 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
| 509 | #else | |
| b0c5ceb3 PK |
510 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 511 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
| e0082f7c | 512 | #endif |
| 728ece34 | 513 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| b0c5ceb3 PK |
514 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
| 515 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| e0082f7c PA |
516 | #ifdef CONFIG_PHYS_64BIT |
| 517 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
| 518 | #else | |
| b0c5ceb3 | 519 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 |
| e0082f7c | 520 | #endif |
| 728ece34 PA |
521 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 522 | ||
| 728ece34 PA |
523 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 524 | ||
| 525 | #undef CONFIG_EEPRO100 | |
| 526 | #undef CONFIG_TULIP | |
| 527 | #undef CONFIG_RTL8139 | |
| 528 | ||
| 529 | #ifdef CONFIG_RTL8139 | |
| 530 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
| 531 | #define KSEG1ADDR(x) (x) | |
| 532 | #define _IO_BASE 0x00000000 | |
| 533 | #endif | |
| 534 | ||
| 535 | ||
| 536 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 537 | #define CONFIG_DOS_PARTITION | |
| 538 | ||
| 539 | #endif /* CONFIG_PCI */ | |
| 540 | ||
| 728ece34 | 541 | |
| b7070904 | 542 | #if defined(CONFIG_TSEC_ENET) |
| 728ece34 PA |
543 | #define CONFIG_MII 1 /* MII PHY management */ |
| 544 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 545 | #define CONFIG_TSEC1 1 | |
| 546 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 547 | #define CONFIG_TSEC2 1 | |
| 548 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 549 | #define CONFIG_TSEC3 1 | |
| 550 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 551 | ||
| 552 | #define TSEC1_PHY_ADDR 2 | |
| 553 | #define TSEC2_PHY_ADDR 0 | |
| 554 | #define TSEC3_PHY_ADDR 1 | |
| 555 | ||
| 556 | #define CONFIG_VSC7385_ENET | |
| 557 | ||
| 558 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 559 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 560 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 561 | ||
| 562 | #define TSEC1_PHYIDX 0 | |
| 563 | #define TSEC2_PHYIDX 0 | |
| 564 | #define TSEC3_PHYIDX 0 | |
| 565 | ||
| 566 | /* Vitesse 7385 */ | |
| 567 | ||
| 568 | #ifdef CONFIG_VSC7385_ENET | |
| 569 | /* The size of the VSC7385 firmware image */ | |
| 570 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
| 571 | #endif | |
| 572 | ||
| 573 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 574 | ||
| 575 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 90b5bf21 | 576 | |
| 728ece34 PA |
577 | #endif /* CONFIG_TSEC_ENET */ |
| 578 | ||
| 579 | /* | |
| 580 | * Environment | |
| 581 | */ | |
| bc2d40ca PK |
582 | #ifdef CONFIG_SPIFLASH |
| 583 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
| 584 | #define CONFIG_ENV_SPI_BUS 0 | |
| 585 | #define CONFIG_ENV_SPI_CS 0 | |
| 586 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
| 587 | #define CONFIG_ENV_SPI_MODE 0 | |
| 588 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
| 589 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
| 590 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 591 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
| 592 | #elif defined(CONFIG_SDCARD) | |
| e59a93e7 | 593 | #define CONFIG_ENV_IS_IN_MMC |
| 4394d0c2 | 594 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
| bc2d40ca PK |
595 | #define CONFIG_ENV_SIZE 0x2000 |
| 596 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
| 597 | #define CONFIG_ENV_OFFSET (512 * 0x800) | |
| 598 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
| 599 | #elif defined(CONFIG_NAND) | |
| 600 | #ifdef CONFIG_TPL_BUILD | |
| 601 | #define CONFIG_ENV_SIZE 0x2000 | |
| 602 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
| 728ece34 | 603 | #else |
| bc2d40ca PK |
604 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
| 605 | #endif | |
| 606 | #define CONFIG_ENV_IS_IN_NAND | |
| 607 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
| 608 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) | |
| 609 | #elif defined(CONFIG_SYS_RAMBOOT) | |
| 610 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ | |
| 611 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 612 | #define CONFIG_ENV_SIZE 0x2000 | |
| 613 | #else | |
| 614 | #define CONFIG_ENV_IS_IN_FLASH | |
| 615 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 616 | #define CONFIG_ENV_SIZE 0x2000 | |
| 617 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 728ece34 | 618 | #endif |
| 728ece34 | 619 | |
| bc2d40ca | 620 | |
| 728ece34 PA |
621 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 622 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 623 | ||
| 624 | /* | |
| 625 | * Command line configuration. | |
| 626 | */ | |
| 627 | #include <config_cmd_default.h> | |
| 628 | ||
| 629 | #define CONFIG_CMD_DATE | |
| 630 | #define CONFIG_CMD_ELF | |
| 631 | #define CONFIG_CMD_I2C | |
| 632 | #define CONFIG_CMD_IRQ | |
| 633 | #define CONFIG_CMD_MII | |
| 634 | #define CONFIG_CMD_PING | |
| 635 | #define CONFIG_CMD_SETEXPR | |
| 199e262e | 636 | #define CONFIG_CMD_REGINFO |
| 728ece34 PA |
637 | |
| 638 | #if defined(CONFIG_PCI) | |
| 728ece34 PA |
639 | #define CONFIG_CMD_NET |
| 640 | #define CONFIG_CMD_PCI | |
| 641 | #endif | |
| 642 | ||
| 643 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 644 | ||
| 645 | #define CONFIG_MMC 1 | |
| 646 | ||
| 647 | #ifdef CONFIG_MMC | |
| 648 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 649 | #define CONFIG_CMD_MMC | |
| 650 | #define CONFIG_DOS_PARTITION | |
| 651 | #define CONFIG_FSL_ESDHC | |
| 652 | #define CONFIG_GENERIC_MMC | |
| 653 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 654 | #ifdef CONFIG_P2020 | |
| 655 | #define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/ | |
| 656 | #endif | |
| 657 | #endif | |
| 658 | ||
| 1120ad60 RM |
659 | #define CONFIG_HAS_FSL_DR_USB |
| 660 | ||
| 661 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
| 728ece34 PA |
662 | #define CONFIG_USB_EHCI |
| 663 | ||
| 664 | #ifdef CONFIG_USB_EHCI | |
| 665 | #define CONFIG_CMD_USB | |
| 666 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
| 667 | #define CONFIG_USB_EHCI_FSL | |
| 668 | #define CONFIG_USB_STORAGE | |
| 1120ad60 | 669 | #endif |
| 728ece34 PA |
670 | #endif |
| 671 | ||
| 672 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) | |
| 673 | #define CONFIG_CMD_EXT2 | |
| 674 | #define CONFIG_CMD_FAT | |
| 675 | #define CONFIG_DOS_PARTITION | |
| 676 | #endif | |
| 677 | ||
| 678 | /* | |
| 679 | * Miscellaneous configurable options | |
| 680 | */ | |
| 681 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 682 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
| 5be58f5f | 683 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 728ece34 | 684 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 728ece34 PA |
685 | #if defined(CONFIG_CMD_KGDB) |
| 686 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 687 | #else | |
| 688 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 689 | #endif | |
| 690 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 691 | /* Print Buffer Size */ | |
| 692 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 693 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
| 728ece34 PA |
694 | |
| 695 | /* | |
| 696 | * For booting Linux, the board info and command line data | |
| a832ac41 | 697 | * have to be in the first 64 MB of memory, since this is |
| 728ece34 PA |
698 | * the maximum mapped by the Linux kernel during initialization. |
| 699 | */ | |
| a832ac41 KG |
700 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20)/* Initial Memory map for Linux*/ |
| 701 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
| 728ece34 | 702 | |
| 728ece34 PA |
703 | #if defined(CONFIG_CMD_KGDB) |
| 704 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 728ece34 PA |
705 | #endif |
| 706 | ||
| 707 | /* | |
| 708 | * Environment Configuration | |
| 709 | */ | |
| 710 | ||
| 711 | #if defined(CONFIG_TSEC_ENET) | |
| 712 | #define CONFIG_HAS_ETH0 | |
| 713 | #define CONFIG_HAS_ETH1 | |
| 714 | #define CONFIG_HAS_ETH2 | |
| 715 | #endif | |
| 716 | ||
| 717 | #define CONFIG_HOSTNAME P2020RDB | |
| 8b3637c6 | 718 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 719 | #define CONFIG_BOOTFILE "uImage" |
| 728ece34 PA |
720 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
| 721 | ||
| 722 | /* default location for tftp and bootm */ | |
| 723 | #define CONFIG_LOADADDR 1000000 | |
| 724 | ||
| 725 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 726 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 727 | ||
| 728 | #define CONFIG_BAUDRATE 115200 | |
| 729 | ||
| 730 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 731 | "netdev=eth0\0" \ | |
| 5368c55d MV |
732 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 733 | "loadaddr=1000000\0" \ | |
| 728ece34 | 734 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 5368c55d MV |
735 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 736 | " +$filesize; " \ | |
| 737 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 738 | " +$filesize; " \ | |
| 739 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 740 | " $filesize; " \ | |
| 741 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 742 | " +$filesize; " \ | |
| 743 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 744 | " $filesize\0" \ | |
| 728ece34 PA |
745 | "consoledev=ttyS0\0" \ |
| 746 | "ramdiskaddr=2000000\0" \ | |
| 747 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
| 748 | "fdtaddr=c00000\0" \ | |
| 749 | "fdtfile=p2020rdb.dtb\0" \ | |
| 750 | "bdev=sda1\0" \ | |
| 751 | "jffs2nor=mtdblock3\0" \ | |
| 752 | "norbootaddr=ef080000\0" \ | |
| 753 | "norfdtaddr=ef040000\0" \ | |
| 754 | "jffs2nand=mtdblock9\0" \ | |
| 755 | "nandbootaddr=100000\0" \ | |
| 756 | "nandfdtaddr=80000\0" \ | |
| 757 | "nandimgsize=400000\0" \ | |
| 758 | "nandfdtsize=80000\0" \ | |
| 68d4230c | 759 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ |
| 728ece34 PA |
760 | "vscfw_addr=ef000000\0" \ |
| 761 | "othbootargs=ramdisk_size=600000\0" \ | |
| 762 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
| 763 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 764 | "usb start;" \ | |
| 765 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
| 766 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
| 767 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
| 768 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 769 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
| 770 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 771 | "usb start;" \ | |
| 772 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
| 773 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
| 774 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
| 775 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
| 776 | "norboot=setenv bootargs root=/dev/$jffs2nor rw " \ | |
| 777 | "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ | |
| 778 | "bootm $norbootaddr - $norfdtaddr\0" \ | |
| 779 | "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \ | |
| 780 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 781 | "nand read 2000000 $nandbootaddr $nandimgsize;" \ | |
| 782 | "nand read 3000000 $nandfdtaddr $nandfdtsize;" \ | |
| 783 | "bootm 2000000 - 3000000;\0" | |
| 784 | ||
| 785 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 786 | "setenv bootargs root=/dev/nfs rw " \ | |
| 787 | "nfsroot=$serverip:$rootpath " \ | |
| 788 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 789 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 790 | "tftp $loadaddr $bootfile;" \ | |
| 791 | "tftp $fdtaddr $fdtfile;" \ | |
| 792 | "bootm $loadaddr - $fdtaddr" | |
| 793 | ||
| 794 | #define CONFIG_HDBOOT \ | |
| 795 | "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ | |
| 796 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 797 | "usb start;" \ | |
| 798 | "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ | |
| 799 | "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ | |
| 800 | "bootm $loadaddr - $fdtaddr" | |
| 801 | ||
| 802 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 803 | "setenv bootargs root=/dev/ram rw " \ | |
| 804 | "console=$consoledev,$baudrate $othbootargs; " \ | |
| 805 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 806 | "tftp $loadaddr $bootfile;" \ | |
| 807 | "tftp $fdtaddr $fdtfile;" \ | |
| 808 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 809 | ||
| 810 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 811 | ||
| 812 | #endif /* __CONFIG_H */ |