[J-u-boot.git] / drivers / rtc / m48t35ax.c

/*
 * (C) Copyright 2001
 * Erik Theisen,  Wave 7 Optics, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Date & Time support for ST Electronics M48T35Ax RTC
 */

/*#define       DEBUG */


#include <common.h>
#include <command.h>
#include <rtc.h>
#include <config.h>

#if defined(CONFIG_CMD_DATE)

static uchar rtc_read  (uchar reg);
static void  rtc_write (uchar reg, uchar val);

/* ------------------------------------------------------------------------- */

int rtc_get (struct rtc_time *tmp)
{
	uchar sec, min, hour, cent_day, date, month, year;
	uchar ccr;			/* Clock control register */

	/* Lock RTC for read using clock control register */
	ccr = rtc_read(0);
	ccr = ccr | 0x40;
	rtc_write(0, ccr);

	sec	= rtc_read (0x1);
	min	= rtc_read (0x2);
	hour	= rtc_read (0x3);
	cent_day= rtc_read (0x4);
	date	= rtc_read (0x5);
	month   = rtc_read (0x6);
	year	= rtc_read (0x7);

	/* UNLock RTC */
	ccr = rtc_read(0);
	ccr = ccr & 0xBF;
	rtc_write(0, ccr);

	debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
		"hr: %02x min: %02x sec: %02x\n",
		year, month, date, cent_day,
		hour, min, sec );

	tmp->tm_sec  = bcd2bin (sec  & 0x7F);
	tmp->tm_min  = bcd2bin (min  & 0x7F);
	tmp->tm_hour = bcd2bin (hour & 0x3F);
	tmp->tm_mday = bcd2bin (date & 0x3F);
	tmp->tm_mon  = bcd2bin (month & 0x1F);
	tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
	tmp->tm_wday = bcd2bin (cent_day & 0x07);
	tmp->tm_yday = 0;
	tmp->tm_isdst= 0;

	debug ( "Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return 0;
}

int rtc_set (struct rtc_time *tmp)
{
	uchar ccr;			/* Clock control register */
	uchar century;

	debug ( "Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	/* Lock RTC for write using clock control register */
	ccr = rtc_read(0);
	ccr = ccr | 0x80;
	rtc_write(0, ccr);

	rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
	rtc_write (0x06, bin2bcd(tmp->tm_mon));
	rtc_write (0x05, bin2bcd(tmp->tm_mday));

	century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20;
	rtc_write (0x04, bin2bcd(tmp->tm_wday) | century);

	rtc_write (0x03, bin2bcd(tmp->tm_hour));
	rtc_write (0x02, bin2bcd(tmp->tm_min ));
	rtc_write (0x01, bin2bcd(tmp->tm_sec ));

	/* UNLock RTC */
	ccr = rtc_read(0);
	ccr = ccr & 0x7F;
	rtc_write(0, ccr);

	return 0;
}

void rtc_reset (void)
{
	uchar val;

	/* Clear all clock control registers */
	rtc_write (0x0, 0x80);		/* No Read Lock or calibration */

	/* Clear stop bit */
	val = rtc_read (0x1);
	val &= 0x7f;
	rtc_write(0x1, val);

	/* Enable century / disable frequency test */
	val = rtc_read (0x4);
	val = (val & 0xBF) | 0x20;
	rtc_write(0x4, val);

	/* Clear write lock */
	rtc_write(0x0, 0);
}

/* ------------------------------------------------------------------------- */

static uchar rtc_read (uchar reg)
{
	uchar val;
	val = *(unsigned char *)
		((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
	return val;
}

static void rtc_write (uchar reg, uchar val)
{
	*(unsigned char *)
		((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
}

#endif
Commit	Line	Data
affae2bf WD	1	/*
	2	* (C) Copyright 2001
	3	* Erik Theisen, Wave 7 Optics, [email protected].
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
affae2bf WD	6	*/
	7
	8	/*
	9	* Date & Time support for ST Electronics M48T35Ax RTC
	10	*/
	11
	12	/#define DEBUG /
	13
	14
	15	#include <common.h>
	16	#include <command.h>
	17	#include <rtc.h>
	18	#include <config.h>
	19
871c18dd	20	#if defined(CONFIG_CMD_DATE)
affae2bf WD	21
	22	static uchar rtc_read (uchar reg);
	23	static void rtc_write (uchar reg, uchar val);
affae2bf WD	24
	25	/* ------------------------------------------------------------------------- */
	26
b73a19e1	27	int rtc_get (struct rtc_time *tmp)
affae2bf WD	28	{
	29	uchar sec, min, hour, cent_day, date, month, year;
	30	uchar ccr; /* Clock control register */
	31
	32	/* Lock RTC for read using clock control register */
	33	ccr = rtc_read(0);
	34	ccr = ccr \| 0x40;
	35	rtc_write(0, ccr);
	36
	37	sec = rtc_read (0x1);
	38	min = rtc_read (0x2);
	39	hour = rtc_read (0x3);
	40	cent_day= rtc_read (0x4);
	41	date = rtc_read (0x5);
	42	month = rtc_read (0x6);
	43	year = rtc_read (0x7);
	44
	45	/* UNLock RTC */
	46	ccr = rtc_read(0);
	47	ccr = ccr & 0xBF;
	48	rtc_write(0, ccr);
	49
	50	debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
	51	"hr: %02x min: %02x sec: %02x\n",
	52	year, month, date, cent_day,
	53	hour, min, sec );
	54
	55	tmp->tm_sec = bcd2bin (sec & 0x7F);
	56	tmp->tm_min = bcd2bin (min & 0x7F);
	57	tmp->tm_hour = bcd2bin (hour & 0x3F);
	58	tmp->tm_mday = bcd2bin (date & 0x3F);
	59	tmp->tm_mon = bcd2bin (month & 0x1F);
	60	tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
	61	tmp->tm_wday = bcd2bin (cent_day & 0x07);
	62	tmp->tm_yday = 0;
	63	tmp->tm_isdst= 0;
	64
	65	debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	66	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	67	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
b73a19e1 YT	68
b73a19e1 YT	69	return 0;
affae2bf WD	70	}
affae2bf WD	71
d1e23194	72	int rtc_set (struct rtc_time *tmp)
affae2bf WD	73	{
	74	uchar ccr; /* Clock control register */
	75	uchar century;
	76
	77	debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	78	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	79	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
	80
	81	/* Lock RTC for write using clock control register */
	82	ccr = rtc_read(0);
	83	ccr = ccr \| 0x80;
	84	rtc_write(0, ccr);
	85
	86	rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
	87	rtc_write (0x06, bin2bcd(tmp->tm_mon));
	88	rtc_write (0x05, bin2bcd(tmp->tm_mday));
	89
	90	century = ((tmp->tm_year >= 2000) ? 0x10 : 0) \| 0x20;
	91	rtc_write (0x04, bin2bcd(tmp->tm_wday) \| century);
	92
	93	rtc_write (0x03, bin2bcd(tmp->tm_hour));
	94	rtc_write (0x02, bin2bcd(tmp->tm_min ));
	95	rtc_write (0x01, bin2bcd(tmp->tm_sec ));
	96
	97	/* UNLock RTC */
	98	ccr = rtc_read(0);
	99	ccr = ccr & 0x7F;
	100	rtc_write(0, ccr);
d1e23194 JCPV	101
d1e23194 JCPV	102	return 0;
affae2bf WD	103	}
	104
	105	void rtc_reset (void)
	106	{
	107	uchar val;
	108
	109	/* Clear all clock control registers */
	110	rtc_write (0x0, 0x80); /* No Read Lock or calibration */
	111
	112	/* Clear stop bit */
	113	val = rtc_read (0x1);
	114	val &= 0x7f;
	115	rtc_write(0x1, val);
	116
	117	/* Enable century / disable frequency test */
	118	val = rtc_read (0x4);
	119	val = (val & 0xBF) \| 0x20;
	120	rtc_write(0x4, val);
	121
	122	/* Clear write lock */
	123	rtc_write(0x0, 0);
	124	}
	125
	126	/* ------------------------------------------------------------------------- */
	127
	128	static uchar rtc_read (uchar reg)
	129	{
	130	uchar val;
	131	val = (unsigned char )
6d0f6bcf	132	((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
affae2bf WD	133	return val;
	134	}
	135
	136	static void rtc_write (uchar reg, uchar val)
	137	{
	138	(unsigned char )
6d0f6bcf	139	((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
affae2bf WD	140	}
affae2bf WD	141
068b60a0	142	#endif