[J-u-boot.git] / include / linux / clk-provider.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2019 DENX Software Engineering
 * Lukasz Majewski, DENX Software Engineering, [email protected]
 *
 * Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
 * Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
 */
#ifndef __LINUX_CLK_PROVIDER_H
#define __LINUX_CLK_PROVIDER_H

static inline void clk_dm(ulong id, struct clk *clk)
{
	if (!IS_ERR(clk))
		clk->id = id;
}

/*
 * flags used across common struct clk.  these flags should only affect the
 * top-level framework.  custom flags for dealing with hardware specifics
 * belong in struct clk_foo
 *
 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
 */
#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
#define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
				/* unused */
#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
/* parents need enable during gate/ungate, set rate and re-parent */
#define CLK_OPS_PARENT_ENABLE	BIT(12)
/* duty cycle call may be forwarded to the parent clock */
#define CLK_DUTY_CYCLE_PARENT	BIT(13)

#define CLK_MUX_INDEX_ONE		BIT(0)
#define CLK_MUX_INDEX_BIT		BIT(1)
#define CLK_MUX_HIWORD_MASK		BIT(2)
#define CLK_MUX_READ_ONLY		BIT(3) /* mux can't be changed */
#define CLK_MUX_ROUND_CLOSEST		BIT(4)

struct clk_mux {
	struct clk	clk;
	void __iomem	*reg;
	u32		*table;
	u32		mask;
	u8		shift;
	u8		flags;

	/*
	 * Fields from struct clk_init_data - this struct has been
	 * omitted to avoid too deep level of CCF for bootloader
	 */
	const char	* const *parent_names;
	u8		num_parents;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
	u32             io_mux_val;
#endif

};

#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
extern const struct clk_ops clk_mux_ops;
u8 clk_mux_get_parent(struct clk *clk);

struct clk_div_table {
	unsigned int	val;
	unsigned int	div;
};

struct clk_divider {
	struct clk	clk;
	void __iomem	*reg;
	u8		shift;
	u8		width;
	u8		flags;
	const struct clk_div_table	*table;
#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
	u32             io_divider_val;
#endif
};

#define clk_div_mask(width)	((1 << (width)) - 1)
#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)

#define CLK_DIVIDER_ONE_BASED		BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
#define CLK_DIVIDER_HIWORD_MASK		BIT(3)
#define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
#define CLK_DIVIDER_READ_ONLY		BIT(5)
#define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)

struct clk_fixed_factor {
	struct clk	clk;
	unsigned int	mult;
	unsigned int	div;
};

#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
					       clk)

int clk_register(struct clk *clk, const char *drv_name, const char *name,
		 const char *parent_name);

struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		unsigned int mult, unsigned int div);

struct clk *clk_register_divider(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_divider_flags);

struct clk *clk_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags);

const char *clk_hw_get_name(const struct clk *hw);
ulong clk_generic_get_rate(struct clk *clk);

static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
{
	return (struct clk *)dev_get_uclass_priv(dev);
}
#endif /* __LINUX_CLK_PROVIDER_H */
Commit	Line	Data
004c1229 LM	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* Copyright (C) 2019 DENX Software Engineering
	4	* Lukasz Majewski, DENX Software Engineering, [email protected]
	5	*
	6	* Copyright (c) 2010-2011 Jeremy Kerr <[email protected]>
	7	* Copyright (C) 2011-2012 Linaro Ltd <[email protected]>
	8	*/
	9	#ifndef __LINUX_CLK_PROVIDER_H
	10	#define __LINUX_CLK_PROVIDER_H
	11
1d7993d1 LM	12	static inline void clk_dm(ulong id, struct clk *clk)
	13	{
	14	if (!IS_ERR(clk))
	15	clk->id = id;
	16	}
	17
	18	/*
	19	* flags used across common struct clk. these flags should only affect the
	20	* top-level framework. custom flags for dealing with hardware specifics
	21	* belong in struct clk_foo
	22	*
	23	* Please update clk_flags[] in drivers/clk/clk.c when making changes here!
	24	*/
	25	#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
	26	#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
	27	#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
	28	#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
	29	/* unused */
	30	#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
	31	#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
	32	#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
	33	#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
	34	#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
	35	#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
	36	#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
	37	/* parents need enable during gate/ungate, set rate and re-parent */
	38	#define CLK_OPS_PARENT_ENABLE BIT(12)
	39	/* duty cycle call may be forwarded to the parent clock */
	40	#define CLK_DUTY_CYCLE_PARENT BIT(13)
	41
	42	#define CLK_MUX_INDEX_ONE BIT(0)
	43	#define CLK_MUX_INDEX_BIT BIT(1)
	44	#define CLK_MUX_HIWORD_MASK BIT(2)
	45	#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
	46	#define CLK_MUX_ROUND_CLOSEST BIT(4)
	47
	48	struct clk_mux {
	49	struct clk clk;
	50	void __iomem *reg;
	51	u32 *table;
	52	u32 mask;
	53	u8 shift;
	54	u8 flags;
	55
	56	/*
	57	* Fields from struct clk_init_data - this struct has been
	58	* omitted to avoid too deep level of CCF for bootloader
	59	*/
	60	const char * const *parent_names;
	61	u8 num_parents;
5da0095e LM	62	#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
	63	u32 io_mux_val;
	64	#endif
	65
1d7993d1 LM	66	};
	67
	68	#define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
4b044082 PF	69	extern const struct clk_ops clk_mux_ops;
4b044082 PF	70	u8 clk_mux_get_parent(struct clk *clk);
1d7993d1 LM	71
	72	struct clk_div_table {
	73	unsigned int val;
	74	unsigned int div;
	75	};
	76
	77	struct clk_divider {
	78	struct clk clk;
	79	void __iomem *reg;
	80	u8 shift;
	81	u8 width;
	82	u8 flags;
	83	const struct clk_div_table *table;
6bb15d6f LM	84	#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
	85	u32 io_divider_val;
	86	#endif
1d7993d1 LM	87	};
	88
	89	#define clk_div_mask(width) ((1 << (width)) - 1)
	90	#define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
	91
	92	#define CLK_DIVIDER_ONE_BASED BIT(0)
	93	#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
	94	#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
	95	#define CLK_DIVIDER_HIWORD_MASK BIT(3)
	96	#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
	97	#define CLK_DIVIDER_READ_ONLY BIT(5)
	98	#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
	99
	100	struct clk_fixed_factor {
	101	struct clk clk;
	102	unsigned int mult;
	103	unsigned int div;
	104	};
	105
	106	#define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
	107	clk)
	108
	109	int clk_register(struct clk clk, const char drv_name, const char *name,
	110	const char *parent_name);
	111
	112	struct clk clk_register_fixed_factor(struct device dev, const char *name,
	113	const char *parent_name, unsigned long flags,
	114	unsigned int mult, unsigned int div);
	115
	116	struct clk clk_register_divider(struct device dev, const char *name,
	117	const char *parent_name, unsigned long flags,
	118	void __iomem *reg, u8 shift, u8 width,
	119	u8 clk_divider_flags);
	120
	121	struct clk clk_register_mux(struct device dev, const char *name,
	122	const char * const *parent_names, u8 num_parents,
	123	unsigned long flags,
	124	void __iomem *reg, u8 shift, u8 width,
	125	u8 clk_mux_flags);
	126
	127	const char clk_hw_get_name(const struct clk hw);
	128	ulong clk_generic_get_rate(struct clk *clk);
	129
004c1229 LM	130	static inline struct clk dev_get_clk_ptr(struct udevice dev)
	131	{
	132	return (struct clk *)dev_get_uclass_priv(dev);
	133	}
	134	#endif /* __LINUX_CLK_PROVIDER_H */