[J-u-boot.git] / include / configs / pm9261.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <[email protected]>
 * Lead Tech Design <www.leadtechdesign.com>
 * Ilko Iliev <www.ronetix.at>
 *
 * Configuation settings for the RONETIX PM9261 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * SoC must be defined first, before hardware.h is included.
 * In this case SoC is defined in boards.cfg.
 */

#include <asm/hardware.h>
/* ARM asynchronous clock */

#define MASTER_PLL_DIV		15
#define MASTER_PLL_MUL		162
#define MAIN_PLL_DIV		2
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000

#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
#define CONFIG_ARCH_CPU_INIT

#define CONFIG_MACH_TYPE	MACH_TYPE_PM9261

/* clocks */
/* CKGR_MOR - enable main osc. */
#define CONFIG_SYS_MOR_VAL						\
		(AT91_PMC_MOR_MOSCEN |					\
		 (255 << 8))		/* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL						\
		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
		 AT91_PMC_PLLXR_OUT(3) |						\
		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR1_VAL		\
		(AT91_PMC_MCKR_CSS_SLOW |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)

/* PCK/2 = MCK Master Clock from PLLA */
#define	CONFIG_SYS_MCKR2_VAL		\
		(AT91_PMC_MCKR_CSS_PLLA |	\
		 AT91_PMC_MCKR_PRES_1 |	\
		 AT91_PMC_MCKR_MDIV_2)

/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000

/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)

/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL							\
		(AT91_SDRAMC_NC_9 |						\
		 AT91_SDRAMC_NR_13 |						\
		 AT91_SDRAMC_NB_4 |						\
		 AT91_SDRAMC_CAS_3 |						\
		 AT91_SDRAMC_DBW_32 |						\
		 (1 <<  8) |		/* Write Recovery Delay */		\
		 (7 << 12) |		/* Row Cycle Delay */			\
		 (3 << 16) |		/* Row Precharge Delay */		\
		 (2 << 20) |		/* Row to Column Delay */		\
		 (5 << 24) |		/* Active to Precharge Delay */		\
		 (1 << 28))		/* Exit Self Refresh to Active Delay */

/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */

/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL					\
		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL					\
		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL				\
		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
		 AT91_SMC_MODE_DBW_16 |				\
		 AT91_SMC_MODE_TDF |				\
		 AT91_SMC_MODE_TDF_CYCLE(6))

/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL			\
		(AT91_RSTC_KEY |		\
		AT91_RSTC_CR_PROCRST |		\
		AT91_RSTC_MR_ERSTL(1) |	\
		AT91_RSTC_MR_ERSTL(2))

/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL				\
		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
		 AT91_WDT_MR_WDV(0xfff) |					\
		 AT91_WDT_MR_WDDIS |				\
		 AT91_WDT_MR_WDD(0xfff))

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#undef CONFIG_SKIP_LOWLEVEL_INIT

/*
 * Hardware drivers
 */

/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1

/* SDRAM */
#define PHYS_SDRAM				0x20000000
#define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */

/* NAND flash */
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)

/* NOR flash */
#define PHYS_FLASH_1				0x10000000
#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT		256
#define CONFIG_SYS_MAX_FLASH_BANKS		1

/* Ethernet */
#define CONFIG_DRIVER_DM9000			1
#define CONFIG_DM9000_BASE			0x30000000
#define DM9000_IO				CONFIG_DM9000_BASE
#define DM9000_DATA				(CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT			1
#define CONFIG_NET_RETRY_COUNT			20
#define CONFIG_RESET_PHY_R			1

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW			1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

#define CONFIG_SYS_LOAD_ADDR			0x22000000

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#undef CONFIG_SYS_USE_DATAFLASH_CS0
#undef CONFIG_SYS_USE_NANDFLASH
#define CONFIG_SYS_USE_FLASH	1

#ifdef CONFIG_SYS_USE_DATAFLASH_CS0

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_OFFSET	0x4200
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_ENV_SECT_SIZE	0x210
#define CONFIG_ENV_SPI_MAX_HZ	15000000
#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
				"sf read 0x22000000 0x84000 0x210000; " \
				"bootm 0x22000000"

#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"

#elif defined (CONFIG_SYS_USE_FLASH)

#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define	CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_OVERWRITE	1

/* JFFS Partition offset set */
#define CONFIG_SYS_JFFS2_FIRST_BANK	0
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11

#define CONFIG_BOOTCOMMAND	"run flashboot"

#define CONFIG_CON_ROT "fbcon=rotate:3 "

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
	"partition=nand0,0\0"					\
	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
		CONFIG_CON_ROT					\
		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
	"addip=setenv bootargs $(bootargs) "			\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
		":$(hostname):eth0:off\0"			\
	"ramboot=tftpboot 0x22000000 vmImage;"			\
		"run ramargs;run addip;bootm 22000000\0"	\
	"nfsboot=tftpboot 0x22000000 vmImage;"			\
		"run nfsargs;run addip;bootm 22000000\0"	\
	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
	""
#else
#error "Undefined memory device"
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		\
		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)

#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
				GENERATED_GBL_DATA_SIZE)

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
32949232 II	2	/*
32949232 II	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <[email protected]>
32949232 II	5	* Lead Tech Design <www.leadtechdesign.com>
	6	* Ilko Iliev <www.ronetix.at>
	7	*
	8	* Configuation settings for the RONETIX PM9261 board.
32949232 II	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
f47316a8 AD	14	/*
	15	* SoC must be defined first, before hardware.h is included.
	16	* In this case SoC is defined in boards.cfg.
	17	*/
	18
	19	#include <asm/hardware.h>
32949232	20	/* ARM asynchronous clock */
32949232	21
32949232 II	22	#define MASTER_PLL_DIV 15
	23	#define MASTER_PLL_MUL 162
	24	#define MAIN_PLL_DIV 2
f47316a8	25	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
7c966a8b	26	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
32949232	27
f47316a8	28	#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
32949232	29	#define CONFIG_ARCH_CPU_INIT
32949232	30
a3e09cc2 AD	31	#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
a3e09cc2 AD	32
32949232 II	33	/* clocks */
	34	/* CKGR_MOR - enable main osc. */
	35	#define CONFIG_SYS_MOR_VAL \
e3150c77	36	(AT91_PMC_MOR_MOSCEN \| \
32949232 II	37	(255 << 8)) /* Main Oscillator Start-up Time */
32949232 II	38	#define CONFIG_SYS_PLLAR_VAL \
e3150c77 AD	39	(AT91_PMC_PLLAR_29 \| /* Bit 29 must be 1 when prog */ \
e3150c77 AD	40	AT91_PMC_PLLXR_OUT(3) \| \
32949232 II	41	((MASTER_PLL_MUL - 1) << 16) \| (MASTER_PLL_DIV))
	42
	43	/* PCK/2 = MCK Master Clock from PLLA */
	44	#define CONFIG_SYS_MCKR1_VAL \
e3150c77 AD	45	(AT91_PMC_MCKR_CSS_SLOW \| \
e3150c77 AD	46	AT91_PMC_MCKR_PRES_1 \| \
7ac2e7c1	47	AT91_PMC_MCKR_MDIV_2)
32949232 II	48
	49	/* PCK/2 = MCK Master Clock from PLLA */
	50	#define CONFIG_SYS_MCKR2_VAL \
e3150c77 AD	51	(AT91_PMC_MCKR_CSS_PLLA \| \
e3150c77 AD	52	AT91_PMC_MCKR_PRES_1 \| \
7ac2e7c1	53	AT91_PMC_MCKR_MDIV_2)
32949232 II	54
	55	/* define PDC[31:16] as DATA[31:16] */
	56	#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
	57	/* no pull-up for D[31:16] */
	58	#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
	59
	60	/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
	61	#define CONFIG_SYS_MATRIX_EBICSA_VAL \
e3150c77	62	(AT91_MATRIX_CSA_DBPUC \| AT91_MATRIX_CSA_EBI_CS1A)
32949232 II	63
	64	/* SDRAM */
	65	/* SDRAMC_MR Mode register */
	66	#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
	67	/* SDRAMC_TR - Refresh Timer register */
	68	#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
	69	/* SDRAMC_CR - Configuration register*/
	70	#define CONFIG_SYS_SDRC_CR_VAL \
	71	(AT91_SDRAMC_NC_9 \| \
	72	AT91_SDRAMC_NR_13 \| \
	73	AT91_SDRAMC_NB_4 \| \
	74	AT91_SDRAMC_CAS_3 \| \
	75	AT91_SDRAMC_DBW_32 \| \
	76	(1 << 8) \| /* Write Recovery Delay */ \
	77	(7 << 12) \| /* Row Cycle Delay */ \
	78	(3 << 16) \| /* Row Precharge Delay */ \
	79	(2 << 20) \| /* Row to Column Delay */ \
	80	(5 << 24) \| /* Active to Precharge Delay */ \
	81	(1 << 28)) /* Exit Self Refresh to Active Delay */
	82
	83	/* Memory Device Register -> SDRAM */
	84	#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
	85	#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
	86	#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
	87	#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
	88	#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
	89	#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
	90	#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
	91	#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
	92	#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
	93	#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
	94	#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
	95	#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
	96	#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
	97	#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
	98	#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
	99	#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
	100	#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
	101	#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
	102
	103	/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
	104	#define CONFIG_SYS_SMC0_SETUP0_VAL \
e3150c77 AD	105	(AT91_SMC_SETUP_NWE(10) \| AT91_SMC_SETUP_NCS_WR(10) \| \
e3150c77 AD	106	AT91_SMC_SETUP_NRD(10) \| AT91_SMC_SETUP_NCS_RD(10))
32949232	107	#define CONFIG_SYS_SMC0_PULSE0_VAL \
e3150c77 AD	108	(AT91_SMC_PULSE_NWE(11) \| AT91_SMC_PULSE_NCS_WR(11) \| \
e3150c77 AD	109	AT91_SMC_PULSE_NRD(11) \| AT91_SMC_PULSE_NCS_RD(11))
32949232	110	#define CONFIG_SYS_SMC0_CYCLE0_VAL \
e3150c77	111	(AT91_SMC_CYCLE_NWE(22) \| AT91_SMC_CYCLE_NRD(22))
32949232	112	#define CONFIG_SYS_SMC0_MODE0_VAL \
e3150c77 AD	113	(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \| \
	114	AT91_SMC_MODE_DBW_16 \| \
	115	AT91_SMC_MODE_TDF \| \
	116	AT91_SMC_MODE_TDF_CYCLE(6))
32949232 II	117
	118	/* user reset enable */
	119	#define CONFIG_SYS_RSTC_RMR_VAL \
	120	(AT91_RSTC_KEY \| \
e3150c77 AD	121	AT91_RSTC_CR_PROCRST \| \
	122	AT91_RSTC_MR_ERSTL(1) \| \
	123	AT91_RSTC_MR_ERSTL(2))
32949232 II	124
	125	/* Disable Watchdog */
	126	#define CONFIG_SYS_WDTC_WDMR_VAL \
e3150c77 AD	127	(AT91_WDT_MR_WDIDLEHLT \| AT91_WDT_MR_WDDBGHLT \| \
	128	AT91_WDT_MR_WDV(0xfff) \| \
	129	AT91_WDT_MR_WDDIS \| \
	130	AT91_WDT_MR_WDD(0xfff))
32949232 II	131
	132	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	133	#define CONFIG_SETUP_MEMORY_TAGS 1
	134	#define CONFIG_INITRD_TAG 1
	135
	136	#undef CONFIG_SKIP_LOWLEVEL_INIT
32949232 II	137
	138	/*
	139	* Hardware drivers
	140	*/
32949232 II	141
32949232 II	142	/* LCD */
32949232 II	143	#define LCD_BPP LCD_COLOR8
	144	#define CONFIG_LCD_LOGO 1
	145	#undef LCD_TEST_PATTERN
	146	#define CONFIG_LCD_INFO 1
	147	#define CONFIG_LCD_INFO_BELOW_LOGO 1
32949232 II	148	#define CONFIG_ATMEL_LCD 1
32949232 II	149	#define CONFIG_ATMEL_LCD_BGR555 1
32949232	150
32949232 II	151	/*
	152	* BOOTP options
	153	*/
	154	#define CONFIG_BOOTP_BOOTFILESIZE 1
32949232	155
32949232	156	/* SDRAM */
32949232 II	157	#define PHYS_SDRAM 0x20000000
	158	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	159
32949232	160	/* NAND flash */
32949232 II	161	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	162	#define CONFIG_SYS_NAND_BASE 0x40000000
	163	#define CONFIG_SYS_NAND_DBW_8 1
	164	/* our ALE is AD22 */
	165	#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
	166	/* our CLE is AD21 */
	167	#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
ac45bb16 AB	168	#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
ac45bb16 AB	169	#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
32949232	170
32949232	171	/* NOR flash */
32949232 II	172	#define PHYS_FLASH_1 0x10000000
	173	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	174	#define CONFIG_SYS_MAX_FLASH_SECT 256
	175	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	176
	177	/* Ethernet */
	178	#define CONFIG_DRIVER_DM9000 1
	179	#define CONFIG_DM9000_BASE 0x30000000
	180	#define DM9000_IO CONFIG_DM9000_BASE
	181	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	182	#define CONFIG_DM9000_USE_16BIT 1
	183	#define CONFIG_NET_RETRY_COUNT 20
	184	#define CONFIG_RESET_PHY_R 1
	185
	186	/* USB */
	187	#define CONFIG_USB_ATMEL
dcd2f1a0	188	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
32949232	189	#define CONFIG_USB_OHCI_NEW 1
32949232 II	190	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	191	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
	192	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
	193	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
32949232 II	194
	195	#define CONFIG_SYS_LOAD_ADDR 0x22000000
	196
	197	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
	198	#define CONFIG_SYS_MEMTEST_END 0x23e00000
	199
	200	#undef CONFIG_SYS_USE_DATAFLASH_CS0
	201	#undef CONFIG_SYS_USE_NANDFLASH
	202	#define CONFIG_SYS_USE_FLASH 1
	203
	204	#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
	205
	206	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
32949232	207	#define CONFIG_ENV_OFFSET 0x4200
32949232	208	#define CONFIG_ENV_SIZE 0x4200
c53a825e WY	209	#define CONFIG_ENV_SECT_SIZE 0x210
	210	#define CONFIG_ENV_SPI_MAX_HZ 15000000
	211	#define CONFIG_BOOTCOMMAND "sf probe 0; " \
	212	"sf read 0x22000000 0x84000 0x210000; " \
	213	"bootm 0x22000000"
32949232 II	214
	215	#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
	216
	217	/* bootstrap + u-boot + env + linux in nandflash */
32949232 II	218	#define CONFIG_ENV_OFFSET 0x60000
	219	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	220	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
	221	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
32949232 II	222
	223	#elif defined (CONFIG_SYS_USE_FLASH)
	224
32949232 II	225	#define CONFIG_ENV_OFFSET 0x40000
	226	#define CONFIG_ENV_SECT_SIZE 0x10000
	227	#define CONFIG_ENV_SIZE 0x10000
	228	#define CONFIG_ENV_OVERWRITE 1
	229
	230	/* JFFS Partition offset set */
	231	#define CONFIG_SYS_JFFS2_FIRST_BANK 0
	232	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	233
	234	/* 512k reserved for u-boot */
	235	#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
	236
	237	#define CONFIG_BOOTCOMMAND "run flashboot"
	238
32949232	239	#define CONFIG_CON_ROT "fbcon=rotate:3 "
32949232 II	240
32949232 II	241	#define CONFIG_EXTRA_ENV_SETTINGS \
43ede0bc TR	242	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
43ede0bc TR	243	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
32949232 II	244	"partition=nand0,0\0" \
	245	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
	246	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	247	CONFIG_CON_ROT \
	248	"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
	249	"addip=setenv bootargs $(bootargs) " \
	250	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
	251	":$(hostname):eth0:off\0" \
	252	"ramboot=tftpboot 0x22000000 vmImage;" \
	253	"run ramargs;run addip;bootm 22000000\0" \
	254	"nfsboot=tftpboot 0x22000000 vmImage;" \
	255	"run nfsargs;run addip;bootm 22000000\0" \
	256	"flashboot=run ramargs;run addip;bootm 0x10050000\0" \
	257	""
	258	#else
	259	#error "Undefined memory device"
	260	#endif
	261
32949232 II	262	/*
	263	* Size of malloc() pool
	264	*/
	265	#define CONFIG_SYS_MALLOC_LEN \
	266	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
32949232	267
4f81bf43	268	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
c53a825e	269	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
4f81bf43 AD	270	GENERATED_GBL_DATA_SIZE)
4f81bf43 AD	271
32949232	272	#endif