[J-u-boot.git] / board / freescale / mpc8641hpcn / mpc8641hpcn.c

/*
 * Copyright 2006, 2007 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/immap_fsl_pci.h>
#include <spd_sdram.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>

#include "../common/pixis.h"

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

void sdram_init(void);
long int fixed_sdram(void);


int board_early_init_f(void)
{
	return 0;
}

int checkboard(void)
{
	printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
		"System Version: 0x%02x, FPGA Version: 0x%02x\n",
		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
		in8(PIXIS_BASE + PIXIS_PVER));
	return 0;
}


phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram();
#else
	dram_size = fixed_sdram();
#endif

#if defined(CFG_RAMBOOT)
	puts("    DDR: ");
	return dram_size;
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	puts("    DDR: ");
	return dram_size;
}


#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */
long int
fixed_sdram(void)
{
#if !defined(CFG_RAMBOOT)
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;

	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	ddr->sdram_mode_1 = CFG_DDR_MODE_1;
	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
	ddr->sdram_interval = CFG_DDR_INTERVAL;
	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
	ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;

#if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000008D;
	ddr->err_sbe = 0x00ff0000;
#endif
	asm("sync;isync");

	udelay(500);

#if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
#else
	ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
#endif
	asm("sync; isync");

	udelay(500);
#endif
	return CFG_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				     PCI_ENET0_MEMADDR,
				     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
	{}
};
#endif


static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
	config_table:pci_mpc86xxcts_config_table
#endif
};
#endif /* CONFIG_PCI */

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif	/* CONFIG_PCI2 */

int first_free_busno = 0;


void pci_init_board(void)
{
	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;

#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;
#ifdef DEBUG
	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
		>> MPC8641_PORBMSR_HA_SHIFT;
	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
#endif
	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
		debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug(" with errors.  Clearing.  Now 0x%08x",
			      pci->pme_msg_det);
		}
		debug("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CFG_PCI_MEMORY_BUS,
			       CFG_PCI_MEMORY_PHYS,
			       CFG_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CFG_PCI1_MEM_BASE,
			       CFG_PCI1_MEM_PHYS,
			       CFG_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CFG_PCI1_IO_BASE,
			       CFG_PCI1_IO_PHYS,
			       CFG_PCI1_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);

		/*
		 * Activate ULI1575 legacy chip by performing a fake
		 * memory access.  Needed to make ULI RTC work.
		 */
		in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
				       + CFG_PCI1_MEM_SIZE - 0x1000000)));

	} else {
		puts("PCI-EXPRESS 1: Disabled\n");
	}
}
#else
	puts("PCI-EXPRESS1: Disabled\n");
#endif /* CONFIG_PCI1 */

#ifdef CONFIG_PCI2
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci2_hose;


	/* inbound */
	pci_set_region(hose->regions + 0,
		       CFG_PCI_MEMORY_BUS,
		       CFG_PCI_MEMORY_PHYS,
		       CFG_PCI_MEMORY_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	/* outbound memory */
	pci_set_region(hose->regions + 1,
		       CFG_PCI2_MEM_BASE,
		       CFG_PCI2_MEM_PHYS,
		       CFG_PCI2_MEM_SIZE,
		       PCI_REGION_MEM);

	/* outbound io */
	pci_set_region(hose->regions + 2,
		       CFG_PCI2_IO_BASE,
		       CFG_PCI2_IO_PHYS,
		       CFG_PCI2_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 3;

	hose->first_busno=first_free_busno;
	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

	fsl_pci_init(hose);

	first_free_busno=hose->last_busno+1;
	printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
		hose->first_busno,hose->last_busno);
}
#else
	puts("PCI-EXPRESS 2: Disabled\n");
#endif /* CONFIG_PCI2 */

}


#if defined(CONFIG_OF_BOARD_SETUP)

void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI1
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
#ifdef CONFIG_PCI2
		path = fdt_getprop(blob, node, "pci1", NULL);
		if (path) {
			tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif


/*
 * get_board_sys_clk
 *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 */

unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i, go_bit, rd_clks;
	ulong val = 0;

	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	go_bit &= 0x01;

	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	rd_clks &= 0x1C;

	/*
	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
	 * should we be using the AUX register. Remember, we also set the
	 * GO bit to boot from the alternate bank on the on-board flash
	 */

	if (go_bit) {
		if (rd_clks == 0x1c)
			i = in8(PIXIS_BASE + PIXIS_AUX);
		else
			i = in8(PIXIS_BASE + PIXIS_SPD);
	} else {
		i = in8(PIXIS_BASE + PIXIS_SPD);
	}

	i &= 0x07;

	switch (i) {
	case 0:
		val = 33000000;
		break;
	case 1:
		val = 40000000;
		break;
	case 2:
		val = 50000000;
		break;
	case 3:
		val = 66000000;
		break;
	case 4:
		val = 83000000;
		break;
	case 5:
		val = 100000000;
		break;
	case 6:
		val = 134000000;
		break;
	case 7:
		val = 166000000;
		break;
	}

	return val;
}
Commit	Line	Data
debb7354	1	/*
3d98b858	2	* Copyright 2006, 2007 Freescale Semiconductor.
debb7354 JL	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
63cec581	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
debb7354 JL	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	#include <common.h>
	24	#include <pci.h>
	25	#include <asm/processor.h>
	26	#include <asm/immap_86xx.h>
63cec581	27	#include <asm/immap_fsl_pci.h>
a30a549a	28	#include <spd_sdram.h>
3d98b858	29	#include <asm/io.h>
ea9f7395 JL	30	#include <libfdt.h>
ea9f7395 JL	31	#include <fdt_support.h>
debb7354	32
4ce91774	33	#include "../common/pixis.h"
4d3d729c	34
debb7354 JL	35	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	36	extern void ddr_enable_ecc(unsigned int dram_size);
	37	#endif
	38
debb7354 JL	39	void sdram_init(void);
	40	long int fixed_sdram(void);
	41
	42
80e955c7	43	int board_early_init_f(void)
debb7354	44	{
cb5965fb	45	return 0;
debb7354 JL	46	}
debb7354 JL	47
80e955c7	48	int checkboard(void)
debb7354	49	{
9b55a253 WD	50	printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
9b55a253 WD	51	"System Version: 0x%02x, FPGA Version: 0x%02x\n",
7de8c21f KG	52	in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
7de8c21f KG	53	in8(PIXIS_BASE + PIXIS_PVER));
debb7354 JL	54	return 0;
	55	}
	56
	57
9973e3c6	58	phys_size_t
debb7354 JL	59	initdram(int board_type)
	60	{
	61	long dram_size = 0;
debb7354 JL	62
debb7354 JL	63	#if defined(CONFIG_SPD_EEPROM)
80e955c7	64	dram_size = spd_sdram();
debb7354	65	#else
80e955c7	66	dram_size = fixed_sdram();
debb7354 JL	67	#endif
	68
	69	#if defined(CFG_RAMBOOT)
	70	puts(" DDR: ");
	71	return dram_size;
	72	#endif
cb5965fb	73
debb7354 JL	74	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	75	/*
	76	* Initialize and enable DDR ECC.
	77	*/
	78	ddr_enable_ecc(dram_size);
	79	#endif
	80
debb7354 JL	81	puts(" DDR: ");
	82	return dram_size;
	83	}
	84
	85
debb7354	86	#if !defined(CONFIG_SPD_EEPROM)
5c9efb36 JL	87	/*
	88	* Fixed sdram init -- doesn't use serial presence detect.
	89	*/
80e955c7 JL	90	long int
80e955c7 JL	91	fixed_sdram(void)
debb7354 JL	92	{
debb7354 JL	93	#if !defined(CFG_RAMBOOT)
80e955c7 JL	94	volatile immap_t immap = (immap_t ) CFG_IMMR;
80e955c7 JL	95	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
debb7354 JL	96
	97	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
	98	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
45239cf4	99	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
debb7354 JL	100	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
	101	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
	102	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
	103	ddr->sdram_mode_1 = CFG_DDR_MODE_1;
	104	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
	105	ddr->sdram_interval = CFG_DDR_INTERVAL;
cb5965fb	106	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
debb7354	107	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
cb5965fb	108	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
debb7354 JL	109	ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
	110
	111	#if defined (CONFIG_DDR_ECC)
	112	ddr->err_disable = 0x0000008D;
	113	ddr->err_sbe = 0x00ff0000;
	114	#endif
	115	asm("sync;isync");
cb5965fb	116
debb7354 JL	117	udelay(500);
	118
	119	#if defined (CONFIG_DDR_ECC)
	120	/* Enable ECC checking */
	121	ddr->sdram_cfg_1 = (CFG_DDR_CONTROL \| 0x20000000);
	122	#else
	123	ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
	124	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
	125	#endif
	126	asm("sync; isync");
cb5965fb	127
debb7354 JL	128	udelay(500);
	129	#endif
	130	return CFG_SDRAM_SIZE * 1024 * 1024;
	131	}
	132	#endif /* !defined(CONFIG_SPD_EEPROM) */
	133
	134
	135	#if defined(CONFIG_PCI)
	136	/*
	137	* Initialize PCI Devices, report devices found.
	138	*/
	139
	140	#ifndef CONFIG_PCI_PNP
	141	static struct pci_config_table pci_fsl86xxads_config_table[] = {
80e955c7 JL	142	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	143	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	144	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	145	PCI_ENET0_MEMADDR,
	146	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER}},
	147	{}
debb7354 JL	148	};
	149	#endif
	150
	151
63cec581	152	static struct pci_controller pci1_hose = {
debb7354	153	#ifndef CONFIG_PCI_PNP
63cec581	154	config_table:pci_mpc86xxcts_config_table
debb7354 JL	155	#endif
debb7354 JL	156	};
80e955c7	157	#endif /* CONFIG_PCI */
debb7354	158
63cec581 ES	159	#ifdef CONFIG_PCI2
	160	static struct pci_controller pci2_hose;
	161	#endif /* CONFIG_PCI2 */
	162
	163	int first_free_busno = 0;
	164
	165
80e955c7	166	void pci_init_board(void)
debb7354	167	{
63cec581 ES	168	volatile immap_t immap = (immap_t ) CFG_CCSRBAR;
	169	volatile ccsr_gur_t *gur = &immap->im_gur;
	170	uint devdisr = gur->devdisr;
a551cee9 JL	171	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
a551cee9 JL	172	>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
63cec581 ES	173
	174	#ifdef CONFIG_PCI1
	175	{
	176	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI1_ADDR;
	177	extern void fsl_pci_init(struct pci_controller *hose);
	178	struct pci_controller *hose = &pci1_hose;
	179	#ifdef DEBUG
a551cee9 JL	180	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
a551cee9 JL	181	>> MPC8641_PORBMSR_HA_SHIFT;
63cec581 ES	182	uint pex1_agent = (host1_agent == 0) \|\| (host1_agent == 1);
	183	#endif
	184	if ((io_sel == 2 \|\| io_sel == 3 \|\| io_sel == 5
	185	\|\| io_sel == 6 \|\| io_sel == 7 \|\| io_sel == 0xF)
	186	&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
	187	debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
	188	debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
	189	if (pci->pme_msg_det) {
	190	pci->pme_msg_det = 0xffffffff;
	191	debug(" with errors. Clearing. Now 0x%08x",
	192	pci->pme_msg_det);
	193	}
	194	debug("\n");
	195
	196	/* inbound */
	197	pci_set_region(hose->regions + 0,
	198	CFG_PCI_MEMORY_BUS,
	199	CFG_PCI_MEMORY_PHYS,
	200	CFG_PCI_MEMORY_SIZE,
	201	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	202
	203	/* outbound memory */
	204	pci_set_region(hose->regions + 1,
	205	CFG_PCI1_MEM_BASE,
	206	CFG_PCI1_MEM_PHYS,
	207	CFG_PCI1_MEM_SIZE,
	208	PCI_REGION_MEM);
	209
	210	/* outbound io */
	211	pci_set_region(hose->regions + 2,
	212	CFG_PCI1_IO_BASE,
	213	CFG_PCI1_IO_PHYS,
	214	CFG_PCI1_IO_SIZE,
	215	PCI_REGION_IO);
	216
	217	hose->region_count = 3;
	218
	219	hose->first_busno=first_free_busno;
	220	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	221
	222	fsl_pci_init(hose);
	223
	224	first_free_busno=hose->last_busno+1;
	225	printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
	226	hose->first_busno,hose->last_busno);
	227
	228	/*
	229	* Activate ULI1575 legacy chip by performing a fake
	230	* memory access. Needed to make ULI RTC work.
	231	*/
cf0b185e JL	232	in_be32((unsigned ) ((char )(CFG_PCI1_MEM_BASE
cf0b185e JL	233	+ CFG_PCI1_MEM_SIZE - 0x1000000)));
63cec581 ES	234
	235	} else {
	236	puts("PCI-EXPRESS 1: Disabled\n");
	237	}
	238	}
	239	#else
	240	puts("PCI-EXPRESS1: Disabled\n");
	241	#endif /* CONFIG_PCI1 */
	242
	243	#ifdef CONFIG_PCI2
	244	{
	245	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CFG_PCI2_ADDR;
	246	extern void fsl_pci_init(struct pci_controller *hose);
	247	struct pci_controller *hose = &pci2_hose;
	248
	249
	250	/* inbound */
	251	pci_set_region(hose->regions + 0,
	252	CFG_PCI_MEMORY_BUS,
	253	CFG_PCI_MEMORY_PHYS,
	254	CFG_PCI_MEMORY_SIZE,
	255	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	256
	257	/* outbound memory */
	258	pci_set_region(hose->regions + 1,
	259	CFG_PCI2_MEM_BASE,
	260	CFG_PCI2_MEM_PHYS,
	261	CFG_PCI2_MEM_SIZE,
	262	PCI_REGION_MEM);
	263
	264	/* outbound io */
	265	pci_set_region(hose->regions + 2,
	266	CFG_PCI2_IO_BASE,
	267	CFG_PCI2_IO_PHYS,
	268	CFG_PCI2_IO_SIZE,
	269	PCI_REGION_IO);
	270
	271	hose->region_count = 3;
	272
	273	hose->first_busno=first_free_busno;
	274	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	275
	276	fsl_pci_init(hose);
	277
	278	first_free_busno=hose->last_busno+1;
	279	printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
	280	hose->first_busno,hose->last_busno);
	281	}
	282	#else
	283	puts("PCI-EXPRESS 2: Disabled\n");
	284	#endif /* CONFIG_PCI2 */
debb7354	285
debb7354 JL	286	}
debb7354 JL	287
13f5433f	288
ea9f7395	289	#if defined(CONFIG_OF_BOARD_SETUP)
13f5433f	290
debb7354 JL	291	void
	292	ft_board_setup(void blob, bd_t bd)
	293	{
ea9f7395 JL	294	int node, tmp[2];
ea9f7395 JL	295	const char *path;
debb7354	296
13f5433f	297	ft_cpu_setup(blob, bd);
ea9f7395 JL	298
	299	node = fdt_path_offset(blob, "/aliases");
	300	tmp[0] = 0;
	301	if (node >= 0) {
f75e89e9	302	#ifdef CONFIG_PCI1
ea9f7395 JL	303	path = fdt_getprop(blob, node, "pci0", NULL);
	304	if (path) {
	305	tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
	306	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	307	}
f75e89e9 ES	308	#endif
f75e89e9 ES	309	#ifdef CONFIG_PCI2
ea9f7395 JL	310	path = fdt_getprop(blob, node, "pci1", NULL);
	311	if (path) {
	312	tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
	313	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	314	}
f75e89e9	315	#endif
ea9f7395	316	}
debb7354 JL	317	}
	318	#endif
	319
debb7354	320
239db37c HW	321	/*
	322	* get_board_sys_clk
	323	* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
	324	*/
	325
80e955c7 JL	326	unsigned long
80e955c7 JL	327	get_board_sys_clk(ulong dummy)
239db37c HW	328	{
	329	u8 i, go_bit, rd_clks;
	330	ulong val = 0;
	331
	332	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
	333	go_bit &= 0x01;
	334
	335	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	336	rd_clks &= 0x1C;
	337
	338	/*
	339	* Only if both go bit and the SCLK bit in VCFGEN0 are set
	340	* should we be using the AUX register. Remember, we also set the
	341	* GO bit to boot from the alternate bank on the on-board flash
	342	*/
	343
	344	if (go_bit) {
	345	if (rd_clks == 0x1c)
	346	i = in8(PIXIS_BASE + PIXIS_AUX);
	347	else
	348	i = in8(PIXIS_BASE + PIXIS_SPD);
	349	} else {
	350	i = in8(PIXIS_BASE + PIXIS_SPD);
	351	}
	352
	353	i &= 0x07;
	354
	355	switch (i) {
	356	case 0:
	357	val = 33000000;
	358	break;
	359	case 1:
	360	val = 40000000;
	361	break;
	362	case 2:
	363	val = 50000000;
	364	break;
	365	case 3:
	366	val = 66000000;
	367	break;
	368	case 4:
	369	val = 83000000;
	370	break;
	371	case 5:
	372	val = 100000000;
	373	break;
	374	case 6:
	375	val = 134000000;
	376	break;
	377	case 7:
	378	val = 166000000;
	379	break;
	380	}
	381
	382	return val;
	383	}