[J-u-boot.git] / include / configs / omapl138_lcdk.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *
 * Based on davinci_dvevm.h. Original Copyrights follow:
 *
 * Copyright (C) 2007 Sergey Kubushyn <[email protected]>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */

/*
 * SoC Configuration
 */
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		24000000
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ			1000

/*
 * Memory Info
 */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/

#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000

/* memtest start addr */

/* memtest will be run on 16MB */

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/*
 * PLL configuration
 */

/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
#define CONFIG_SYS_DA850_PLL0_PLLM     18
#define CONFIG_SYS_DA850_PLL1_PLLM     21

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
	(4 << DV_DDR_SDCR_CL_SHIFT)		| \
	(3 << DV_DDR_SDCR_IBANK_SHIFT)		| \
	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
	(2 << DV_DDR_SDTMR1_WR_SHIFT)		| \
	(6 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
	(8 << DV_DDR_SDTMR1_RC_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
	(1 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
	(20 << DV_DDR_SDTMR2_XSNR_SHIFT)	| \
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT)	| \
	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
	(2 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30

/*
 * Serial Driver info
 */
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)

#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)

/*
 * I2C Configuration
 */
#define CONFIG_SYS_DAVINCI_I2C_SPEED	25000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE	10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20

/*
 * Flash & Environment
 */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define	CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_CS		3
#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_NAND_MASK_CLE	0x10
#define CONFIG_SYS_NAND_MASK_ALE	0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_SIZE	SZ_512K
#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
					CONFIG_SYS_NAND_U_BOOT_SIZE - \
					CONFIG_SYS_MALLOC_LEN -       \
					GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_NAND_ECCPOS		{				\
				6, 7, 8, 9, 10, 11, 12, 13, 14, 15,	\
				22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
				38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
				54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	10
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SPL_NAND_LOAD
#endif

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_NET_RETRY_COUNT	10
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_BOOTFILE		"zImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */

/*
 * USB Configs
 */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
#define CONFIG_BOOTCOMMAND \
		"run envboot; " \
		"run mmcboot; "

#define DEFAULT_LINUX_BOOT_ENV \
	"loadaddr=0xc0700000\0" \
	"fdtaddr=0xc0600000\0" \
	"scriptaddr=0xc0600000\0"

#include <environment/ti/mmc.h>

#define CONFIG_EXTRA_ENV_SETTINGS \
	DEFAULT_LINUX_BOOT_ENV \
	DEFAULT_MMC_TI_ARGS \
	"bootpart=0:2\0" \
	"bootdir=/boot\0" \
	"bootfile=zImage\0" \
	"fdtfile=da850-lcdk.dtb\0" \
	"boot_fdt=yes\0" \
	"boot_fit=0\0" \
	"console=ttyS2,115200n8\0"

#ifdef CONFIG_CMD_BDI
#define CONFIG_CLOCKS
#endif

/* SD/MMC */

/* defines for SPL */
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SPL_STACK	0x8001ff00
#define CONFIG_SPL_MAX_FOOTPRINT	32768
#define CONFIG_SPL_PAD_TO	32768

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
					GENERATED_GBL_DATA_SIZE)

#include <asm/arch/hardware.h>

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
a868e443 PH	2	/*
	3	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	4	*
	5	* Based on davinci_dvevm.h. Original Copyrights follow:
	6	*
	7	* Copyright (C) 2007 Sergey Kubushyn <[email protected]>
a868e443 PH	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* Board
	15	*/
a868e443 PH	16
	17	/*
	18	* SoC Configuration
	19	*/
a868e443 PH	20	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	21	#define CONFIG_SYS_OSCIN_FREQ 24000000
	22	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	23	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
	24	#define CONFIG_SYS_HZ 1000
a868e443 PH	25
	26	/*
	27	* Memory Info
	28	*/
a868e443 PH	29	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
	30	#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
	31	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
	32
15b8c750 AF	33	#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
	34	#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
	35
a868e443	36	/* memtest start addr */
a868e443 PH	37
a868e443 PH	38	/* memtest will be run on 16MB */
a868e443	39
a868e443 PH	40	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
	41	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
	42	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
	43	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
	44	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
	45	DAVINCI_SYSCFG_SUSPSRC_I2C)
	46
	47	/*
	48	* PLL configuration
	49	*/
a868e443	50
dc73483a DL	51	/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
dc73483a DL	52	#define CONFIG_SYS_DA850_PLL0_PLLM 18
a868e443 PH	53	#define CONFIG_SYS_DA850_PLL1_PLLM 21
a868e443 PH	54
a5ab44f6 FP	55	/*
	56	* DDR2 memory configuration
	57	*/
	58	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	59	DV_DDR_PHY_EXT_STRBEN \| \
	60	(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	61
	62	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	63	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) \| \
	64	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	65	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	66	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	67	(4 << DV_DDR_SDCR_CL_SHIFT) \| \
	68	(3 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	69	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	70
	71	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
	72	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
	73
	74	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	75	(19 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	76	(1 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	77	(1 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	78	(2 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	79	(6 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	80	(8 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	81	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	82	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
	83
	84	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	85	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
	86	(2 << DV_DDR_SDTMR2_XP_SHIFT) \| \
	87	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
264e420f	88	(20 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
a5ab44f6 FP	89	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
	90	(1 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
	91	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
	92
	93	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492
	94	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
	95
a868e443 PH	96	/*
	97	* Serial Driver info
	98	*/
d6d8c4d4	99	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
a868e443	100
a868e443 PH	101	#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
a868e443 PH	102	#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
a868e443	103
a868e443 PH	104	/*
	105	* I2C Configuration
	106	*/
a868e443 PH	107	#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
	108	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
	109	#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
	110
	111	/*
	112	* Flash & Environment
	113	*/
88718be3	114	#ifdef CONFIG_MTD_RAW_NAND
a868e443 PH	115	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
a868e443 PH	116	#define CONFIG_SYS_NAND_PAGE_2K
a868e443 PH	117	#define CONFIG_SYS_NAND_CS 3
a868e443 PH	118	#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
1dbab274	119	#define CONFIG_SYS_NAND_MASK_CLE 0x10
ef044796	120	#define CONFIG_SYS_NAND_MASK_ALE 0x8
a868e443 PH	121	#undef CONFIG_SYS_NAND_HW_ECC
a868e443 PH	122	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
c69a05d0	123	#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
2b2cab24	124	#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
c69a05d0 FP	125	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	126	#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
	127	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
c0c10449	128	#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
c69a05d0 FP	129	#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
	130	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
	131	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
	132	CONFIG_SYS_NAND_U_BOOT_SIZE - \
	133	CONFIG_SYS_MALLOC_LEN - \
	134	GENERATED_GBL_DATA_SIZE)
	135	#define CONFIG_SYS_NAND_ECCPOS { \
2b2cab24 FP	136	6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
	137	22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
	138	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
	139	54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
c69a05d0 FP	140	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	141	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	142	#define CONFIG_SYS_NAND_ECCSIZE 512
	143	#define CONFIG_SYS_NAND_ECCBYTES 10
	144	#define CONFIG_SYS_NAND_OOBSIZE 64
c69a05d0	145	#define CONFIG_SPL_NAND_LOAD
a868e443 PH	146	#endif
a868e443 PH	147
a868e443 PH	148	/*
	149	* Network & Ethernet Configuration
	150	*/
	151	#ifdef CONFIG_DRIVER_TI_EMAC
a868e443	152	#define CONFIG_NET_RETRY_COUNT 10
a868e443 PH	153	#endif
	154
	155	/*
	156	* U-Boot general configuration
	157	*/
963ed6f3	158	#define CONFIG_BOOTFILE "zImage" /* Boot file name */
a868e443	159	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a868e443	160	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
a868e443	161
8f6babf8 AF	162	/*
	163	* USB Configs
	164	*/
	165	#define CONFIG_USB_OHCI_NEW
	166	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	167
a868e443 PH	168	/*
	169	* Linux Information
	170	*/
	171	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
f96ab6a4	172	#define CONFIG_BOOTCOMMAND \
1120dda8	173	"run envboot; " \
4c8865a2	174	"run mmcboot; "
6e806961 SN	175
	176	#define DEFAULT_LINUX_BOOT_ENV \
	177	"loadaddr=0xc0700000\0" \
5ca28f67	178	"fdtaddr=0xc0600000\0" \
6e806961 SN	179	"scriptaddr=0xc0600000\0"
6e806961 SN	180
1120dda8 SN	181	#include <environment/ti/mmc.h>
1120dda8 SN	182
6e806961 SN	183	#define CONFIG_EXTRA_ENV_SETTINGS \
6e806961 SN	184	DEFAULT_LINUX_BOOT_ENV \
1120dda8 SN	185	DEFAULT_MMC_TI_ARGS \
	186	"bootpart=0:2\0" \
	187	"bootdir=/boot\0" \
	188	"bootfile=zImage\0" \
5ca28f67	189	"fdtfile=da850-lcdk.dtb\0" \
1120dda8 SN	190	"boot_fdt=yes\0" \
	191	"boot_fit=0\0" \
	192	"console=ttyS2,115200n8\0"
a868e443	193
a868e443 PH	194	#ifdef CONFIG_CMD_BDI
	195	#define CONFIG_CLOCKS
	196	#endif
	197
a868e443	198	/* SD/MMC */
a868e443	199
a868e443	200	/* defines for SPL */
a868e443 PH	201	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
	202	CONFIG_SYS_MALLOC_LEN)
	203	#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
a868e443	204	#define CONFIG_SPL_STACK 0x8001ff00
a868e443 PH	205	#define CONFIG_SPL_MAX_FOOTPRINT 32768
a868e443 PH	206	#define CONFIG_SPL_PAD_TO 32768
a868e443 PH	207
	208	/* additions for new relocation code, must added to all boards */
	209	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
	210	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
	211	GENERATED_GBL_DATA_SIZE)
89f5eaa1 SG	212
	213	#include <asm/arch/hardware.h>
	214
a868e443	215	#endif /* __CONFIG_H */