[J-u-boot.git] / include / configs / cm_t35.h

/*
 * (C) Copyright 2011 CompuLab, Ltd.
 * Mike Rapoport <[email protected]>
 * Igor Grinberg <[email protected]>
 *
 * Based on omap3_beagle.h
 * (C) Copyright 2006-2008
 * Texas Instruments.
 * Richard Woodruff <[email protected]>
 * Syed Mohammed Khasim <[email protected]>
 *
 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP	/* in a TI OMAP core */
#define CONFIG_OMAP34XX	/* which is a 34XX */
#define CONFIG_OMAP_GPIO
#define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */

#define CONFIG_SYS_TEXT_BASE	0x80008000

#define CONFIG_SDRC	/* The chip has SDRC controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_OF_LIBFDT		1
/*
 * The early kernel mapping on ARM currently only maps from the base of DRAM
 * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
 * so that leaves DRAM base to DRAM base + 0x4000 available.
 */
#define CONFIG_SYS_BOOTMAPSZ	        0x4000

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
					/* Sector */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* USB */
#define CONFIG_MUSB_UDC
#define CONFIG_USB_OMAP3
#define CONFIG_TWL4030_USB

/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define MTDIDS_DEFAULT		"nand0=nand"
#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
				"1920k(u-boot),128k(u-boot-env),"\
				"4m(kernel),-(fs)"

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_I2C_MULTI_BUS

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER
#define CONFIG_TWL4030_LED

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */
#define GPMC_NAND_ECC_LP_x8_LAYOUT

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		10

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"usbtty=cdc_acm\0" \
	"console=ttyS2,115200n8\0" \
	"mpurate=500\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=/dev/mtdblock4 rw\0" \
	"nandrootfstype=jffs2\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapfb.debug=y " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD		"no"
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"CM-T3x # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
								/* works on */
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1	/* CS1 is never populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CM_T3X_SMC911X_BASE	0x2C000000
#define SB_T35_SMC911X_BASE	(CM_T3X_SMC911X_BASE + (16 << 20))
#define CONFIG_SMC911X_BASE	CM_T3X_SMC911X_BASE
#endif /* (CONFIG_CMD_NET) */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
					 CONFIG_SYS_INIT_RAM_SIZE -	\
					 GENERATED_GBL_DATA_SIZE)

/* Status LED */
#define CONFIG_STATUS_LED		/* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_GREEN		0
#define STATUS_LED_BIT			STATUS_LED_GREEN
#define STATUS_LED_STATE		STATUS_LED_ON
#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT			STATUS_LED_BIT
#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */

/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
36b4e2dd	1	/*
9fc376be	2	* (C) Copyright 2011 CompuLab, Ltd.
36b4e2dd	3	* Mike Rapoport <[email protected]>
dccd9a0b	4	* Igor Grinberg <[email protected]>
36b4e2dd MR	5	*
	6	* Based on omap3_beagle.h
	7	* (C) Copyright 2006-2008
	8	* Texas Instruments.
	9	* Richard Woodruff <[email protected]>
	10	* Syed Mohammed Khasim <[email protected]>
	11	*
b65a77a8	12	* Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
36b4e2dd MR	13	*
	14	* See file CREDITS for list of people who contributed to this
	15	* project.
	16	*
	17	* This program is free software; you can redistribute it and/or
	18	* modify it under the terms of the GNU General Public License as
	19	* published by the Free Software Foundation; either version 2 of
	20	* the License, or (at your option) any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; if not, write to the Free Software
dccd9a0b	29	* Foundation, Inc.
36b4e2dd MR	30	*/
	31
	32	#ifndef __CONFIG_H
	33	#define __CONFIG_H
	34
	35	/*
	36	* High Level Configuration Options
	37	*/
9fc376be NK	38	#define CONFIG_OMAP /* in a TI OMAP core */
9fc376be NK	39	#define CONFIG_OMAP34XX /* which is a 34XX */
308252ad	40	#define CONFIG_OMAP_GPIO
9fc376be	41	#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
36b4e2dd MR	42
	43	#define CONFIG_SYS_TEXT_BASE 0x80008000
	44
	45	#define CONFIG_SDRC /* The chip has SDRC controller */
	46
	47	#include <asm/arch/cpu.h> /* get chip and board defs */
	48	#include <asm/arch/omap3.h>
	49
	50	/*
	51	* Display CPU and Board information
	52	*/
9fc376be NK	53	#define CONFIG_DISPLAY_CPUINFO
9fc376be NK	54	#define CONFIG_DISPLAY_BOARDINFO
36b4e2dd MR	55
	56	/* Clock Defines */
	57	#define V_OSCK 26000000 /* Clock output from T2 */
	58	#define V_SCLK (V_OSCK >> 1)
	59
36b4e2dd MR	60	#define CONFIG_MISC_INIT_R
	61
	62	#define CONFIG_OF_LIBFDT 1
	63	/*
	64	* The early kernel mapping on ARM currently only maps from the base of DRAM
	65	* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
	66	* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
	67	* so that leaves DRAM base to DRAM base + 0x4000 available.
	68	*/
	69	#define CONFIG_SYS_BOOTMAPSZ 0x4000
	70
9fc376be NK	71	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	72	#define CONFIG_SETUP_MEMORY_TAGS
	73	#define CONFIG_INITRD_TAG
	74	#define CONFIG_REVISION_TAG
82309250	75	#define CONFIG_SERIAL_TAG
36b4e2dd MR	76
	77	/*
	78	* Size of malloc() pool
	79	*/
390cdcda	80	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
9fc376be NK	81	/* Sector */
9fc376be NK	82	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
36b4e2dd MR	83
	84	/*
	85	* Hardware drivers
	86	*/
	87
	88	/*
	89	* NS16550 Configuration
	90	*/
	91	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	92
	93	#define CONFIG_SYS_NS16550
	94	#define CONFIG_SYS_NS16550_SERIAL
	95	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	96	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	97
	98	/*
	99	* select serial console configuration
	100	*/
	101	#define CONFIG_CONS_INDEX 3
	102	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	103	#define CONFIG_SERIAL3 3 /* UART3 */
	104
	105	/* allow to overwrite serial and ethaddr */
	106	#define CONFIG_ENV_OVERWRITE
	107	#define CONFIG_BAUDRATE 115200
	108	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	109	115200}
9fc376be NK	110
	111	#define CONFIG_GENERIC_MMC
	112	#define CONFIG_MMC
	113	#define CONFIG_OMAP_HSMMC
	114	#define CONFIG_DOS_PARTITION
36b4e2dd	115
36b4e2dd	116	/* USB */
9fc376be NK	117	#define CONFIG_MUSB_UDC
	118	#define CONFIG_USB_OMAP3
	119	#define CONFIG_TWL4030_USB
36b4e2dd MR	120
36b4e2dd MR	121	/* USB device configuration */
9fc376be NK	122	#define CONFIG_USB_DEVICE
	123	#define CONFIG_USB_TTY
	124	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
36b4e2dd MR	125
	126	/* commands to include */
	127	#include <config_cmd_default.h>
	128
	129	#define CONFIG_CMD_CACHE
	130	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	131	#define CONFIG_CMD_FAT /* FAT support */
	132	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	133	#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
	134	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
9fc376be NK	135	#define MTDIDS_DEFAULT "nand0=nand"
	136	#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
	137	"1920k(u-boot),128k(u-boot-env),"\
	138	"4m(kernel),-(fs)"
36b4e2dd MR	139
	140	#define CONFIG_CMD_I2C /* I2C serial bus support */
	141	#define CONFIG_CMD_MMC /* MMC support */
	142	#define CONFIG_CMD_NAND /* NAND support */
	143	#define CONFIG_CMD_DHCP
	144	#define CONFIG_CMD_PING
	145
	146	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	147	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	148	#undef CONFIG_CMD_IMLS /* List all found images */
	149
	150	#define CONFIG_SYS_NO_FLASH
9fc376be	151	#define CONFIG_HARD_I2C
36b4e2dd MR	152	#define CONFIG_SYS_I2C_SPEED 100000
	153	#define CONFIG_SYS_I2C_SLAVE 1
	154	#define CONFIG_SYS_I2C_BUS 0
	155	#define CONFIG_SYS_I2C_BUS_SELECT 1
9fc376be	156	#define CONFIG_DRIVER_OMAP34XX_I2C
82309250 NK	157	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
82309250 NK	158	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
79874ae9	159	#define CONFIG_I2C_MULTI_BUS
36b4e2dd MR	160
	161	/*
	162	* TWL4030
	163	*/
9fc376be NK	164	#define CONFIG_TWL4030_POWER
9fc376be NK	165	#define CONFIG_TWL4030_LED
36b4e2dd MR	166
	167	/*
	168	* Board NAND Info.
	169	*/
9fc376be	170	#define CONFIG_SYS_NAND_QUIET_TEST
36b4e2dd MR	171	#define CONFIG_NAND_OMAP_GPMC
	172	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	173	/* to access nand */
	174	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	175	/* to access nand at */
	176	/* CS0 */
816e3921	177	#define GPMC_NAND_ECC_LP_x8_LAYOUT
36b4e2dd MR	178
	179	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	180	/* devices */
	181	#define CONFIG_JFFS2_NAND
	182	/* nand device jffs2 lives on */
	183	#define CONFIG_JFFS2_DEV "nand0"
	184	/* start of jffs2 partition */
	185	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	186	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	187	/* partition */
	188
	189	/* Environment information */
	190	#define CONFIG_BOOTDELAY 10
	191
	192	#define CONFIG_EXTRA_ENV_SETTINGS \
	193	"loadaddr=0x82000000\0" \
	194	"usbtty=cdc_acm\0" \
	195	"console=ttyS2,115200n8\0" \
	196	"mpurate=500\0" \
	197	"vram=12M\0" \
	198	"dvimode=1024x768MR-16@60\0" \
	199	"defaultdisplay=dvi\0" \
	200	"mmcdev=0\0" \
	201	"mmcroot=/dev/mmcblk0p2 rw\0" \
	202	"mmcrootfstype=ext3 rootwait\0" \
	203	"nandroot=/dev/mtdblock4 rw\0" \
	204	"nandrootfstype=jffs2\0" \
	205	"mmcargs=setenv bootargs console=${console} " \
	206	"mpurate=${mpurate} " \
	207	"vram=${vram} " \
	208	"omapfb.mode=dvi:${dvimode} " \
	209	"omapfb.debug=y " \
	210	"omapdss.def_disp=${defaultdisplay} " \
	211	"root=${mmcroot} " \
	212	"rootfstype=${mmcrootfstype}\0" \
	213	"nandargs=setenv bootargs console=${console} " \
	214	"mpurate=${mpurate} " \
	215	"vram=${vram} " \
	216	"omapfb.mode=dvi:${dvimode} " \
	217	"omapfb.debug=y " \
	218	"omapdss.def_disp=${defaultdisplay} " \
	219	"root=${nandroot} " \
	220	"rootfstype=${nandrootfstype}\0" \
	221	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	222	"bootscript=echo Running bootscript from mmc ...; " \
	223	"source ${loadaddr}\0" \
	224	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	225	"mmcboot=echo Booting from mmc ...; " \
	226	"run mmcargs; " \
	227	"bootm ${loadaddr}\0" \
	228	"nandboot=echo Booting from nand ...; " \
	229	"run nandargs; " \
	230	"nand read ${loadaddr} 280000 400000; " \
	231	"bootm ${loadaddr}\0" \
	232
	233	#define CONFIG_BOOTCOMMAND \
66968110	234	"mmc dev ${mmcdev}; if mmc rescan; then " \
36b4e2dd MR	235	"if run loadbootscript; then " \
	236	"run bootscript; " \
	237	"else " \
	238	"if run loaduimage; then " \
	239	"run mmcboot; " \
	240	"else run nandboot; " \
	241	"fi; " \
	242	"fi; " \
	243	"else run nandboot; fi"
	244
36b4e2dd MR	245	/*
	246	* Miscellaneous configurable options
	247	*/
41d7e702 IG	248	#define CONFIG_AUTO_COMPLETE
	249	#define CONFIG_CMDLINE_EDITING
	250	#define CONFIG_TIMESTAMP
9fc376be	251	#define CONFIG_SYS_AUTOLOAD "no"
36b4e2dd MR	252	#define CONFIG_SYS_LONGHELP /* undef to save memory */
36b4e2dd MR	253	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
b65a77a8	254	#define CONFIG_SYS_PROMPT "CM-T3x # "
36b4e2dd MR	255	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	256	/* Print Buffer Size */
	257	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	258	sizeof(CONFIG_SYS_PROMPT) + 16)
	259	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	260	/* Boot Argument Buffer Size */
	261	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	262
	263	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
	264	/* works on */
	265	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	266	0x01F00000) /* 31MB */
	267
	268	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	269	/* load address */
	270
	271	/*
	272	* OMAP3 has 12 GP timers, they can be driven by the system clock
	273	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	274	* This rate is divided by a local divisor.
	275	*/
	276	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	277	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	278	#define CONFIG_SYS_HZ 1000
	279
36b4e2dd MR	280	/*-----------------------------------------------------------------------
	281	* Physical Memory Map
	282	*/
	283	#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
	284	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	285	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
	286
36b4e2dd MR	287	/*-----------------------------------------------------------------------
	288	* FLASH and environment organization
	289	*/
	290
	291	/* ** PISMO SUPPORT * */
36b4e2dd MR	292	/* Configure the PISMO */
36b4e2dd MR	293	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
36b4e2dd MR	294
	295	/* Monitor at start of flash */
	296	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
3530a35d	297	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
36b4e2dd	298
9fc376be	299	#define CONFIG_ENV_IS_IN_NAND
36b4e2dd	300	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
6cbec7b3	301	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
36b4e2dd MR	302	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
36b4e2dd MR	303
36b4e2dd	304	#if defined(CONFIG_CMD_NET)
36b4e2dd MR	305	#define CONFIG_SMC911X
36b4e2dd MR	306	#define CONFIG_SMC911X_32_BIT
b65a77a8 IG	307	#define CM_T3X_SMC911X_BASE 0x2C000000
	308	#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
	309	#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
36b4e2dd MR	310	#endif /* (CONFIG_CMD_NET) */
	311
	312	/* additions for new relocation code, must be added to all boards */
	313	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	314	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	315	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	316	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	317	CONFIG_SYS_INIT_RAM_SIZE - \
	318	GENERATED_GBL_DATA_SIZE)
	319
2b8754b2	320	/* Status LED */
9fc376be NK	321	#define CONFIG_STATUS_LED /* Status LED enabled */
9fc376be NK	322	#define CONFIG_BOARD_SPECIFIC_LED
2b8754b2 IG	323	#define STATUS_LED_GREEN 0
	324	#define STATUS_LED_BIT STATUS_LED_GREEN
	325	#define STATUS_LED_STATE STATUS_LED_ON
	326	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
	327	#define STATUS_LED_BOOT STATUS_LED_BIT
	328	#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
	329
	330	/* GPIO banks */
	331	#ifdef CONFIG_STATUS_LED
9fc376be	332	#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
2b8754b2 IG	333	#endif
2b8754b2 IG	334
36b4e2dd	335	#endif /* __CONFIG_H */