[J-u-boot.git] / arch / arm / dts / stm32f429.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright 2015 - Maxime Coquelin <[email protected]>
 *
 */

#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_i2s_ckin: i2s-ckin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
	};

	soc {
		romem: efuse@1fff7800 {
			compatible = "st,stm32f4-otp";
			reg = <0x1fff7800 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ts_cal1: calib@22c {
				reg = <0x22c 0x2>;
			};
			ts_cal2: calib@22e {
				reg = <0x22e 0x2>;
			};
		};

		timers2: timers@40000000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@1 {
				compatible = "st,stm32-timer-trigger";
				reg = <1>;
				status = "disabled";
			};
		};

		timers3: timers@40000400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40000400 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@2 {
				compatible = "st,stm32-timer-trigger";
				reg = <2>;
				status = "disabled";
			};
		};

		timers4: timers@40000800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40000800 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@3 {
				compatible = "st,stm32-timer-trigger";
				reg = <3>;
				status = "disabled";
			};
		};

		timers5: timers@40000c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40000C00 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@4 {
				compatible = "st,stm32-timer-trigger";
				reg = <4>;
				status = "disabled";
			};
		};

		timers6: timers@40001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
			clock-names = "int";
			status = "disabled";

			timer@5 {
				compatible = "st,stm32-timer-trigger";
				reg = <5>;
				status = "disabled";
			};
		};

		timers7: timers@40001400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
			clock-names = "int";
			status = "disabled";

			timer@6 {
				compatible = "st,stm32-timer-trigger";
				reg = <6>;
				status = "disabled";
			};
		};

		timers12: timers@40001800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40001800 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@11 {
				compatible = "st,stm32-timer-trigger";
				reg = <11>;
				status = "disabled";
			};
		};

		timers13: timers@40001c00 {
			compatible = "st,stm32-timers";
			reg = <0x40001C00 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		timers14: timers@40002000 {
			compatible = "st,stm32-timers";
			reg = <0x40002000 0x400>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		rtc: rtc@40002800 {
			compatible = "st,stm32-rtc";
			reg = <0x40002800 0x400>;
			clocks = <&rcc 1 CLK_RTC>;
			assigned-clocks = <&rcc 1 CLK_RTC>;
			assigned-clock-parents = <&rcc 1 CLK_LSE>;
			interrupt-parent = <&exti>;
			interrupts = <17 1>;
			st,syscfg = <&pwrcfg 0x00 0x100>;
			status = "disabled";
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-iwdg";
			reg = <0x40003000 0x400>;
			clocks = <&clk_lsi>;
			clock-names = "lsi";
			status = "disabled";
		};

		spi2: spi@40003800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32f4-spi";
			reg = <0x40003800 0x400>;
			interrupts = <36>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
			status = "disabled";
		};

		spi3: spi@40003c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32f4-spi";
			reg = <0x40003c00 0x400>;
			interrupts = <51>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-uart";
			reg = <0x40004400 0x400>;
			interrupts = <38>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
			status = "disabled";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-uart";
			reg = <0x40004800 0x400>;
			interrupts = <39>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
			status = "disabled";
			dmas = <&dma1 1 4 0x400 0x0>,
			       <&dma1 3 4 0x400 0x0>;
			dma-names = "rx", "tx";
		};

		usart4: serial@40004c00 {
			compatible = "st,stm32-uart";
			reg = <0x40004c00 0x400>;
			interrupts = <52>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
			status = "disabled";
		};

		usart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			interrupts = <53>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
			status = "disabled";
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32f4-i2c";
			reg = <0x40005400 0x400>;
			interrupts = <31>,
				     <32>;
			resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@40005c00 {
			compatible = "st,stm32f4-i2c";
			reg = <0x40005c00 0x400>;
			interrupts = <72>,
				     <73>;
			resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can1: can@40006400 {
			compatible = "st,stm32f4-bxcan";
			reg = <0x40006400 0x200>;
			interrupts = <19>, <20>, <21>, <22>;
			interrupt-names = "tx", "rx0", "rx1", "sce";
			resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
			st,can-primary;
			st,gcan = <&gcan>;
			status = "disabled";
		};

		gcan: gcan@40006600 {
			compatible = "st,stm32f4-gcan", "syscon";
			reg = <0x40006600 0x200>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
		};

		can2: can@40006800 {
			compatible = "st,stm32f4-bxcan";
			reg = <0x40006800 0x200>;
			interrupts = <63>, <64>, <65>, <66>;
			interrupt-names = "tx", "rx0", "rx1", "sce";
			resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
			st,can-secondary;
			st,gcan = <&gcan>;
			status = "disabled";
		};

		dac: dac@40007400 {
			compatible = "st,stm32f4-dac-core";
			reg = <0x40007400 0x400>;
			resets = <&rcc STM32F4_APB1_RESET(DAC)>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
			clock-names = "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			dac1: dac@1 {
				compatible = "st,stm32-dac";
				#io-channel-cells = <1>;
				reg = <1>;
				status = "disabled";
			};

			dac2: dac@2 {
				compatible = "st,stm32-dac";
				#io-channel-cells = <1>;
				reg = <2>;
				status = "disabled";
			};
		};

		usart7: serial@40007800 {
			compatible = "st,stm32-uart";
			reg = <0x40007800 0x400>;
			interrupts = <82>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
			status = "disabled";
		};

		usart8: serial@40007c00 {
			compatible = "st,stm32-uart";
			reg = <0x40007c00 0x400>;
			interrupts = <83>;
			clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
			status = "disabled";
		};

		timers1: timers@40010000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40010000 0x400>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@0 {
				compatible = "st,stm32-timer-trigger";
				reg = <0>;
				status = "disabled";
			};
		};

		timers8: timers@40010400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40010400 0x400>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@7 {
				compatible = "st,stm32-timer-trigger";
				reg = <7>;
				status = "disabled";
			};
		};

		usart1: serial@40011000 {
			compatible = "st,stm32-uart";
			reg = <0x40011000 0x400>;
			interrupts = <37>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
			status = "disabled";
			dmas = <&dma2 2 4 0x400 0x0>,
			       <&dma2 7 4 0x400 0x0>;
			dma-names = "rx", "tx";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-uart";
			reg = <0x40011400 0x400>;
			interrupts = <71>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
			status = "disabled";
		};

		adc: adc@40012000 {
			compatible = "st,stm32f4-adc-core";
			reg = <0x40012000 0x400>;
			interrupts = <18>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
			clock-names = "adc";
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			adc1: adc@0 {
				compatible = "st,stm32f4-adc";
				#io-channel-cells = <1>;
				reg = <0x0>;
				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
				interrupt-parent = <&adc>;
				interrupts = <0>;
				dmas = <&dma2 0 0 0x400 0x0>;
				dma-names = "rx";
				status = "disabled";
			};

			adc2: adc@100 {
				compatible = "st,stm32f4-adc";
				#io-channel-cells = <1>;
				reg = <0x100>;
				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
				interrupt-parent = <&adc>;
				interrupts = <1>;
				dmas = <&dma2 3 1 0x400 0x0>;
				dma-names = "rx";
				status = "disabled";
			};

			adc3: adc@200 {
				compatible = "st,stm32f4-adc";
				#io-channel-cells = <1>;
				reg = <0x200>;
				clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
				interrupt-parent = <&adc>;
				interrupts = <2>;
				dmas = <&dma2 1 2 0x400 0x0>;
				dma-names = "rx";
				status = "disabled";
			};
		};

		sdio: mmc@40012c00 {
			compatible = "arm,pl180", "arm,primecell";
			arm,primecell-periphid = <0x00880180>;
			reg = <0x40012c00 0x400>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
			clock-names = "apb_pclk";
			interrupts = <49>;
			max-frequency = <48000000>;
			status = "disabled";
		};

		spi1: spi@40013000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32f4-spi";
			reg = <0x40013000 0x400>;
			interrupts = <35>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
			status = "disabled";
		};

		spi4: spi@40013400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32f4-spi";
			reg = <0x40013400 0x400>;
			interrupts = <84>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
			status = "disabled";
		};

		syscfg: syscon@40013800 {
			compatible = "st,stm32-syscfg", "syscon";
			reg = <0x40013800 0x400>;
		};

		exti: interrupt-controller@40013c00 {
			compatible = "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x40013C00 0x400>;
			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
		};

		timers9: timers@40014000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40014000 0x400>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@8 {
				compatible = "st,stm32-timer-trigger";
				reg = <8>;
				status = "disabled";
			};
		};

		timers10: timers@40014400 {
			compatible = "st,stm32-timers";
			reg = <0x40014400 0x400>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		timers11: timers@40014800 {
			compatible = "st,stm32-timers";
			reg = <0x40014800 0x400>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
			clock-names = "int";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};
		};

		spi5: spi@40015000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32f4-spi";
			reg = <0x40015000 0x400>;
			interrupts = <85>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
			dmas = <&dma2 3 2 0x400 0x0>,
				<&dma2 4 2 0x400 0x0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		spi6: spi@40015400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32f4-spi";
			reg = <0x40015400 0x400>;
			interrupts = <86>;
			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
			status = "disabled";
		};

		pwrcfg: power-config@40007000 {
			compatible = "st,stm32-power-config", "syscon";
			reg = <0x40007000 0x400>;
		};

		ltdc: display-controller@40016800 {
			compatible = "st,stm32-ltdc";
			reg = <0x40016800 0x200>;
			interrupts = <88>, <89>;
			resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
			clocks = <&rcc 1 CLK_LCD>;
			clock-names = "lcd";
			status = "disabled";
		};

		crc: crc@40023000 {
			compatible = "st,stm32f4-crc";
			reg = <0x40023000 0x400>;
			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
			status = "disabled";
		};

		rcc: rcc@40023800 {
			#reset-cells = <1>;
			#clock-cells = <2>;
			compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
			reg = <0x40023800 0x400>;
			clocks = <&clk_hse>, <&clk_i2s_ckin>;
			st,syscfg = <&pwrcfg>;
			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
			assigned-clock-rates = <1000000>;
		};

		dma1: dma-controller@40026000 {
			compatible = "st,stm32-dma";
			reg = <0x40026000 0x400>;
			interrupts = <11>,
				     <12>,
				     <13>,
				     <14>,
				     <15>,
				     <16>,
				     <17>,
				     <47>;
			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
			#dma-cells = <4>;
		};

		dma2: dma-controller@40026400 {
			compatible = "st,stm32-dma";
			reg = <0x40026400 0x400>;
			interrupts = <56>,
				     <57>,
				     <58>,
				     <59>,
				     <60>,
				     <68>,
				     <69>,
				     <70>;
			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
			#dma-cells = <4>;
			st,mem2mem;
		};

		mac: ethernet@40028000 {
			compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
			reg = <0x40028000 0x8000>;
			reg-names = "stmmaceth";
			interrupts = <61>;
			interrupt-names = "macirq";
			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
					<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
			st,syscon = <&syscfg 0x4>;
			snps,pbl = <8>;
			snps,mixed-burst;
			status = "disabled";
		};

		dma2d: dma2d@4002b000 {
			compatible = "st,stm32-dma2d";
			reg = <0x4002b000 0xc00>;
			interrupts = <90>;
			resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
			clock-names = "dma2d";
			status = "disabled";
		};

		usbotg_hs: usb@40040000 {
			compatible = "snps,dwc2";
			reg = <0x40040000 0x40000>;
			interrupts = <77>;
			clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
			clock-names = "otg";
			status = "disabled";
		};

		usbotg_fs: usb@50000000 {
			compatible = "st,stm32f4x9-fsotg";
			reg = <0x50000000 0x40000>;
			interrupts = <67>;
			clocks = <&rcc 0 39>;
			clock-names = "otg";
			status = "disabled";
		};

		dcmi: dcmi@50050000 {
			compatible = "st,stm32-dcmi";
			reg = <0x50050000 0x400>;
			interrupts = <78>;
			resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
			clock-names = "mclk";
			pinctrl-names = "default";
			pinctrl-0 = <&dcmi_pins>;
			dmas = <&dma2 1 1 0x414 0x3>;
			dma-names = "tx";
			status = "disabled";
		};

		rng: rng@50060800 {
			compatible = "st,stm32-rng";
			reg = <0x50060800 0x400>;
			clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;

		};
	};
};

&systick {
	clocks = <&rcc 1 SYSTICK>;
	status = "okay";
};
Commit	Line	Data
e07a86b5	1	// SPDX-License-Identifier: GPL-2.0+ OR X11
46b1e54b	2	/*
71dfd5f3	3	* Copyright 2015 - Maxime Coquelin <[email protected]>
46b1e54b	4	*
46b1e54b PC	5	*/
46b1e54b PC	6
46b1e54b PC	7	#include "armv7-m.dtsi"
	8	#include <dt-bindings/clock/stm32fx-clock.h>
	9	#include <dt-bindings/mfd/stm32f4-rcc.h>
	10
	11	/ {
e07a86b5 PD	12	#address-cells = <1>;
	13	#size-cells = <1>;
	14
46b1e54b PC	15	clocks {
	16	clk_hse: clk-hse {
	17	#clock-cells = <0>;
	18	compatible = "fixed-clock";
	19	clock-frequency = <0>;
	20	};
	21
	22	clk_lse: clk-lse {
	23	#clock-cells = <0>;
	24	compatible = "fixed-clock";
	25	clock-frequency = <32768>;
	26	};
	27
	28	clk_lsi: clk-lsi {
	29	#clock-cells = <0>;
	30	compatible = "fixed-clock";
	31	clock-frequency = <32000>;
	32	};
	33
	34	clk_i2s_ckin: i2s-ckin {
	35	#clock-cells = <0>;
	36	compatible = "fixed-clock";
	37	clock-frequency = <0>;
	38	};
	39	};
	40
	41	soc {
61c88ace	42	romem: efuse@1fff7800 {
e07a86b5 PD	43	compatible = "st,stm32f4-otp";
	44	reg = <0x1fff7800 0x400>;
	45	#address-cells = <1>;
	46	#size-cells = <1>;
	47	ts_cal1: calib@22c {
	48	reg = <0x22c 0x2>;
	49	};
	50	ts_cal2: calib@22e {
	51	reg = <0x22e 0x2>;
	52	};
	53	};
	54
46b1e54b PC	55	timers2: timers@40000000 {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58	compatible = "st,stm32-timers";
	59	reg = <0x40000000 0x400>;
	60	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
	61	clock-names = "int";
	62	status = "disabled";
	63
	64	pwm {
	65	compatible = "st,stm32-pwm";
62d620c2	66	#pwm-cells = <3>;
46b1e54b PC	67	status = "disabled";
	68	};
	69
	70	timer@1 {
	71	compatible = "st,stm32-timer-trigger";
	72	reg = <1>;
	73	status = "disabled";
	74	};
	75	};
	76
46b1e54b PC	77	timers3: timers@40000400 {
	78	#address-cells = <1>;
	79	#size-cells = <0>;
	80	compatible = "st,stm32-timers";
	81	reg = <0x40000400 0x400>;
	82	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
	83	clock-names = "int";
	84	status = "disabled";
	85
	86	pwm {
	87	compatible = "st,stm32-pwm";
62d620c2	88	#pwm-cells = <3>;
46b1e54b PC	89	status = "disabled";
	90	};
	91
	92	timer@2 {
	93	compatible = "st,stm32-timer-trigger";
	94	reg = <2>;
	95	status = "disabled";
	96	};
	97	};
	98
46b1e54b PC	99	timers4: timers@40000800 {
	100	#address-cells = <1>;
	101	#size-cells = <0>;
	102	compatible = "st,stm32-timers";
	103	reg = <0x40000800 0x400>;
	104	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
	105	clock-names = "int";
	106	status = "disabled";
	107
	108	pwm {
	109	compatible = "st,stm32-pwm";
62d620c2	110	#pwm-cells = <3>;
46b1e54b PC	111	status = "disabled";
	112	};
	113
	114	timer@3 {
	115	compatible = "st,stm32-timer-trigger";
	116	reg = <3>;
	117	status = "disabled";
	118	};
	119	};
	120
46b1e54b PC	121	timers5: timers@40000c00 {
	122	#address-cells = <1>;
	123	#size-cells = <0>;
	124	compatible = "st,stm32-timers";
	125	reg = <0x40000C00 0x400>;
	126	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
	127	clock-names = "int";
	128	status = "disabled";
	129
	130	pwm {
	131	compatible = "st,stm32-pwm";
62d620c2	132	#pwm-cells = <3>;
46b1e54b PC	133	status = "disabled";
	134	};
	135
	136	timer@4 {
	137	compatible = "st,stm32-timer-trigger";
	138	reg = <4>;
	139	status = "disabled";
	140	};
	141	};
	142
46b1e54b PC	143	timers6: timers@40001000 {
	144	#address-cells = <1>;
	145	#size-cells = <0>;
	146	compatible = "st,stm32-timers";
	147	reg = <0x40001000 0x400>;
	148	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
	149	clock-names = "int";
	150	status = "disabled";
	151
	152	timer@5 {
	153	compatible = "st,stm32-timer-trigger";
	154	reg = <5>;
	155	status = "disabled";
	156	};
	157	};
	158
46b1e54b PC	159	timers7: timers@40001400 {
	160	#address-cells = <1>;
	161	#size-cells = <0>;
	162	compatible = "st,stm32-timers";
	163	reg = <0x40001400 0x400>;
	164	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
	165	clock-names = "int";
	166	status = "disabled";
	167
	168	timer@6 {
	169	compatible = "st,stm32-timer-trigger";
	170	reg = <6>;
	171	status = "disabled";
	172	};
	173	};
	174
	175	timers12: timers@40001800 {
	176	#address-cells = <1>;
	177	#size-cells = <0>;
	178	compatible = "st,stm32-timers";
	179	reg = <0x40001800 0x400>;
	180	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
	181	clock-names = "int";
	182	status = "disabled";
	183
	184	pwm {
	185	compatible = "st,stm32-pwm";
62d620c2	186	#pwm-cells = <3>;
46b1e54b PC	187	status = "disabled";
	188	};
	189
	190	timer@11 {
	191	compatible = "st,stm32-timer-trigger";
	192	reg = <11>;
	193	status = "disabled";
	194	};
	195	};
	196
	197	timers13: timers@40001c00 {
46b1e54b PC	198	compatible = "st,stm32-timers";
	199	reg = <0x40001C00 0x400>;
	200	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
	201	clock-names = "int";
	202	status = "disabled";
	203
	204	pwm {
	205	compatible = "st,stm32-pwm";
62d620c2	206	#pwm-cells = <3>;
46b1e54b PC	207	status = "disabled";
	208	};
	209	};
	210
	211	timers14: timers@40002000 {
46b1e54b PC	212	compatible = "st,stm32-timers";
	213	reg = <0x40002000 0x400>;
	214	clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
	215	clock-names = "int";
	216	status = "disabled";
	217
	218	pwm {
	219	compatible = "st,stm32-pwm";
62d620c2	220	#pwm-cells = <3>;
46b1e54b PC	221	status = "disabled";
	222	};
	223	};
	224
	225	rtc: rtc@40002800 {
	226	compatible = "st,stm32-rtc";
	227	reg = <0x40002800 0x400>;
	228	clocks = <&rcc 1 CLK_RTC>;
46b1e54b PC	229	assigned-clocks = <&rcc 1 CLK_RTC>;
	230	assigned-clock-parents = <&rcc 1 CLK_LSE>;
	231	interrupt-parent = <&exti>;
	232	interrupts = <17 1>;
71dfd5f3	233	st,syscfg = <&pwrcfg 0x00 0x100>;
46b1e54b PC	234	status = "disabled";
	235	};
	236
	237	iwdg: watchdog@40003000 {
	238	compatible = "st,stm32-iwdg";
	239	reg = <0x40003000 0x400>;
	240	clocks = <&clk_lsi>;
71dfd5f3	241	clock-names = "lsi";
46b1e54b PC	242	status = "disabled";
	243	};
	244
e07a86b5 PD	245	spi2: spi@40003800 {
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	compatible = "st,stm32f4-spi";
	249	reg = <0x40003800 0x400>;
	250	interrupts = <36>;
	251	clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
	252	status = "disabled";
	253	};
	254
	255	spi3: spi@40003c00 {
	256	#address-cells = <1>;
	257	#size-cells = <0>;
	258	compatible = "st,stm32f4-spi";
	259	reg = <0x40003c00 0x400>;
	260	interrupts = <51>;
	261	clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
	262	status = "disabled";
	263	};
	264
46b1e54b PC	265	usart2: serial@40004400 {
	266	compatible = "st,stm32-uart";
	267	reg = <0x40004400 0x400>;
	268	interrupts = <38>;
	269	clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
	270	status = "disabled";
	271	};
	272
	273	usart3: serial@40004800 {
	274	compatible = "st,stm32-uart";
	275	reg = <0x40004800 0x400>;
	276	interrupts = <39>;
	277	clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
	278	status = "disabled";
	279	dmas = <&dma1 1 4 0x400 0x0>,
	280	<&dma1 3 4 0x400 0x0>;
	281	dma-names = "rx", "tx";
	282	};
	283
	284	usart4: serial@40004c00 {
	285	compatible = "st,stm32-uart";
	286	reg = <0x40004c00 0x400>;
	287	interrupts = <52>;
	288	clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
	289	status = "disabled";
	290	};
	291
	292	usart5: serial@40005000 {
	293	compatible = "st,stm32-uart";
	294	reg = <0x40005000 0x400>;
	295	interrupts = <53>;
	296	clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
	297	status = "disabled";
	298	};
	299
	300	i2c1: i2c@40005400 {
	301	compatible = "st,stm32f4-i2c";
	302	reg = <0x40005400 0x400>;
	303	interrupts = <31>,
	304	<32>;
	305	resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
	306	clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
	307	#address-cells = <1>;
	308	#size-cells = <0>;
	309	status = "disabled";
	310	};
	311
61c88ace PC	312	i2c3: i2c@40005c00 {
	313	compatible = "st,stm32f4-i2c";
	314	reg = <0x40005c00 0x400>;
	315	interrupts = <72>,
	316	<73>;
	317	resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
	318	clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321	status = "disabled";
	322	};
	323
78692e51 DB	324	can1: can@40006400 {
	325	compatible = "st,stm32f4-bxcan";
	326	reg = <0x40006400 0x200>;
	327	interrupts = <19>, <20>, <21>, <22>;
	328	interrupt-names = "tx", "rx0", "rx1", "sce";
	329	resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
	330	clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
	331	st,can-primary;
	332	st,gcan = <&gcan>;
	333	status = "disabled";
	334	};
	335
	336	gcan: gcan@40006600 {
	337	compatible = "st,stm32f4-gcan", "syscon";
	338	reg = <0x40006600 0x200>;
	339	clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
	340	};
	341
	342	can2: can@40006800 {
	343	compatible = "st,stm32f4-bxcan";
	344	reg = <0x40006800 0x200>;
	345	interrupts = <63>, <64>, <65>, <66>;
	346	interrupt-names = "tx", "rx0", "rx1", "sce";
	347	resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
	348	clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
388f8726	349	st,can-secondary;
78692e51 DB	350	st,gcan = <&gcan>;
	351	status = "disabled";
	352	};
	353
46b1e54b PC	354	dac: dac@40007400 {
	355	compatible = "st,stm32f4-dac-core";
	356	reg = <0x40007400 0x400>;
	357	resets = <&rcc STM32F4_APB1_RESET(DAC)>;
	358	clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
	359	clock-names = "pclk";
	360	#address-cells = <1>;
	361	#size-cells = <0>;
	362	status = "disabled";
	363
	364	dac1: dac@1 {
	365	compatible = "st,stm32-dac";
61c88ace	366	#io-channel-cells = <1>;
46b1e54b PC	367	reg = <1>;
	368	status = "disabled";
	369	};
	370
	371	dac2: dac@2 {
	372	compatible = "st,stm32-dac";
61c88ace	373	#io-channel-cells = <1>;
46b1e54b PC	374	reg = <2>;
	375	status = "disabled";
	376	};
	377	};
	378
	379	usart7: serial@40007800 {
	380	compatible = "st,stm32-uart";
	381	reg = <0x40007800 0x400>;
	382	interrupts = <82>;
	383	clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
	384	status = "disabled";
	385	};
	386
	387	usart8: serial@40007c00 {
	388	compatible = "st,stm32-uart";
	389	reg = <0x40007c00 0x400>;
	390	interrupts = <83>;
	391	clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
	392	status = "disabled";
	393	};
	394
	395	timers1: timers@40010000 {
	396	#address-cells = <1>;
	397	#size-cells = <0>;
	398	compatible = "st,stm32-timers";
	399	reg = <0x40010000 0x400>;
	400	clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
	401	clock-names = "int";
	402	status = "disabled";
	403
	404	pwm {
	405	compatible = "st,stm32-pwm";
62d620c2	406	#pwm-cells = <3>;
46b1e54b PC	407	status = "disabled";
	408	};
	409
	410	timer@0 {
	411	compatible = "st,stm32-timer-trigger";
	412	reg = <0>;
	413	status = "disabled";
	414	};
	415	};
	416
	417	timers8: timers@40010400 {
	418	#address-cells = <1>;
	419	#size-cells = <0>;
	420	compatible = "st,stm32-timers";
	421	reg = <0x40010400 0x400>;
	422	clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
	423	clock-names = "int";
	424	status = "disabled";
	425
	426	pwm {
	427	compatible = "st,stm32-pwm";
62d620c2	428	#pwm-cells = <3>;
46b1e54b PC	429	status = "disabled";
	430	};
	431
	432	timer@7 {
	433	compatible = "st,stm32-timer-trigger";
	434	reg = <7>;
	435	status = "disabled";
	436	};
	437	};
	438
	439	usart1: serial@40011000 {
	440	compatible = "st,stm32-uart";
	441	reg = <0x40011000 0x400>;
	442	interrupts = <37>;
	443	clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
	444	status = "disabled";
	445	dmas = <&dma2 2 4 0x400 0x0>,
	446	<&dma2 7 4 0x400 0x0>;
	447	dma-names = "rx", "tx";
	448	};
	449
	450	usart6: serial@40011400 {
	451	compatible = "st,stm32-uart";
	452	reg = <0x40011400 0x400>;
	453	interrupts = <71>;
	454	clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
	455	status = "disabled";
	456	};
	457
	458	adc: adc@40012000 {
	459	compatible = "st,stm32f4-adc-core";
	460	reg = <0x40012000 0x400>;
	461	interrupts = <18>;
	462	clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
	463	clock-names = "adc";
	464	interrupt-controller;
	465	#interrupt-cells = <1>;
	466	#address-cells = <1>;
	467	#size-cells = <0>;
	468	status = "disabled";
	469
	470	adc1: adc@0 {
	471	compatible = "st,stm32f4-adc";
	472	#io-channel-cells = <1>;
	473	reg = <0x0>;
	474	clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
	475	interrupt-parent = <&adc>;
	476	interrupts = <0>;
	477	dmas = <&dma2 0 0 0x400 0x0>;
	478	dma-names = "rx";
	479	status = "disabled";
	480	};
	481
	482	adc2: adc@100 {
	483	compatible = "st,stm32f4-adc";
	484	#io-channel-cells = <1>;
	485	reg = <0x100>;
	486	clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
	487	interrupt-parent = <&adc>;
	488	interrupts = <1>;
	489	dmas = <&dma2 3 1 0x400 0x0>;
	490	dma-names = "rx";
	491	status = "disabled";
	492	};
493
494	adc3: adc@200 {
495	compatible = "st,stm32f4-adc";
496	#io-channel-cells = <1>;
497	reg = <0x200>;
498	clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
499	interrupt-parent = <&adc>;
500	interrupts = <2>;
501	dmas = <&dma2 1 2 0x400 0x0>;
502	dma-names = "rx";
503	status = "disabled";
504	};
505	};
506
9f603e2f	507	sdio: mmc@40012c00 {
71dfd5f3 PC	508	compatible = "arm,pl180", "arm,primecell";
	509	arm,primecell-periphid = <0x00880180>;
	510	reg = <0x40012c00 0x400>;
	511	clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
	512	clock-names = "apb_pclk";
	513	interrupts = <49>;
	514	max-frequency = <48000000>;
	515	status = "disabled";
	516	};
	517
e07a86b5 PD	518	spi1: spi@40013000 {
	519	#address-cells = <1>;
	520	#size-cells = <0>;
	521	compatible = "st,stm32f4-spi";
	522	reg = <0x40013000 0x400>;
	523	interrupts = <35>;
	524	clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
	525	status = "disabled";
	526	};
	527
	528	spi4: spi@40013400 {
	529	#address-cells = <1>;
	530	#size-cells = <0>;
	531	compatible = "st,stm32f4-spi";
	532	reg = <0x40013400 0x400>;
	533	interrupts = <84>;
	534	clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
	535	status = "disabled";
	536	};
	537
61c88ace PC	538	syscfg: syscon@40013800 {
61c88ace PC	539	compatible = "st,stm32-syscfg", "syscon";
46b1e54b PC	540	reg = <0x40013800 0x400>;
	541	};
	542
	543	exti: interrupt-controller@40013c00 {
	544	compatible = "st,stm32-exti";
	545	interrupt-controller;
	546	#interrupt-cells = <2>;
	547	reg = <0x40013C00 0x400>;
	548	interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
	549	};
	550
	551	timers9: timers@40014000 {
	552	#address-cells = <1>;
	553	#size-cells = <0>;
	554	compatible = "st,stm32-timers";
	555	reg = <0x40014000 0x400>;
	556	clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
	557	clock-names = "int";
	558	status = "disabled";
	559
	560	pwm {
	561	compatible = "st,stm32-pwm";
62d620c2	562	#pwm-cells = <3>;
46b1e54b PC	563	status = "disabled";
	564	};
	565
	566	timer@8 {
	567	compatible = "st,stm32-timer-trigger";
	568	reg = <8>;
	569	status = "disabled";
	570	};
	571	};
	572
	573	timers10: timers@40014400 {
46b1e54b PC	574	compatible = "st,stm32-timers";
	575	reg = <0x40014400 0x400>;
	576	clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
	577	clock-names = "int";
	578	status = "disabled";
	579
	580	pwm {
	581	compatible = "st,stm32-pwm";
62d620c2	582	#pwm-cells = <3>;
46b1e54b PC	583	status = "disabled";
	584	};
	585	};
	586
	587	timers11: timers@40014800 {
46b1e54b PC	588	compatible = "st,stm32-timers";
	589	reg = <0x40014800 0x400>;
	590	clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
	591	clock-names = "int";
	592	status = "disabled";
	593
	594	pwm {
	595	compatible = "st,stm32-pwm";
62d620c2	596	#pwm-cells = <3>;
46b1e54b PC	597	status = "disabled";
	598	};
	599	};
	600
e07a86b5 PD	601	spi5: spi@40015000 {
	602	#address-cells = <1>;
	603	#size-cells = <0>;
	604	compatible = "st,stm32f4-spi";
	605	reg = <0x40015000 0x400>;
	606	interrupts = <85>;
	607	clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
61c88ace PC	608	dmas = <&dma2 3 2 0x400 0x0>,
	609	<&dma2 4 2 0x400 0x0>;
	610	dma-names = "rx", "tx";
e07a86b5 PD	611	status = "disabled";
	612	};
	613
	614	spi6: spi@40015400 {
	615	#address-cells = <1>;
	616	#size-cells = <0>;
	617	compatible = "st,stm32f4-spi";
	618	reg = <0x40015400 0x400>;
	619	interrupts = <86>;
	620	clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
	621	status = "disabled";
	622	};
	623
46b1e54b	624	pwrcfg: power-config@40007000 {
61c88ace	625	compatible = "st,stm32-power-config", "syscon";
46b1e54b PC	626	reg = <0x40007000 0x400>;
	627	};
	628
	629	ltdc: display-controller@40016800 {
	630	compatible = "st,stm32-ltdc";
	631	reg = <0x40016800 0x200>;
	632	interrupts = <88>, <89>;
	633	resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
	634	clocks = <&rcc 1 CLK_LCD>;
	635	clock-names = "lcd";
	636	status = "disabled";
	637	};
	638
	639	crc: crc@40023000 {
	640	compatible = "st,stm32f4-crc";
	641	reg = <0x40023000 0x400>;
	642	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
	643	status = "disabled";
	644	};
	645
9f603e2f	646	rcc: rcc@40023800 {
46b1e54b PC	647	#reset-cells = <1>;
	648	#clock-cells = <2>;
	649	compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
	650	reg = <0x40023800 0x400>;
	651	clocks = <&clk_hse>, <&clk_i2s_ckin>;
	652	st,syscfg = <&pwrcfg>;
	653	assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
	654	assigned-clock-rates = <1000000>;
	655	};
	656
	657	dma1: dma-controller@40026000 {
	658	compatible = "st,stm32-dma";
	659	reg = <0x40026000 0x400>;
	660	interrupts = <11>,
	661	<12>,
	662	<13>,
	663	<14>,
	664	<15>,
	665	<16>,
	666	<17>,
	667	<47>;
	668	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
	669	#dma-cells = <4>;
	670	};
	671
	672	dma2: dma-controller@40026400 {
	673	compatible = "st,stm32-dma";
	674	reg = <0x40026400 0x400>;
	675	interrupts = <56>,
	676	<57>,
	677	<58>,
	678	<59>,
	679	<60>,
	680	<68>,
	681	<69>,
	682	<70>;
	683	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
	684	#dma-cells = <4>;
	685	st,mem2mem;
	686	};
	687
	688	mac: ethernet@40028000 {
	689	compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
	690	reg = <0x40028000 0x8000>;
	691	reg-names = "stmmaceth";
	692	interrupts = <61>;
	693	interrupt-names = "macirq";
	694	clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
	695	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
	696	<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
	697	<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
	698	st,syscon = <&syscfg 0x4>;
	699	snps,pbl = <8>;
	700	snps,mixed-burst;
	701	status = "disabled";
	702	};
	703
9f603e2f PC	704	dma2d: dma2d@4002b000 {
	705	compatible = "st,stm32-dma2d";
	706	reg = <0x4002b000 0xc00>;
	707	interrupts = <90>;
	708	resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
	709	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
	710	clock-names = "dma2d";
	711	status = "disabled";
	712	};
	713
46b1e54b PC	714	usbotg_hs: usb@40040000 {
	715	compatible = "snps,dwc2";
	716	reg = <0x40040000 0x40000>;
	717	interrupts = <77>;
	718	clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
	719	clock-names = "otg";
	720	status = "disabled";
	721	};
	722
	723	usbotg_fs: usb@50000000 {
	724	compatible = "st,stm32f4x9-fsotg";
	725	reg = <0x50000000 0x40000>;
	726	interrupts = <67>;
	727	clocks = <&rcc 0 39>;
	728	clock-names = "otg";
	729	status = "disabled";
	730	};
	731
	732	dcmi: dcmi@50050000 {
	733	compatible = "st,stm32-dcmi";
	734	reg = <0x50050000 0x400>;
	735	interrupts = <78>;
	736	resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
	737	clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
	738	clock-names = "mclk";
	739	pinctrl-names = "default";
	740	pinctrl-0 = <&dcmi_pins>;
	741	dmas = <&dma2 1 1 0x414 0x3>;
	742	dma-names = "tx";
	743	status = "disabled";
	744	};
	745
	746	rng: rng@50060800 {
	747	compatible = "st,stm32-rng";
	748	reg = <0x50060800 0x400>;
46b1e54b PC	749	clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
	750
	751	};
	752	};
	753	};
	754
	755	&systick {
	756	clocks = <&rcc 1 SYSTICK>;
	757	status = "okay";
	758	};