[J-u-boot.git] / drivers / usb / host / xhci-dwc3.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * DWC3 controller driver
 *
 * Author: Ramneek Mehresh<[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <generic-phy.h>
#include <log.h>
#include <usb.h>
#include <dwc3-uboot.h>
#include <linux/delay.h>

#include <usb/xhci.h>
#include <asm/io.h>
#include <linux/usb/dwc3.h>
#include <linux/usb/otg.h>

struct xhci_dwc3_platdata {
	struct phy_bulk phys;
};

void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
	clrsetbits_le32(&dwc3_reg->g_ctl,
			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
			DWC3_GCTL_PRTCAPDIR(mode));
}

static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
{
	/* Assert USB3 PHY reset */
	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);

	/* Assert USB2 PHY reset */
	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);

	mdelay(100);

	/* Clear USB3 PHY reset */
	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);

	/* Clear USB2 PHY reset */
	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
}

void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
	/* Before Resetting PHY, put Core in Reset */
	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);

	/* reset USB3 phy - if required */
	dwc3_phy_reset(dwc3_reg);

	mdelay(100);

	/* After PHYs are stable we can take Core out of reset state */
	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}

int dwc3_core_init(struct dwc3 *dwc3_reg)
{
	u32 reg;
	u32 revision;
	unsigned int dwc3_hwparams1;

	revision = readl(&dwc3_reg->g_snpsid);
	/* This should read as U3 followed by revision number */
	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
		puts("this is not a DesignWare USB3 DRD Core\n");
		return -1;
	}

	dwc3_core_soft_reset(dwc3_reg);

	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);

	reg = readl(&dwc3_reg->g_ctl);
	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		debug("No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * where the device can fail to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter a Connect/Disconnect loop
	 */
	if ((revision & DWC3_REVISION_MASK) < 0x190a)
		reg |= DWC3_GCTL_U2RSTECN;

	writel(reg, &dwc3_reg->g_ctl);

	return 0;
}

void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
{
	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
			GFLADJ_30MHZ(val));
}

#if CONFIG_IS_ENABLED(DM_USB)
static int xhci_dwc3_probe(struct udevice *dev)
{
	struct xhci_hcor *hcor;
	struct xhci_hccr *hccr;
	struct dwc3 *dwc3_reg;
	enum usb_dr_mode dr_mode;
	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
	const char *phy;
	u32 reg;
	int ret;

	hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

	ret = dwc3_setup_phy(dev, &plat->phys);
	if (ret && (ret != -ENOTSUPP))
		return ret;

	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);

	dwc3_core_init(dwc3_reg);

	/* Set dwc3 usb2 phy config */
	reg = readl(&dwc3_reg->g_usb2phycfg[0]);

	phy = dev_read_string(dev, "phy_type");
	if (phy && strcmp(phy, "utmi_wide") == 0) {
		reg |= DWC3_GUSB2PHYCFG_PHYIF;
		reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
		reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	}

	if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;

	if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

	writel(reg, &dwc3_reg->g_usb2phycfg[0]);

	dr_mode = usb_get_dr_mode(dev->node);
	if (dr_mode == USB_DR_MODE_UNKNOWN)
		/* by default set dual role mode to HOST */
		dr_mode = USB_DR_MODE_HOST;

	dwc3_set_mode(dwc3_reg, dr_mode);

	return xhci_register(dev, hccr, hcor);
}

static int xhci_dwc3_remove(struct udevice *dev)
{
	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);

	dwc3_shutdown_phy(dev, &plat->phys);

	return xhci_deregister(dev);
}

static const struct udevice_id xhci_dwc3_ids[] = {
	{ .compatible = "snps,dwc3" },
	{ }
};

U_BOOT_DRIVER(xhci_dwc3) = {
	.name = "xhci-dwc3",
	.id = UCLASS_USB,
	.of_match = xhci_dwc3_ids,
	.probe = xhci_dwc3_probe,
	.remove = xhci_dwc3_remove,
	.ops = &xhci_usb_ops,
	.priv_auto	= sizeof(struct xhci_ctrl),
	.platdata_auto	= sizeof(struct xhci_dwc3_platdata),
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dc9cdf85 RM	2	/*
	3	* Copyright 2015 Freescale Semiconductor, Inc.
	4	*
	5	* DWC3 controller driver
	6	*
	7	* Author: Ramneek Mehresh<[email protected]>
dc9cdf85 RM	8	*/
	9
	10	#include <common.h>
b7c1c7d2	11	#include <dm.h>
f56db163	12	#include <generic-phy.h>
f7ae49fc	13	#include <log.h>
b7c1c7d2	14	#include <usb.h>
d648a50c	15	#include <dwc3-uboot.h>
c05ed00a	16	#include <linux/delay.h>
b7c1c7d2	17
1708a123	18	#include <usb/xhci.h>
dc9cdf85 RM	19	#include <asm/io.h>
dc9cdf85 RM	20	#include <linux/usb/dwc3.h>
576e3cc7	21	#include <linux/usb/otg.h>
dc9cdf85	22
f56db163	23	struct xhci_dwc3_platdata {
58221d7e	24	struct phy_bulk phys;
f56db163 PC	25	};
f56db163 PC	26
dc9cdf85 RM	27	void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
	28	{
	29	clrsetbits_le32(&dwc3_reg->g_ctl,
	30	DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
	31	DWC3_GCTL_PRTCAPDIR(mode));
	32	}
	33
121a4d13	34	static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
dc9cdf85 RM	35	{
	36	/* Assert USB3 PHY reset */
	37	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
	38
	39	/* Assert USB2 PHY reset */
	40	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
	41
	42	mdelay(100);
	43
	44	/* Clear USB3 PHY reset */
	45	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
	46
	47	/* Clear USB2 PHY reset */
	48	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
	49	}
	50
	51	void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
	52	{
	53	/* Before Resetting PHY, put Core in Reset */
	54	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
	55
	56	/* reset USB3 phy - if required */
	57	dwc3_phy_reset(dwc3_reg);
	58
5955bb93 RB	59	mdelay(100);
5955bb93 RB	60
dc9cdf85 RM	61	/* After PHYs are stable we can take Core out of reset state */
	62	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
	63	}
	64
	65	int dwc3_core_init(struct dwc3 *dwc3_reg)
	66	{
	67	u32 reg;
	68	u32 revision;
	69	unsigned int dwc3_hwparams1;
	70
	71	revision = readl(&dwc3_reg->g_snpsid);
	72	/* This should read as U3 followed by revision number */
	73	if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
	74	puts("this is not a DesignWare USB3 DRD Core\n");
	75	return -1;
	76	}
	77
	78	dwc3_core_soft_reset(dwc3_reg);
	79
	80	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
	81
	82	reg = readl(&dwc3_reg->g_ctl);
	83	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	84	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	85	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
	86	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	87	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	88	break;
	89	default:
	90	debug("No power optimization available\n");
	91	}
	92
	93	/*
	94	* WORKAROUND: DWC3 revisions <1.90a have a bug
	95	* where the device can fail to connect at SuperSpeed
	96	* and falls back to high-speed mode which causes
	97	* the device to enter a Connect/Disconnect loop
	98	*/
	99	if ((revision & DWC3_REVISION_MASK) < 0x190a)
	100	reg \|= DWC3_GCTL_U2RSTECN;
	101
	102	writel(reg, &dwc3_reg->g_ctl);
	103
	104	return 0;
	105	}
667f4dd9 NB	106
	107	void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
	108	{
	109	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL \|
	110	GFLADJ_30MHZ(val));
	111	}
b7c1c7d2	112
fd09c205	113	#if CONFIG_IS_ENABLED(DM_USB)
3fc2635d V	114	static int xhci_dwc3_probe(struct udevice *dev)
3fc2635d V	115	{
3fc2635d V	116	struct xhci_hcor *hcor;
	117	struct xhci_hccr *hccr;
	118	struct dwc3 *dwc3_reg;
	119	enum usb_dr_mode dr_mode;
d648a50c	120	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
062790f4 MK	121	const char *phy;
062790f4 MK	122	u32 reg;
3fc2635d V	123	int ret;
3fc2635d V	124
72a53ac5	125	hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
3fc2635d V	126	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
	127	HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
	128
58221d7e	129	ret = dwc3_setup_phy(dev, &plat->phys);
d648a50c	130	if (ret && (ret != -ENOTSUPP))
3fc2635d	131	return ret;
2fd4242c	132
b7c1c7d2 PC	133	dwc3_reg = (struct dwc3 )((char )(hccr) + DWC3_REG_OFFSET);
	134
	135	dwc3_core_init(dwc3_reg);
	136
062790f4 MK	137	/* Set dwc3 usb2 phy config */
	138	reg = readl(&dwc3_reg->g_usb2phycfg[0]);
	139
	140	phy = dev_read_string(dev, "phy_type");
	141	if (phy && strcmp(phy, "utmi_wide") == 0) {
	142	reg \|= DWC3_GUSB2PHYCFG_PHYIF;
	143	reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
	144	reg \|= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
	145	}
	146
	147	if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
	148	reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
	149
	150	if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
	151	reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
	152
b35b8076 NA	153	if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
	154	reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
	155
062790f4 MK	156	writel(reg, &dwc3_reg->g_usb2phycfg[0]);
062790f4 MK	157
ac28e59a	158	dr_mode = usb_get_dr_mode(dev->node);
576e3cc7 PC	159	if (dr_mode == USB_DR_MODE_UNKNOWN)
	160	/* by default set dual role mode to HOST */
	161	dr_mode = USB_DR_MODE_HOST;
	162
	163	dwc3_set_mode(dwc3_reg, dr_mode);
	164
b7c1c7d2 PC	165	return xhci_register(dev, hccr, hcor);
	166	}
	167
	168	static int xhci_dwc3_remove(struct udevice *dev)
	169	{
d648a50c JJH	170	struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
d648a50c JJH	171
58221d7e	172	dwc3_shutdown_phy(dev, &plat->phys);
f56db163	173
b7c1c7d2 PC	174	return xhci_deregister(dev);
	175	}
	176
	177	static const struct udevice_id xhci_dwc3_ids[] = {
	178	{ .compatible = "snps,dwc3" },
	179	{ }
	180	};
	181
	182	U_BOOT_DRIVER(xhci_dwc3) = {
	183	.name = "xhci-dwc3",
	184	.id = UCLASS_USB,
	185	.of_match = xhci_dwc3_ids,
	186	.probe = xhci_dwc3_probe,
	187	.remove = xhci_dwc3_remove,
	188	.ops = &xhci_usb_ops,
41575d8e SG	189	.priv_auto = sizeof(struct xhci_ctrl),
41575d8e SG	190	.platdata_auto = sizeof(struct xhci_dwc3_platdata),
b7c1c7d2 PC	191	.flags = DM_FLAG_ALLOC_PRIV_DMA,
b7c1c7d2 PC	192	};
623b7aca	193	#endif