[J-u-boot.git] / drivers / misc / imx8 / scu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2018 NXP
 *
 * Peng Fan <[email protected]>
 */

#include <common.h>
#include <log.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
#include <asm/arch/sci/sci.h>
#include <linux/bitops.h>
#include <linux/iopoll.h>
#include <misc.h>

DECLARE_GLOBAL_DATA_PTR;

struct mu_type {
	u32 tr[4];
	u32 rr[4];
	u32 sr;
	u32 cr;
};

struct imx8_scu {
	struct mu_type *base;
};

#define MU_CR_GIE_MASK		0xF0000000u
#define MU_CR_RIE_MASK		0xF000000u
#define MU_CR_GIR_MASK		0xF0000u
#define MU_CR_TIE_MASK		0xF00000u
#define MU_CR_F_MASK		0x7u
#define MU_SR_TE0_MASK		BIT(23)
#define MU_SR_RF0_MASK		BIT(27)
#define MU_TR_COUNT		4
#define MU_RR_COUNT		4

static inline void mu_hal_init(struct mu_type *base)
{
	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
	clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
		     MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
}

static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
{
	u32 mask = MU_SR_TE0_MASK >> reg_index;
	u32 val;
	int ret;

	assert(reg_index < MU_TR_COUNT);

	/* Wait TX register to be empty. */
	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
	if (ret < 0) {
		printf("%s timeout\n", __func__);
		return -ETIMEDOUT;
	}

	writel(msg, &base->tr[reg_index]);

	return 0;
}

static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
{
	u32 mask = MU_SR_RF0_MASK >> reg_index;
	u32 val;
	int ret;

	assert(reg_index < MU_TR_COUNT);

	/* Wait RX register to be full. */
	ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
	if (ret < 0) {
		printf("%s timeout\n", __func__);
		return -ETIMEDOUT;
	}

	*msg = readl(&base->rr[reg_index]);

	return 0;
}

static int sc_ipc_read(struct mu_type *base, void *data)
{
	struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
	int ret;
	u8 count = 0;

	if (!msg)
		return -EINVAL;

	/* Read first word */
	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
	if (ret)
		return ret;
	count++;

	/* Check size */
	if (msg->size > SC_RPC_MAX_MSG) {
		*((u32 *)msg) = 0;
		return -EINVAL;
	}

	/* Read remaining words */
	while (count < msg->size) {
		ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
					&msg->DATA.u32[count - 1]);
		if (ret)
			return ret;
		count++;
	}

	return 0;
}

static int sc_ipc_write(struct mu_type *base, void *data)
{
	struct sc_rpc_msg_s *msg = (struct sc_rpc_msg_s *)data;
	int ret;
	u8 count = 0;

	if (!msg)
		return -EINVAL;

	/* Check size */
	if (msg->size > SC_RPC_MAX_MSG)
		return -EINVAL;

	/* Write first word */
	ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
	if (ret)
		return ret;
	count++;

	/* Write remaining words */
	while (count < msg->size) {
		ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
				     msg->DATA.u32[count - 1]);
		if (ret)
			return ret;
		count++;
	}

	return 0;
}

/*
 * Note the function prototype use msgid as the 2nd parameter, here
 * we take it as no_resp.
 */
static int imx8_scu_call(struct udevice *dev, int no_resp, void *tx_msg,
			 int tx_size, void *rx_msg, int rx_size)
{
	struct imx8_scu *plat = dev_get_platdata(dev);
	sc_err_t result;
	int ret;

	/* Expect tx_msg, rx_msg are the same value */
	if (rx_msg && tx_msg != rx_msg)
		printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);

	ret = sc_ipc_write(plat->base, tx_msg);
	if (ret)
		return ret;
	if (!no_resp) {
		ret = sc_ipc_read(plat->base, rx_msg);
		if (ret)
			return ret;
	}

	result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);

	return sc_err_to_linux(result);
}

static int imx8_scu_probe(struct udevice *dev)
{
	struct imx8_scu *plat = dev_get_platdata(dev);
	fdt_addr_t addr;

	debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

#ifdef CONFIG_SPL_BUILD
	plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
#else
	plat->base = (struct mu_type *)addr;
#endif

	/* U-Boot not enable interrupts, so need to enable RX interrupts */
	mu_hal_init(plat->base);

	gd->arch.scu_dev = dev;

	return 0;
}

static int imx8_scu_remove(struct udevice *dev)
{
	return 0;
}

static int imx8_scu_bind(struct udevice *dev)
{
	int ret;
	struct udevice *child;
	ofnode node;

	debug("%s(dev=%p)\n", __func__, dev);
	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
		ret = lists_bind_fdt(dev, node, &child, true);
		if (ret)
			return ret;
		debug("bind child dev %s\n", child->name);
	}

	return 0;
}

static struct misc_ops imx8_scu_ops = {
	.call = imx8_scu_call,
};

static const struct udevice_id imx8_scu_ids[] = {
	{ .compatible = "fsl,imx8qxp-mu" },
	{ .compatible = "fsl,imx8-mu" },
	{ }
};

U_BOOT_DRIVER(imx8_scu) = {
	.name		= "imx8_scu",
	.id		= UCLASS_MISC,
	.of_match	= imx8_scu_ids,
	.probe		= imx8_scu_probe,
	.bind		= imx8_scu_bind,
	.remove		= imx8_scu_remove,
	.ops		= &imx8_scu_ops,
	.platdata_auto	= sizeof(struct imx8_scu),
	.flags		= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
ef64e782 PF	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2018 NXP
	4	*
	5	* Peng Fan <[email protected]>
	6	*/
	7
	8	#include <common.h>
f7ae49fc	9	#include <log.h>
ef64e782 PF	10	#include <asm/io.h>
	11	#include <dm.h>
	12	#include <dm/lists.h>
	13	#include <dm/root.h>
	14	#include <dm/device-internal.h>
	15	#include <asm/arch/sci/sci.h>
cd93d625	16	#include <linux/bitops.h>
ef64e782 PF	17	#include <linux/iopoll.h>
	18	#include <misc.h>
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	struct mu_type {
	23	u32 tr[4];
	24	u32 rr[4];
	25	u32 sr;
	26	u32 cr;
	27	};
	28
	29	struct imx8_scu {
	30	struct mu_type *base;
ef64e782 PF	31	};
	32
	33	#define MU_CR_GIE_MASK 0xF0000000u
	34	#define MU_CR_RIE_MASK 0xF000000u
	35	#define MU_CR_GIR_MASK 0xF0000u
	36	#define MU_CR_TIE_MASK 0xF00000u
	37	#define MU_CR_F_MASK 0x7u
	38	#define MU_SR_TE0_MASK BIT(23)
	39	#define MU_SR_RF0_MASK BIT(27)
	40	#define MU_TR_COUNT 4
	41	#define MU_RR_COUNT 4
	42
	43	static inline void mu_hal_init(struct mu_type *base)
	44	{
	45	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
	46	clrbits_le32(&base->cr, MU_CR_GIE_MASK \| MU_CR_RIE_MASK \|
	47	MU_CR_TIE_MASK \| MU_CR_GIR_MASK \| MU_CR_F_MASK);
	48	}
	49
	50	static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
	51	{
	52	u32 mask = MU_SR_TE0_MASK >> reg_index;
	53	u32 val;
	54	int ret;
	55
	56	assert(reg_index < MU_TR_COUNT);
	57
	58	/* Wait TX register to be empty. */
	59	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
	60	if (ret < 0) {
	61	printf("%s timeout\n", __func__);
	62	return -ETIMEDOUT;
	63	}
	64
	65	writel(msg, &base->tr[reg_index]);
	66
	67	return 0;
	68	}
	69
	70	static int mu_hal_receivemsg(struct mu_type base, u32 reg_index, u32 msg)
	71	{
	72	u32 mask = MU_SR_RF0_MASK >> reg_index;
	73	u32 val;
	74	int ret;
	75
	76	assert(reg_index < MU_TR_COUNT);
	77
	78	/* Wait RX register to be full. */
77ed80c9	79	ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
ef64e782 PF	80	if (ret < 0) {
	81	printf("%s timeout\n", __func__);
	82	return -ETIMEDOUT;
	83	}
	84
	85	*msg = readl(&base->rr[reg_index]);
	86
	87	return 0;
	88	}
	89
	90	static int sc_ipc_read(struct mu_type base, void data)
	91	{
	92	struct sc_rpc_msg_s msg = (struct sc_rpc_msg_s )data;
	93	int ret;
	94	u8 count = 0;
	95
	96	if (!msg)
	97	return -EINVAL;
	98
	99	/* Read first word */
	100	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
	101	if (ret)
	102	return ret;
	103	count++;
	104
	105	/* Check size */
	106	if (msg->size > SC_RPC_MAX_MSG) {
	107	((u32 )msg) = 0;
	108	return -EINVAL;
	109	}
	110
	111	/* Read remaining words */
	112	while (count < msg->size) {
	113	ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
	114	&msg->DATA.u32[count - 1]);
	115	if (ret)
	116	return ret;
	117	count++;
	118	}
	119
	120	return 0;
	121	}
	122
	123	static int sc_ipc_write(struct mu_type base, void data)
	124	{
	125	struct sc_rpc_msg_s msg = (struct sc_rpc_msg_s )data;
	126	int ret;
	127	u8 count = 0;
	128
	129	if (!msg)
	130	return -EINVAL;
	131
	132	/* Check size */
	133	if (msg->size > SC_RPC_MAX_MSG)
	134	return -EINVAL;
	135
	136	/* Write first word */
	137	ret = mu_hal_sendmsg(base, 0, ((u32 )msg));
	138	if (ret)
	139	return ret;
	140	count++;
	141
	142	/* Write remaining words */
	143	while (count < msg->size) {
144	ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
145	msg->DATA.u32[count - 1]);
146	if (ret)
147	return ret;
148	count++;
149	}
150
151	return 0;
152	}
153
154	/*
155	* Note the function prototype use msgid as the 2nd parameter, here
156	* we take it as no_resp.
157	*/
158	static int imx8_scu_call(struct udevice dev, int no_resp, void tx_msg,
159	int tx_size, void *rx_msg, int rx_size)
160	{
026381fc	161	struct imx8_scu *plat = dev_get_platdata(dev);
ef64e782 PF	162	sc_err_t result;
	163	int ret;
	164
	165	/* Expect tx_msg, rx_msg are the same value */
	166	if (rx_msg && tx_msg != rx_msg)
	167	printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
	168
026381fc	169	ret = sc_ipc_write(plat->base, tx_msg);
ef64e782 PF	170	if (ret)
	171	return ret;
	172	if (!no_resp) {
026381fc	173	ret = sc_ipc_read(plat->base, rx_msg);
ef64e782 PF	174	if (ret)
	175	return ret;
	176	}
	177
	178	result = RPC_R8((struct sc_rpc_msg_s *)tx_msg);
	179
	180	return sc_err_to_linux(result);
	181	}
	182
	183	static int imx8_scu_probe(struct udevice *dev)
	184	{
026381fc	185	struct imx8_scu *plat = dev_get_platdata(dev);
ef64e782 PF	186	fdt_addr_t addr;
ef64e782 PF	187
026381fc	188	debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
ef64e782	189
2548493a	190	addr = dev_read_addr(dev);
ef64e782 PF	191	if (addr == FDT_ADDR_T_NONE)
	192	return -EINVAL;
	193
04b24965 PF	194	#ifdef CONFIG_SPL_BUILD
	195	plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
	196	#else
026381fc	197	plat->base = (struct mu_type *)addr;
04b24965	198	#endif
ef64e782 PF	199
ef64e782 PF	200	/* U-Boot not enable interrupts, so need to enable RX interrupts */
026381fc	201	mu_hal_init(plat->base);
ef64e782 PF	202
	203	gd->arch.scu_dev = dev;
	204
ef64e782 PF	205	return 0;
	206	}
	207
	208	static int imx8_scu_remove(struct udevice *dev)
	209	{
	210	return 0;
	211	}
	212
	213	static int imx8_scu_bind(struct udevice *dev)
	214	{
ef64e782 PF	215	int ret;
ef64e782 PF	216	struct udevice *child;
816d093c	217	ofnode node;
ef64e782 PF	218
ef64e782 PF	219	debug("%s(dev=%p)\n", __func__, dev);
816d093c PF	220	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
	221	ret = lists_bind_fdt(dev, node, &child, true);
	222	if (ret)
	223	return ret;
	224	debug("bind child dev %s\n", child->name);
	225	}
ef64e782 PF	226
	227	return 0;
	228	}
	229
	230	static struct misc_ops imx8_scu_ops = {
	231	.call = imx8_scu_call,
	232	};
	233
	234	static const struct udevice_id imx8_scu_ids[] = {
	235	{ .compatible = "fsl,imx8qxp-mu" },
	236	{ .compatible = "fsl,imx8-mu" },
	237	{ }
	238	};
	239
	240	U_BOOT_DRIVER(imx8_scu) = {
	241	.name = "imx8_scu",
	242	.id = UCLASS_MISC,
	243	.of_match = imx8_scu_ids,
	244	.probe = imx8_scu_probe,
	245	.bind = imx8_scu_bind,
	246	.remove = imx8_scu_remove,
	247	.ops = &imx8_scu_ops,
41575d8e	248	.platdata_auto = sizeof(struct imx8_scu),
ef64e782 PF	249	.flags = DM_FLAG_PRE_RELOC,
ef64e782 PF	250	};