[J-u-boot.git] / drivers / clk / owl / clk_owl.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Common clock driver for Actions Semi SoCs.
 *
 * Copyright (C) 2015 Actions Semi Co., Ltd.
 * Copyright (C) 2018 Manivannan Sadhasivam <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include "clk_owl.h"
#include <asm/io.h>
#if defined(CONFIG_MACH_S900)
#include <asm/arch-owl/regs_s900.h>
#include <dt-bindings/clock/actions,s900-cmu.h>
#elif defined(CONFIG_MACH_S700)
#include <asm/arch-owl/regs_s700.h>
#include <dt-bindings/clock/actions,s700-cmu.h>
#endif
#include <linux/bitops.h>
#include <linux/delay.h>

void owl_clk_init(struct owl_clk_priv *priv)
{
	u32 bus_clk = 0, core_pll, dev_pll;

#if defined(CONFIG_MACH_S900)
	/* Enable ASSIST_PLL */
	setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
	udelay(PLL_STABILITY_WAIT_US);
#endif

	/* Source HOSC to DEV_CLK */
	clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);

	/* Configure BUS_CLK */
	bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
			CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
			CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
	writel(bus_clk, priv->base + CMU_BUSCLK);

	udelay(PLL_STABILITY_WAIT_US);

	/* Configure CORE_PLL */
	core_pll = readl(priv->base + CMU_COREPLL);
	core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
	writel(core_pll, priv->base + CMU_COREPLL);

	udelay(PLL_STABILITY_WAIT_US);

	/* Configure DEV_PLL */
	dev_pll = readl(priv->base + CMU_DEVPLL);
	dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
	writel(dev_pll, priv->base + CMU_DEVPLL);

	udelay(PLL_STABILITY_WAIT_US);

	/* Source CORE_PLL for CORE_CLK */
	clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
			CMU_CORECLK_CPLL);

	/* Source DEV_PLL for DEV_CLK */
	setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);

	udelay(PLL_STABILITY_WAIT_US);
}

int owl_clk_enable(struct clk *clk)
{
	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
	enum owl_soc model = dev_get_driver_data(clk->dev);

	switch (clk->id) {
	case CLK_UART5:
		if (model != S900)
			return -EINVAL;
		/* Source HOSC for UART5 interface */
		clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
		/* Enable UART5 interface clock */
		setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
		break;
	case CLK_UART3:
		if (model != S700)
			return -EINVAL;
		/* Source HOSC for UART3 interface */
		clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
		/* Enable UART3 interface clock */
		setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
		break;
	case CLK_RMII_REF:
	case CLK_ETHERNET:
		setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
		setbits_le32(priv->base + CMU_ETHERNETPLL, 5);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

int owl_clk_disable(struct clk *clk)
{
	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
	enum owl_soc model = dev_get_driver_data(clk->dev);

	switch (clk->id) {
	case CLK_UART5:
		if (model != S900)
			return -EINVAL;
		/* Disable UART5 interface clock */
		clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
		break;
	case CLK_UART3:
		if (model != S700)
			return -EINVAL;
		/* Disable UART3 interface clock */
		clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
		break;
	case CLK_RMII_REF:
	case CLK_ETHERNET:
		clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int owl_clk_probe(struct udevice *dev)
{
	struct owl_clk_priv *priv = dev_get_priv(dev);

	priv->base = dev_read_addr(dev);
	if (priv->base == FDT_ADDR_T_NONE)
		return -EINVAL;

	/* setup necessary clocks */
	owl_clk_init(priv);

	return 0;
}

static const struct clk_ops owl_clk_ops = {
	.enable = owl_clk_enable,
	.disable = owl_clk_disable,
};

static const struct udevice_id owl_clk_ids[] = {
#if defined(CONFIG_MACH_S900)
	{ .compatible = "actions,s900-cmu", .data = S900 },
#elif defined(CONFIG_MACH_S700)
	{ .compatible = "actions,s700-cmu", .data = S700 },
#endif
	{ }
};

U_BOOT_DRIVER(clk_owl) = {
	.name		= "clk_owl",
	.id		= UCLASS_CLK,
	.of_match	= owl_clk_ids,
	.ops		= &owl_clk_ops,
	.priv_auto	= sizeof(struct owl_clk_priv),
	.probe		= owl_clk_probe,
};
Commit	Line	Data
ae485b54 MS	1	// SPDX-License-Identifier: GPL-2.0+
ae485b54 MS	2	/*
8b520ac1	3	* Common clock driver for Actions Semi SoCs.
ae485b54 MS	4	*
	5	* Copyright (C) 2015 Actions Semi Co., Ltd.
	6	* Copyright (C) 2018 Manivannan Sadhasivam <[email protected]>
	7	*/
	8
	9	#include <common.h>
	10	#include <dm.h>
8b520ac1	11	#include "clk_owl.h"
ae485b54	12	#include <asm/io.h>
8b520ac1 AST	13	#if defined(CONFIG_MACH_S900)
8b520ac1 AST	14	#include <asm/arch-owl/regs_s900.h>
4939beea	15	#include <dt-bindings/clock/actions,s900-cmu.h>
8b520ac1 AST	16	#elif defined(CONFIG_MACH_S700)
	17	#include <asm/arch-owl/regs_s700.h>
	18	#include <dt-bindings/clock/actions,s700-cmu.h>
	19	#endif
cd93d625	20	#include <linux/bitops.h>
c05ed00a	21	#include <linux/delay.h>
ae485b54 MS	22
	23	void owl_clk_init(struct owl_clk_priv *priv)
	24	{
	25	u32 bus_clk = 0, core_pll, dev_pll;
	26
8b520ac1	27	#if defined(CONFIG_MACH_S900)
ae485b54 MS	28	/* Enable ASSIST_PLL */
ae485b54 MS	29	setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
ae485b54	30	udelay(PLL_STABILITY_WAIT_US);
8b520ac1	31	#endif
ae485b54 MS	32
	33	/* Source HOSC to DEV_CLK */
	34	clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
	35
	36	/* Configure BUS_CLK */
	37	bus_clk \|= (CMU_PDBGDIV_DIV \| CMU_PERDIV_DIV \| CMU_NOCDIV_DIV \|
	38	CMU_DMMCLK_SRC \| CMU_APBCLK_DIV \| CMU_AHBCLK_DIV \|
	39	CMU_NOCCLK_SRC \| CMU_CORECLK_HOSC);
	40	writel(bus_clk, priv->base + CMU_BUSCLK);
	41
	42	udelay(PLL_STABILITY_WAIT_US);
	43
	44	/* Configure CORE_PLL */
	45	core_pll = readl(priv->base + CMU_COREPLL);
	46	core_pll \|= (CMU_COREPLL_EN \| CMU_COREPLL_HOSC_EN \| CMU_COREPLL_OUT);
	47	writel(core_pll, priv->base + CMU_COREPLL);
	48
	49	udelay(PLL_STABILITY_WAIT_US);
	50
	51	/* Configure DEV_PLL */
	52	dev_pll = readl(priv->base + CMU_DEVPLL);
	53	dev_pll \|= (CMU_DEVPLL_EN \| CMU_DEVPLL_OUT);
	54	writel(dev_pll, priv->base + CMU_DEVPLL);
	55
	56	udelay(PLL_STABILITY_WAIT_US);
	57
	58	/* Source CORE_PLL for CORE_CLK */
	59	clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
	60	CMU_CORECLK_CPLL);
	61
	62	/* Source DEV_PLL for DEV_CLK */
	63	setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
	64
	65	udelay(PLL_STABILITY_WAIT_US);
	66	}
	67
ae485b54 MS	68	int owl_clk_enable(struct clk *clk)
	69	{
	70	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
8b520ac1	71	enum owl_soc model = dev_get_driver_data(clk->dev);
ae485b54 MS	72
ae485b54 MS	73	switch (clk->id) {
4939beea	74	case CLK_UART5:
8b520ac1 AST	75	if (model != S900)
	76	return -EINVAL;
	77	/* Source HOSC for UART5 interface */
	78	clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
	79	/* Enable UART5 interface clock */
	80	setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
	81	break;
	82	case CLK_UART3:
	83	if (model != S700)
	84	return -EINVAL;
	85	/* Source HOSC for UART3 interface */
	86	clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
	87	/* Enable UART3 interface clock */
	88	setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
ae485b54	89	break;
3a217346 AST	90	case CLK_RMII_REF:
	91	case CLK_ETHERNET:
	92	setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
	93	setbits_le32(priv->base + CMU_ETHERNETPLL, 5);
	94	break;
ae485b54	95	default:
8b520ac1	96	return -EINVAL;
ae485b54 MS	97	}
	98
	99	return 0;
	100	}
	101
	102	int owl_clk_disable(struct clk *clk)
	103	{
	104	struct owl_clk_priv *priv = dev_get_priv(clk->dev);
8b520ac1	105	enum owl_soc model = dev_get_driver_data(clk->dev);
ae485b54 MS	106
ae485b54 MS	107	switch (clk->id) {
4939beea	108	case CLK_UART5:
8b520ac1 AST	109	if (model != S900)
	110	return -EINVAL;
	111	/* Disable UART5 interface clock */
	112	clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
	113	break;
	114	case CLK_UART3:
	115	if (model != S700)
	116	return -EINVAL;
	117	/* Disable UART3 interface clock */
	118	clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
ae485b54	119	break;
3a217346 AST	120	case CLK_RMII_REF:
	121	case CLK_ETHERNET:
	122	clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
	123	break;
ae485b54	124	default:
8b520ac1	125	return -EINVAL;
ae485b54 MS	126	}
	127
	128	return 0;
	129	}
	130
	131	static int owl_clk_probe(struct udevice *dev)
	132	{
	133	struct owl_clk_priv *priv = dev_get_priv(dev);
	134
	135	priv->base = dev_read_addr(dev);
	136	if (priv->base == FDT_ADDR_T_NONE)
	137	return -EINVAL;
	138
	139	/* setup necessary clocks */
	140	owl_clk_init(priv);
	141
	142	return 0;
	143	}
	144
8b520ac1	145	static const struct clk_ops owl_clk_ops = {
ae485b54 MS	146	.enable = owl_clk_enable,
	147	.disable = owl_clk_disable,
	148	};
	149
	150	static const struct udevice_id owl_clk_ids[] = {
8b520ac1 AST	151	#if defined(CONFIG_MACH_S900)
	152	{ .compatible = "actions,s900-cmu", .data = S900 },
	153	#elif defined(CONFIG_MACH_S700)
	154	{ .compatible = "actions,s700-cmu", .data = S700 },
	155	#endif
ae485b54 MS	156	{ }
	157	};
	158
	159	U_BOOT_DRIVER(clk_owl) = {
8b520ac1	160	.name = "clk_owl",
ae485b54 MS	161	.id = UCLASS_CLK,
	162	.of_match = owl_clk_ids,
	163	.ops = &owl_clk_ops,
41575d8e	164	.priv_auto = sizeof(struct owl_clk_priv),
ae485b54	165	.probe = owl_clk_probe,
ae485b54	166	};