[J-u-boot.git] / drivers / usb / host / ehci-mx5.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2009 Daniel Mack <[email protected]>
 * Copyright (C) 2010 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <log.h>
#include <usb.h>
#include <errno.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <usb/ehci-ci.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <dm.h>
#include <power/regulator.h>

#include "ehci.h"

#define MX5_USBOTHER_REGS_OFFSET 0x800


#define MXC_OTG_OFFSET			0
#define MXC_H1_OFFSET			0x200
#define MXC_H2_OFFSET			0x400
#define MXC_H3_OFFSET			0x600

#define MXC_USBCTRL_OFFSET		0
#define MXC_USB_PHY_CTR_FUNC_OFFSET	0x8
#define MXC_USB_PHY_CTR_FUNC2_OFFSET	0xc
#define MXC_USB_CTRL_1_OFFSET		0x10
#define MXC_USBH2CTRL_OFFSET		0x14
#define MXC_USBH3CTRL_OFFSET		0x18

/* USB_CTRL */
/* OTG wakeup intr enable */
#define MXC_OTG_UCTRL_OWIE_BIT		(1 << 27)
/* OTG power mask */
#define MXC_OTG_UCTRL_OPM_BIT		(1 << 24)
/* OTG power pin polarity */
#define MXC_OTG_UCTRL_O_PWR_POL_BIT	(1 << 24)
/* Host1 ULPI interrupt enable */
#define MXC_H1_UCTRL_H1UIE_BIT		(1 << 12)
/* HOST1 wakeup intr enable */
#define MXC_H1_UCTRL_H1WIE_BIT		(1 << 11)
/* HOST1 power mask */
#define MXC_H1_UCTRL_H1PM_BIT		(1 << 8)
/* HOST1 power pin polarity */
#define MXC_H1_UCTRL_H1_PWR_POL_BIT	(1 << 8)

/* USB_PHY_CTRL_FUNC */
/* OTG Polarity of Overcurrent */
#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)
/* OTG Disable Overcurrent Event */
#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)
/* UH1 Polarity of Overcurrent */
#define MXC_H1_OC_POL_BIT		(1 << 6)
/* UH1 Disable Overcurrent Event */
#define MXC_H1_OC_DIS_BIT		(1 << 5)
/* OTG Power Pin Polarity */
#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)

/* USBH2CTRL */
#define MXC_H2_UCTRL_H2_OC_POL_BIT	(1 << 31)
#define MXC_H2_UCTRL_H2_OC_DIS_BIT	(1 << 30)
#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
#define MXC_H2_UCTRL_H2WIE_BIT		(1 << 7)
#define MXC_H2_UCTRL_H2PM_BIT		(1 << 4)
#define MXC_H2_UCTRL_H2_PWR_POL_BIT	(1 << 4)

/* USBH3CTRL */
#define MXC_H3_UCTRL_H3_OC_POL_BIT	(1 << 31)
#define MXC_H3_UCTRL_H3_OC_DIS_BIT	(1 << 30)
#define MXC_H3_UCTRL_H3UIE_BIT		(1 << 8)
#define MXC_H3_UCTRL_H3WIE_BIT		(1 << 7)
#define MXC_H3_UCTRL_H3_PWR_POL_BIT	(1 << 4)

/* USB_CTRL_1 */
#define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

int mxc_set_usbcontrol(int port, unsigned int flags)
{
	unsigned int v;
	void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
	void __iomem *usbother_base;
	int ret = 0;

	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	switch (port) {
	case 0:	/* OTG port */
		if (flags & MXC_EHCI_INTERNAL_PHY) {
			v = __raw_readl(usbother_base +
					MXC_USB_PHY_CTR_FUNC_OFFSET);
			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
			else
				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				/* OC/USBPWR is used */
				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
			else
				/* OC/USBPWR is not used */
				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
#ifdef CONFIG_MX51
			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
			else
				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
#endif
			__raw_writel(v, usbother_base +
					MXC_USB_PHY_CTR_FUNC_OFFSET);

			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
#ifdef CONFIG_MX51
			if (flags & MXC_EHCI_POWER_PINS_ENABLED)
				v &= ~MXC_OTG_UCTRL_OPM_BIT;
			else
				v |= MXC_OTG_UCTRL_OPM_BIT;
#endif
#ifdef CONFIG_MX53
			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
				v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
			else
				v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
#endif
			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
		}
		break;
	case 1:	/* Host 1 ULPI */
#ifdef CONFIG_MX51
		/* The clock for the USBH1 ULPI port will come externally
		   from the PHY. */
		v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
		__raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
				MXC_USB_CTRL_1_OFFSET);
#endif

		v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
#ifdef CONFIG_MX51
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
		else
			v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
#endif
#ifdef CONFIG_MX53
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
		else
			v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
#endif
		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H1_OC_POL_BIT;
		else
			v &= ~MXC_H1_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
		__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

		break;
	case 2: /* Host 2 ULPI */
		v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
#ifdef CONFIG_MX51
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
		else
			v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
#endif
#ifdef CONFIG_MX53
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
		else
			v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
		else
			v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
#endif
		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
		break;
#ifdef CONFIG_MX53
	case 3: /* Host 3 ULPI */
		v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
			v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
		else
			v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
		if (flags & MXC_EHCI_POWER_PINS_ENABLED)
			v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
		else
			v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
			v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
		else
			v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
		__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
		break;
#endif
	}

	return ret;
}

int __weak board_ehci_hcd_init(int port)
{
	return 0;
}

void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
{
}

__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
				   uint32_t *reg)
{
	mdelay(50);
}

#if !CONFIG_IS_ENABLED(DM_USB)
static const struct ehci_ops mx5_ehci_ops = {
	.powerup_fixup		= mx5_ehci_powerup_fixup,
};

int ehci_hcd_init(int index, enum usb_init_type init,
		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
	struct usb_ehci *ehci;

	/* The only user for this is efikamx-usb */
	ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
	set_usboh3_clk();
	enable_usboh3_clk(true);
	set_usb_phy_clk();
	enable_usb_phy1_clk(true);
	enable_usb_phy2_clk(true);
	mdelay(1);

	/* Do board specific initialization */
	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);

	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
		(0x200 * CONFIG_MXC_USB_PORT));
	*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
			HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	/* Do board specific post-initialization */
	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);

	return 0;
}

int ehci_hcd_stop(int index)
{
	return 0;
}
#else /* CONFIG_IS_ENABLED(DM_USB) */
struct ehci_mx5_priv_data {
	struct ehci_ctrl ctrl;
	struct usb_ehci *ehci;
	struct udevice *vbus_supply;
	enum usb_init_type init_type;
	int portnr;
};

static const struct ehci_ops mx5_ehci_ops = {
	.powerup_fixup		= mx5_ehci_powerup_fixup,
};

static int ehci_usb_of_to_plat(struct udevice *dev)
{
	struct usb_plat *plat = dev_get_plat(dev);
	const char *mode;

	mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
	if (mode) {
		if (strcmp(mode, "peripheral") == 0)
			plat->init_type = USB_INIT_DEVICE;
		else if (strcmp(mode, "host") == 0)
			plat->init_type = USB_INIT_HOST;
		else
			return -EINVAL;
	}

	return 0;
}

static int ehci_usb_probe(struct udevice *dev)
{
	struct usb_plat *plat = dev_get_plat(dev);
	struct usb_ehci *ehci = dev_read_addr_ptr(dev);
	struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
	enum usb_init_type type = plat->init_type;
	struct ehci_hccr *hccr;
	struct ehci_hcor *hcor;
	int ret;

	set_usboh3_clk();
	enable_usboh3_clk(true);
	set_usb_phy_clk();
	enable_usb_phy1_clk(true);
	enable_usb_phy2_clk(true);
	mdelay(1);

	priv->ehci = ehci;
	priv->portnr = dev_seq(dev);
	priv->init_type = type;

	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &priv->vbus_supply);
	if (ret)
		debug("%s: No vbus supply\n", dev->name);

	if (!ret && priv->vbus_supply) {
		ret = regulator_set_enable(priv->vbus_supply,
					   (type == USB_INIT_DEVICE) ?
					   false : true);
		if (ret) {
			puts("Error enabling VBUS supply\n");
			return ret;
		}
	}

	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	hcor = (struct ehci_hcor *)((uint32_t)hccr +
			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
	setbits_le32(&ehci->usbmode, CM_HOST);

	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	setbits_le32(&ehci->portsc, USB_EN);

	mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
	mdelay(10);

	return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
			     priv->init_type);
}

static const struct udevice_id mx5_usb_ids[] = {
	{ .compatible = "fsl,imx53-usb" },
	{ }
};

U_BOOT_DRIVER(usb_mx5) = {
	.name	= "ehci_mx5",
	.id	= UCLASS_USB,
	.of_match = mx5_usb_ids,
	.of_to_plat = ehci_usb_of_to_plat,
	.probe	= ehci_usb_probe,
	.remove = ehci_deregister,
	.ops	= &ehci_usb_ops,
	.plat_auto	= sizeof(struct usb_plat),
	.priv_auto	= sizeof(struct ehci_mx5_priv_data),
	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* !CONFIG_IS_ENABLED(DM_USB) */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1ca56202 WG	2	/*
	3	* Copyright (c) 2009 Daniel Mack <[email protected]>
	4	* Copyright (C) 2010 Freescale Semiconductor, Inc.
1ca56202 WG	5	*/
	6
	7	#include <common.h>
f7ae49fc	8	#include <log.h>
1ca56202 WG	9	#include <usb.h>
	10	#include <errno.h>
	11	#include <linux/compiler.h>
c05ed00a	12	#include <linux/delay.h>
e162c6b1	13	#include <usb/ehci-ci.h>
401d1c4f	14	#include <asm/global_data.h>
1ca56202 WG	15	#include <asm/io.h>
	16	#include <asm/arch/imx-regs.h>
	17	#include <asm/arch/clock.h>
22988766 LM	18	#include <dm.h>
22988766 LM	19	#include <power/regulator.h>
1ca56202 WG	20
1ca56202 WG	21	#include "ehci.h"
1ca56202 WG	22
	23	#define MX5_USBOTHER_REGS_OFFSET 0x800
	24
	25
bdc52020 BT	26	#define MXC_OTG_OFFSET 0
	27	#define MXC_H1_OFFSET 0x200
	28	#define MXC_H2_OFFSET 0x400
2cfe0b8f	29	#define MXC_H3_OFFSET 0x600
1ca56202 WG	30
	31	#define MXC_USBCTRL_OFFSET 0
	32	#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
	33	#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
	34	#define MXC_USB_CTRL_1_OFFSET 0x10
	35	#define MXC_USBH2CTRL_OFFSET 0x14
2cfe0b8f	36	#define MXC_USBH3CTRL_OFFSET 0x18
1ca56202 WG	37
1ca56202 WG	38	/* USB_CTRL */
bdc52020 BT	39	/* OTG wakeup intr enable */
	40	#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
	41	/* OTG power mask */
	42	#define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
31ac2d0c BT	43	/* OTG power pin polarity */
31ac2d0c BT	44	#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
bdc52020 BT	45	/* Host1 ULPI interrupt enable */
	46	#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
	47	/* HOST1 wakeup intr enable */
	48	#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
	49	/* HOST1 power mask */
	50	#define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
31ac2d0c BT	51	/* HOST1 power pin polarity */
31ac2d0c BT	52	#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
1ca56202 WG	53
1ca56202 WG	54	/* USB_PHY_CTRL_FUNC */
31ac2d0c BT	55	/* OTG Polarity of Overcurrent */
31ac2d0c BT	56	#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
bdc52020 BT	57	/* OTG Disable Overcurrent Event */
bdc52020 BT	58	#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
31ac2d0c BT	59	/* UH1 Polarity of Overcurrent */
31ac2d0c BT	60	#define MXC_H1_OC_POL_BIT (1 << 6)
bdc52020 BT	61	/* UH1 Disable Overcurrent Event */
bdc52020 BT	62	#define MXC_H1_OC_DIS_BIT (1 << 5)
31ac2d0c BT	63	/* OTG Power Pin Polarity */
31ac2d0c BT	64	#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
1ca56202 WG	65
1ca56202 WG	66	/* USBH2CTRL */
31ac2d0c	67	#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
2cfe0b8f	68	#define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
bdc52020 BT	69	#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
	70	#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
	71	#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
31ac2d0c	72	#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
1ca56202	73
2cfe0b8f	74	/* USBH3CTRL */
31ac2d0c	75	#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
2cfe0b8f BT	76	#define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
	77	#define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
	78	#define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
31ac2d0c	79	#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
2cfe0b8f	80
1ca56202	81	/* USB_CTRL_1 */
bdc52020	82	#define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
1ca56202 WG	83
	84	int mxc_set_usbcontrol(int port, unsigned int flags)
	85	{
	86	unsigned int v;
	87	void __iomem usb_base = (void __iomem )OTG_BASE_ADDR;
	88	void __iomem *usbother_base;
	89	int ret = 0;
	90
	91	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	92
	93	switch (port) {
	94	case 0: /* OTG port */
	95	if (flags & MXC_EHCI_INTERNAL_PHY) {
	96	v = __raw_readl(usbother_base +
	97	MXC_USB_PHY_CTR_FUNC_OFFSET);
31ac2d0c BT	98	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	99	v \|= MXC_OTG_PHYCTRL_OC_POL_BIT;
	100	else
	101	v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
1ca56202	102	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
1ca56202 WG	103	/* OC/USBPWR is used */
1ca56202 WG	104	v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
7d42432d BT	105	else
	106	/* OC/USBPWR is not used */
	107	v \|= MXC_OTG_PHYCTRL_OC_DIS_BIT;
31ac2d0c BT	108	#ifdef CONFIG_MX51
	109	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	110	v \|= MXC_OTG_PHYCTRL_PWR_POL_BIT;
	111	else
	112	v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
	113	#endif
1ca56202 WG	114	__raw_writel(v, usbother_base +
	115	MXC_USB_PHY_CTR_FUNC_OFFSET);
	116
	117	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
661052f4	118	#ifdef CONFIG_MX51
1ca56202	119	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
1ca56202	120	v &= ~MXC_OTG_UCTRL_OPM_BIT;
394c00dc BT	121	else
394c00dc BT	122	v \|= MXC_OTG_UCTRL_OPM_BIT;
31ac2d0c BT	123	#endif
	124	#ifdef CONFIG_MX53
	125	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	126	v \|= MXC_OTG_UCTRL_O_PWR_POL_BIT;
	127	else
	128	v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
661052f4	129	#endif
1ca56202 WG	130	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	131	}
	132	break;
bdc52020	133	case 1: /* Host 1 ULPI */
1ca56202 WG	134	#ifdef CONFIG_MX51
	135	/* The clock for the USBH1 ULPI port will come externally
	136	from the PHY. */
	137	v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
	138	__raw_writel(v \| MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
	139	MXC_USB_CTRL_1_OFFSET);
	140	#endif
	141
	142	v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
661052f4	143	#ifdef CONFIG_MX51
1ca56202	144	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
bdc52020	145	v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
1ca56202	146	else
bdc52020	147	v \|= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
31ac2d0c BT	148	#endif
	149	#ifdef CONFIG_MX53
	150	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	151	v \|= MXC_H1_UCTRL_H1_PWR_POL_BIT;
	152	else
	153	v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
661052f4	154	#endif
1ca56202 WG	155	__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
	156
	157	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
31ac2d0c BT	158	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	159	v \|= MXC_H1_OC_POL_BIT;
	160	else
	161	v &= ~MXC_H1_OC_POL_BIT;
1ca56202 WG	162	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	163	v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
	164	else
	165	v \|= MXC_H1_OC_DIS_BIT; /* OC is not used */
	166	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
	167
	168	break;
	169	case 2: /* Host 2 ULPI */
	170	v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
661052f4	171	#ifdef CONFIG_MX51
1ca56202	172	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
bdc52020	173	v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
1ca56202	174	else
bdc52020	175	v \|= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
2cfe0b8f BT	176	#endif
2cfe0b8f BT	177	#ifdef CONFIG_MX53
31ac2d0c BT	178	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	179	v \|= MXC_H2_UCTRL_H2_OC_POL_BIT;
	180	else
	181	v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
2cfe0b8f BT	182	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	183	v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
	184	else
	185	v \|= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
31ac2d0c BT	186	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	187	v \|= MXC_H2_UCTRL_H2_PWR_POL_BIT;
	188	else
	189	v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
661052f4	190	#endif
1ca56202 WG	191	__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
1ca56202 WG	192	break;
2cfe0b8f BT	193	#ifdef CONFIG_MX53
	194	case 3: /* Host 3 ULPI */
	195	v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
31ac2d0c BT	196	if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
	197	v \|= MXC_H3_UCTRL_H3_OC_POL_BIT;
	198	else
	199	v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
2cfe0b8f BT	200	if (flags & MXC_EHCI_POWER_PINS_ENABLED)
	201	v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
	202	else
	203	v \|= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
31ac2d0c BT	204	if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
	205	v \|= MXC_H3_UCTRL_H3_PWR_POL_BIT;
	206	else
	207	v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
2cfe0b8f BT	208	__raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
	209	break;
	210	#endif
1ca56202 WG	211	}
	212
	213	return ret;
	214	}
	215
f22e4fae	216	int __weak board_ehci_hcd_init(int port)
1b80f270	217	{
f22e4fae	218	return 0;
1b80f270 MV	219	}
1b80f270 MV	220
f22e4fae BT	221	void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
	222	{
	223	}
1b80f270	224
deb8508c SG	225	__weak void mx5_ehci_powerup_fixup(struct ehci_ctrl ctrl, uint32_t status_reg,
	226	uint32_t *reg)
	227	{
	228	mdelay(50);
	229	}
	230
22988766	231	#if !CONFIG_IS_ENABLED(DM_USB)
deb8508c SG	232	static const struct ehci_ops mx5_ehci_ops = {
	233	.powerup_fixup = mx5_ehci_powerup_fixup,
	234	};
	235
127efc4f TK	236	int ehci_hcd_init(int index, enum usb_init_type init,
127efc4f TK	237	struct ehci_hccr hccr, struct ehci_hcor hcor)
1ca56202 WG	238	{
1ca56202 WG	239	struct usb_ehci *ehci;
1ca56202	240
deb8508c SG	241	/* The only user for this is efikamx-usb */
deb8508c SG	242	ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
1ca56202	243	set_usboh3_clk();
76b6b196	244	enable_usboh3_clk(true);
414e1660	245	set_usb_phy_clk();
76b6b196 FE	246	enable_usb_phy1_clk(true);
76b6b196 FE	247	enable_usb_phy2_clk(true);
1ca56202 WG	248	mdelay(1);
1ca56202 WG	249
1b80f270	250	/* Do board specific initialization */
1ca56202 WG	251	board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
	252
	253	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
	254	(0x200 * CONFIG_MXC_USB_PORT));
676ae068 LS	255	hccr = (struct ehci_hccr )((uint32_t)&ehci->caplength);
	256	hcor = (struct ehci_hcor )((uint32_t)*hccr +
	257	HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
1ca56202 WG	258	setbits_le32(&ehci->usbmode, CM_HOST);
	259
	260	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	261	setbits_le32(&ehci->portsc, USB_EN);
	262
	263	mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
1ca56202 WG	264	mdelay(10);
1ca56202 WG	265
1b80f270 MV	266	/* Do board specific post-initialization */
	267	board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
	268
1ca56202 WG	269	return 0;
	270	}
	271
676ae068	272	int ehci_hcd_stop(int index)
1ca56202 WG	273	{
	274	return 0;
	275	}
22988766 LM	276	#else /* CONFIG_IS_ENABLED(DM_USB) */
	277	struct ehci_mx5_priv_data {
	278	struct ehci_ctrl ctrl;
	279	struct usb_ehci *ehci;
	280	struct udevice *vbus_supply;
	281	enum usb_init_type init_type;
	282	int portnr;
	283	};
	284
	285	static const struct ehci_ops mx5_ehci_ops = {
	286	.powerup_fixup = mx5_ehci_powerup_fixup,
	287	};
	288
d1998a9f	289	static int ehci_usb_of_to_plat(struct udevice *dev)
22988766	290	{
8a8d24bd	291	struct usb_plat *plat = dev_get_plat(dev);
22988766 LM	292	const char *mode;
	293
	294	mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
	295	if (mode) {
	296	if (strcmp(mode, "peripheral") == 0)
	297	plat->init_type = USB_INIT_DEVICE;
	298	else if (strcmp(mode, "host") == 0)
	299	plat->init_type = USB_INIT_HOST;
	300	else
	301	return -EINVAL;
	302	}
	303
	304	return 0;
	305	}
	306
	307	static int ehci_usb_probe(struct udevice *dev)
	308	{
8a8d24bd	309	struct usb_plat *plat = dev_get_plat(dev);
8613c8d8	310	struct usb_ehci *ehci = dev_read_addr_ptr(dev);
22988766 LM	311	struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
	312	enum usb_init_type type = plat->init_type;
	313	struct ehci_hccr *hccr;
	314	struct ehci_hcor *hcor;
	315	int ret;
	316
	317	set_usboh3_clk();
	318	enable_usboh3_clk(true);
	319	set_usb_phy_clk();
	320	enable_usb_phy1_clk(true);
	321	enable_usb_phy2_clk(true);
	322	mdelay(1);
	323
	324	priv->ehci = ehci;
8b85dfc6	325	priv->portnr = dev_seq(dev);
22988766 LM	326	priv->init_type = type;
	327
	328	ret = device_get_supply_regulator(dev, "vbus-supply",
	329	&priv->vbus_supply);
	330	if (ret)
	331	debug("%s: No vbus supply\n", dev->name);
	332
	333	if (!ret && priv->vbus_supply) {
	334	ret = regulator_set_enable(priv->vbus_supply,
	335	(type == USB_INIT_DEVICE) ?
	336	false : true);
	337	if (ret) {
	338	puts("Error enabling VBUS supply\n");
	339	return ret;
	340	}
	341	}
	342
	343	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
	344	hcor = (struct ehci_hcor *)((uint32_t)hccr +
	345	HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
	346	setbits_le32(&ehci->usbmode, CM_HOST);
	347
	348	__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
	349	setbits_le32(&ehci->portsc, USB_EN);
	350
	351	mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
	352	mdelay(10);
	353
	354	return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
	355	priv->init_type);
	356	}
	357
	358	static const struct udevice_id mx5_usb_ids[] = {
	359	{ .compatible = "fsl,imx53-usb" },
	360	{ }
	361	};
	362
	363	U_BOOT_DRIVER(usb_mx5) = {
	364	.name = "ehci_mx5",
	365	.id = UCLASS_USB,
	366	.of_match = mx5_usb_ids,
d1998a9f	367	.of_to_plat = ehci_usb_of_to_plat,
22988766 LM	368	.probe = ehci_usb_probe,
	369	.remove = ehci_deregister,
	370	.ops = &ehci_usb_ops,
8a8d24bd	371	.plat_auto = sizeof(struct usb_plat),
41575d8e	372	.priv_auto = sizeof(struct ehci_mx5_priv_data),
22988766 LM	373	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	374	};
	375	#endif /* !CONFIG_IS_ENABLED(DM_USB) */