[J-u-boot.git] / drivers / serial / serial_mxc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (c) 2007 Sascha Hauer <[email protected]>
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_mxc.h>
#include <serial.h>
#include <linux/compiler.h>

/* UART Control Register Bit Fields.*/
#define URXD_CHARRDY	(1<<15)
#define URXD_ERR	(1<<14)
#define URXD_OVRRUN	(1<<13)
#define URXD_FRMERR	(1<<12)
#define URXD_BRK	(1<<11)
#define URXD_PRERR	(1<<10)
#define URXD_RX_DATA	(0xFF)
#define UCR1_ADEN	(1<<15) /* Auto dectect interrupt */
#define UCR1_ADBR	(1<<14) /* Auto detect baud rate */
#define UCR1_TRDYEN	(1<<13) /* Transmitter ready interrupt enable */
#define UCR1_IDEN	(1<<12) /* Idle condition interrupt */
#define UCR1_RRDYEN	(1<<9)	/* Recv ready interrupt enable */
#define UCR1_RDMAEN	(1<<8)	/* Recv ready DMA enable */
#define UCR1_IREN	(1<<7)	/* Infrared interface enable */
#define UCR1_TXMPTYEN	(1<<6)	/* Transimitter empty interrupt enable */
#define UCR1_RTSDEN	(1<<5)	/* RTS delta interrupt enable */
#define UCR1_SNDBRK	(1<<4)	/* Send break */
#define UCR1_TDMAEN	(1<<3)	/* Transmitter ready DMA enable */
#define UCR1_UARTCLKEN	(1<<2)	/* UART clock enabled */
#define UCR1_DOZE	(1<<1)	/* Doze */
#define UCR1_UARTEN	(1<<0)	/* UART enabled */
#define UCR2_ESCI	(1<<15) /* Escape seq interrupt enable */
#define UCR2_IRTS	(1<<14) /* Ignore RTS pin */
#define UCR2_CTSC	(1<<13) /* CTS pin control */
#define UCR2_CTS	(1<<12) /* Clear to send */
#define UCR2_ESCEN	(1<<11) /* Escape enable */
#define UCR2_PREN	(1<<8)  /* Parity enable */
#define UCR2_PROE	(1<<7)  /* Parity odd/even */
#define UCR2_STPB	(1<<6)	/* Stop */
#define UCR2_WS		(1<<5)	/* Word size */
#define UCR2_RTSEN	(1<<4)	/* Request to send interrupt enable */
#define UCR2_TXEN	(1<<2)	/* Transmitter enabled */
#define UCR2_RXEN	(1<<1)	/* Receiver enabled */
#define UCR2_SRST	(1<<0)	/* SW reset */
#define UCR3_DTREN	(1<<13) /* DTR interrupt enable */
#define UCR3_PARERREN	(1<<12) /* Parity enable */
#define UCR3_FRAERREN	(1<<11) /* Frame error interrupt enable */
#define UCR3_DSR	(1<<10) /* Data set ready */
#define UCR3_DCD	(1<<9)  /* Data carrier detect */
#define UCR3_RI		(1<<8)  /* Ring indicator */
#define UCR3_ADNIMP	(1<<7)  /* Autobaud Detection Not Improved */
#define UCR3_RXDSEN	(1<<6)  /* Receive status interrupt enable */
#define UCR3_AIRINTEN	(1<<5)  /* Async IR wake interrupt enable */
#define UCR3_AWAKEN	(1<<4)  /* Async wake interrupt enable */
#define UCR3_REF25	(1<<3)  /* Ref freq 25 MHz */
#define UCR3_REF30	(1<<2)  /* Ref Freq 30 MHz */
#define UCR3_INVT	(1<<1)  /* Inverted Infrared transmission */
#define UCR3_BPEN	(1<<0)  /* Preset registers enable */
#define UCR4_CTSTL_32	(32<<10) /* CTS trigger level (32 chars) */
#define UCR4_INVR	(1<<9)  /* Inverted infrared reception */
#define UCR4_ENIRI	(1<<8)  /* Serial infrared interrupt enable */
#define UCR4_WKEN	(1<<7)  /* Wake interrupt enable */
#define UCR4_REF16	(1<<6)  /* Ref freq 16 MHz */
#define UCR4_IRSC	(1<<5)  /* IR special case */
#define UCR4_TCEN	(1<<3)  /* Transmit complete interrupt enable */
#define UCR4_BKEN	(1<<2)  /* Break condition interrupt enable */
#define UCR4_OREN	(1<<1)  /* Receiver overrun interrupt enable */
#define UCR4_DREN	(1<<0)  /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF	0       /* Receiver trigger level shift */
#define UFCR_RFDIV	(7<<7)  /* Reference freq divider mask */
#define UFCR_RFDIV_SHF	7	/* Reference freq divider shift */
#define RFDIV		4	/* divide input clock by 2 */
#define UFCR_DCEDTE	(1<<6)  /* DTE mode select */
#define UFCR_TXTL_SHF	10      /* Transmitter trigger level shift */
#define USR1_PARITYERR	(1<<15) /* Parity error interrupt flag */
#define USR1_RTSS	(1<<14) /* RTS pin status */
#define USR1_TRDY	(1<<13) /* Transmitter ready interrupt/dma flag */
#define USR1_RTSD	(1<<12) /* RTS delta */
#define USR1_ESCF	(1<<11) /* Escape seq interrupt flag */
#define USR1_FRAMERR	(1<<10) /* Frame error interrupt flag */
#define USR1_RRDY	(1<<9)	/* Receiver ready interrupt/dma flag */
#define USR1_TIMEOUT	(1<<7)	/* Receive timeout interrupt status */
#define USR1_RXDS	(1<<6)	/* Receiver idle interrupt flag */
#define USR1_AIRINT	(1<<5)	/* Async IR wake interrupt flag */
#define USR1_AWAKE	(1<<4)	/* Aysnc wake interrupt flag */
#define USR2_ADET	(1<<15) /* Auto baud rate detect complete */
#define USR2_TXFE	(1<<14) /* Transmit buffer FIFO empty */
#define USR2_DTRF	(1<<13) /* DTR edge interrupt flag */
#define USR2_IDLE	(1<<12) /* Idle condition */
#define USR2_IRINT	(1<<8)	/* Serial infrared interrupt flag */
#define USR2_WAKE	(1<<7)	/* Wake */
#define USR2_RTSF	(1<<4)	/* RTS edge interrupt flag */
#define USR2_TXDC	(1<<3)	/* Transmitter complete */
#define USR2_BRCD	(1<<2)	/* Break condition */
#define USR2_ORE	(1<<1)	/* Overrun error */
#define USR2_RDR	(1<<0)	/* Recv data ready */
#define UTS_FRCPERR	(1<<13) /* Force parity error */
#define UTS_LOOP	(1<<12) /* Loop tx and rx */
#define UTS_TXEMPTY	(1<<6)	/* TxFIFO empty */
#define UTS_RXEMPTY	(1<<5)	/* RxFIFO empty */
#define UTS_TXFULL	(1<<4)	/* TxFIFO full */
#define UTS_RXFULL	(1<<3)	/* RxFIFO full */
#define UTS_SOFTRS	(1<<0)	/* Software reset */
#define TXTL		2  /* reset default */
#define RXTL		1  /* reset default */

DECLARE_GLOBAL_DATA_PTR;

struct mxc_uart {
	u32 rxd;
	u32 spare0[15];

	u32 txd;
	u32 spare1[15];

	u32 cr1;
	u32 cr2;
	u32 cr3;
	u32 cr4;

	u32 fcr;
	u32 sr1;
	u32 sr2;
	u32 esc;

	u32 tim;
	u32 bir;
	u32 bmr;
	u32 brc;

	u32 onems;
	u32 ts;
};

static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
{
	writel(0, &base->cr1);
	writel(0, &base->cr2);

	while (!(readl(&base->cr2) & UCR2_SRST));

	if (use_dte)
		writel(0x404 | UCR3_ADNIMP, &base->cr3);
	else
		writel(0x704 | UCR3_ADNIMP, &base->cr3);

	writel(0x704 | UCR3_ADNIMP, &base->cr3);
	writel(0x8000, &base->cr4);
	writel(0x2b, &base->esc);
	writel(0, &base->tim);

	writel(0, &base->ts);
}

static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
			       unsigned long baudrate, bool use_dte)
{
	u32 tmp;

	tmp = RFDIV << UFCR_RFDIV_SHF;
	if (use_dte)
		tmp |= UFCR_DCEDTE;
	else
		tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
	writel(tmp, &base->fcr);

	writel(0xf, &base->bir);
	writel(clk / (2 * baudrate), &base->bmr);

	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
	       &base->cr2);
	writel(UCR1_UARTEN, &base->cr1);
}

#if !CONFIG_IS_ENABLED(DM_SERIAL)

#ifndef CONFIG_MXC_UART_BASE
#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
#endif

#define mxc_base	((struct mxc_uart *)CONFIG_MXC_UART_BASE)

static void mxc_serial_setbrg(void)
{
	u32 clk = imx_get_uartclk();

	if (!gd->baudrate)
		gd->baudrate = CONFIG_BAUDRATE;

	_mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
}

static int mxc_serial_getc(void)
{
	while (readl(&mxc_base->ts) & UTS_RXEMPTY)
		WATCHDOG_RESET();
	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
}

static void mxc_serial_putc(const char c)
{
	/* If \n, also do \r */
	if (c == '\n')
		serial_putc('\r');

	writel(c, &mxc_base->txd);

	/* wait for transmitter to be ready */
	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
		WATCHDOG_RESET();
}

/* Test whether a character is in the RX buffer */
static int mxc_serial_tstc(void)
{
	/* If receive fifo is empty, return false */
	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
		return 0;
	return 1;
}

/*
 * Initialise the serial port with the given baudrate. The settings
 * are always 8 data bits, no parity, 1 stop bit, no start bits.
 */
static int mxc_serial_init(void)
{
	_mxc_serial_init(mxc_base, false);

	serial_setbrg();

	return 0;
}

static struct serial_device mxc_serial_drv = {
	.name	= "mxc_serial",
	.start	= mxc_serial_init,
	.stop	= NULL,
	.setbrg	= mxc_serial_setbrg,
	.putc	= mxc_serial_putc,
	.puts	= default_serial_puts,
	.getc	= mxc_serial_getc,
	.tstc	= mxc_serial_tstc,
};

void mxc_serial_initialize(void)
{
	serial_register(&mxc_serial_drv);
}

__weak struct serial_device *default_serial_console(void)
{
	return &mxc_serial_drv;
}
#endif

#if CONFIG_IS_ENABLED(DM_SERIAL)

int mxc_serial_setbrg(struct udevice *dev, int baudrate)
{
	struct mxc_serial_plat *plat = dev_get_plat(dev);
	u32 clk = imx_get_uartclk();

	_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);

	return 0;
}

static int mxc_serial_probe(struct udevice *dev)
{
	struct mxc_serial_plat *plat = dev_get_plat(dev);

	_mxc_serial_init(plat->reg, plat->use_dte);

	return 0;
}

static int mxc_serial_getc(struct udevice *dev)
{
	struct mxc_serial_plat *plat = dev_get_plat(dev);
	struct mxc_uart *const uart = plat->reg;

	if (readl(&uart->ts) & UTS_RXEMPTY)
		return -EAGAIN;

	return readl(&uart->rxd) & URXD_RX_DATA;
}

static int mxc_serial_putc(struct udevice *dev, const char ch)
{
	struct mxc_serial_plat *plat = dev_get_plat(dev);
	struct mxc_uart *const uart = plat->reg;

	if (!(readl(&uart->ts) & UTS_TXEMPTY))
		return -EAGAIN;

	writel(ch, &uart->txd);

	return 0;
}

static int mxc_serial_pending(struct udevice *dev, bool input)
{
	struct mxc_serial_plat *plat = dev_get_plat(dev);
	struct mxc_uart *const uart = plat->reg;
	uint32_t sr2 = readl(&uart->sr2);

	if (input)
		return sr2 & USR2_RDR ? 1 : 0;
	else
		return sr2 & USR2_TXDC ? 0 : 1;
}

static const struct dm_serial_ops mxc_serial_ops = {
	.putc = mxc_serial_putc,
	.pending = mxc_serial_pending,
	.getc = mxc_serial_getc,
	.setbrg = mxc_serial_setbrg,
};

#if CONFIG_IS_ENABLED(OF_CONTROL)
static int mxc_serial_of_to_plat(struct udevice *dev)
{
	struct mxc_serial_plat *plat = dev_get_plat(dev);
	fdt_addr_t addr;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	plat->reg = (struct mxc_uart *)addr;

	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
					"fsl,dte-mode");
	return 0;
}

static const struct udevice_id mxc_serial_ids[] = {
	{ .compatible = "fsl,imx21-uart" },
	{ .compatible = "fsl,imx53-uart" },
	{ .compatible = "fsl,imx6sx-uart" },
	{ .compatible = "fsl,imx6ul-uart" },
	{ .compatible = "fsl,imx7d-uart" },
	{ .compatible = "fsl,imx6q-uart" },
	{ }
};
#endif

U_BOOT_DRIVER(serial_mxc) = {
	.name	= "serial_mxc",
	.id	= UCLASS_SERIAL,
#if CONFIG_IS_ENABLED(OF_CONTROL)
	.of_match = mxc_serial_ids,
	.of_to_plat = mxc_serial_of_to_plat,
	.plat_auto	= sizeof(struct mxc_serial_plat),
#endif
	.probe = mxc_serial_probe,
	.ops	= &mxc_serial_ops,
	.flags = DM_FLAG_PRE_RELOC,
};
#endif

#ifdef CONFIG_DEBUG_UART_MXC
#include <debug_uart.h>

static inline void _debug_uart_init(void)
{
	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;

	_mxc_serial_init(base, false);
	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
			   CONFIG_BAUDRATE, false);
}

static inline void _debug_uart_putc(int ch)
{
	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;

	while (!(readl(&base->ts) & UTS_TXEMPTY))
		WATCHDOG_RESET();

	writel(ch, &base->txd);
}

DEBUG_UART_FUNCS

#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
9b56f4f0 SH	2	/*
9b56f4f0 SH	3	* (c) 2007 Sascha Hauer <[email protected]>
9b56f4f0 SH	4	*/
	5
	6	#include <common.h>
a8ba569c SG	7	#include <dm.h>
a8ba569c SG	8	#include <errno.h>
4ec3d2a7	9	#include <watchdog.h>
47d19da4 IY	10	#include <asm/arch/imx-regs.h>
47d19da4 IY	11	#include <asm/arch/clock.h>
401d1c4f	12	#include <asm/global_data.h>
86256b79	13	#include <dm/platform_data/serial_mxc.h>
a943472c MV	14	#include <serial.h>
a943472c MV	15	#include <linux/compiler.h>
9b56f4f0	16
9b56f4f0	17	/* UART Control Register Bit Fields.*/
52c14cab JT	18	#define URXD_CHARRDY (1<<15)
	19	#define URXD_ERR (1<<14)
	20	#define URXD_OVRRUN (1<<13)
	21	#define URXD_FRMERR (1<<12)
	22	#define URXD_BRK (1<<11)
	23	#define URXD_PRERR (1<<10)
	24	#define URXD_RX_DATA (0xFF)
	25	#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
	26	#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
	27	#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
	28	#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
	29	#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
	30	#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
	31	#define UCR1_IREN (1<<7) /* Infrared interface enable */
	32	#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
	33	#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
	34	#define UCR1_SNDBRK (1<<4) /* Send break */
	35	#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
	36	#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
	37	#define UCR1_DOZE (1<<1) /* Doze */
	38	#define UCR1_UARTEN (1<<0) /* UART enabled */
	39	#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
	40	#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
	41	#define UCR2_CTSC (1<<13) /* CTS pin control */
	42	#define UCR2_CTS (1<<12) /* Clear to send */
	43	#define UCR2_ESCEN (1<<11) /* Escape enable */
	44	#define UCR2_PREN (1<<8) /* Parity enable */
	45	#define UCR2_PROE (1<<7) /* Parity odd/even */
	46	#define UCR2_STPB (1<<6) /* Stop */
	47	#define UCR2_WS (1<<5) /* Word size */
	48	#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
	49	#define UCR2_TXEN (1<<2) /* Transmitter enabled */
	50	#define UCR2_RXEN (1<<1) /* Receiver enabled */
	51	#define UCR2_SRST (1<<0) /* SW reset */
	52	#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
	53	#define UCR3_PARERREN (1<<12) /* Parity enable */
	54	#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
	55	#define UCR3_DSR (1<<10) /* Data set ready */
	56	#define UCR3_DCD (1<<9) /* Data carrier detect */
	57	#define UCR3_RI (1<<8) /* Ring indicator */
	58	#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
	59	#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
	60	#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
	61	#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
	62	#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
	63	#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
	64	#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
	65	#define UCR3_BPEN (1<<0) /* Preset registers enable */
	66	#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
	67	#define UCR4_INVR (1<<9) /* Inverted infrared reception */
	68	#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
	69	#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
	70	#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
	71	#define UCR4_IRSC (1<<5) /* IR special case */
	72	#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
	73	#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
	74	#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
	75	#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
	76	#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
	77	#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
	78	#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
	79	#define RFDIV 4 /* divide input clock by 2 */
	80	#define UFCR_DCEDTE (1<<6) /* DTE mode select */
	81	#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
82	#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
83	#define USR1_RTSS (1<<14) /* RTS pin status */
84	#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
85	#define USR1_RTSD (1<<12) /* RTS delta */
86	#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
87	#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
88	#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
89	#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
90	#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
91	#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
92	#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
93	#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
94	#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
95	#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
96	#define USR2_IDLE (1<<12) /* Idle condition */
97	#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
98	#define USR2_WAKE (1<<7) /* Wake */
99	#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
100	#define USR2_TXDC (1<<3) /* Transmitter complete */
101	#define USR2_BRCD (1<<2) /* Break condition */
102	#define USR2_ORE (1<<1) /* Overrun error */
103	#define USR2_RDR (1<<0) /* Recv data ready */
104	#define UTS_FRCPERR (1<<13) /* Force parity error */
105	#define UTS_LOOP (1<<12) /* Loop tx and rx */
106	#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
107	#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
108	#define UTS_TXFULL (1<<4) /* TxFIFO full */
109	#define UTS_RXFULL (1<<3) /* RxFIFO full */
110	#define UTS_SOFTRS (1<<0) /* Software reset */
45d97511 JT	111	#define TXTL 2 /* reset default */
45d97511 JT	112	#define RXTL 1 /* reset default */
9b56f4f0	113
a99546ab SA	114	DECLARE_GLOBAL_DATA_PTR;
a99546ab SA	115
ffa8bcd7 JT	116	struct mxc_uart {
	117	u32 rxd;
	118	u32 spare0[15];
	119
	120	u32 txd;
	121	u32 spare1[15];
	122
	123	u32 cr1;
	124	u32 cr2;
	125	u32 cr3;
	126	u32 cr4;
	127
	128	u32 fcr;
	129	u32 sr1;
	130	u32 sr2;
	131	u32 esc;
	132
	133	u32 tim;
	134	u32 bir;
	135	u32 bmr;
	136	u32 brc;
	137
	138	u32 onems;
	139	u32 ts;
	140	};
	141
a2453208	142	static void _mxc_serial_init(struct mxc_uart *base, int use_dte)
97548d59 JT	143	{
	144	writel(0, &base->cr1);
	145	writel(0, &base->cr2);
	146
	147	while (!(readl(&base->cr2) & UCR2_SRST));
	148
a2453208 MK	149	if (use_dte)
	150	writel(0x404 \| UCR3_ADNIMP, &base->cr3);
	151	else
	152	writel(0x704 \| UCR3_ADNIMP, &base->cr3);
	153
97548d59 JT	154	writel(0x704 \| UCR3_ADNIMP, &base->cr3);
	155	writel(0x8000, &base->cr4);
	156	writel(0x2b, &base->esc);
	157	writel(0, &base->tim);
	158
	159	writel(0, &base->ts);
	160	}
	161
45d97511 JT	162	static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
	163	unsigned long baudrate, bool use_dte)
	164	{
	165	u32 tmp;
	166
	167	tmp = RFDIV << UFCR_RFDIV_SHF;
	168	if (use_dte)
	169	tmp \|= UFCR_DCEDTE;
	170	else
	171	tmp \|= (TXTL << UFCR_TXTL_SHF) \| (RXTL << UFCR_RXTL_SHF);
	172	writel(tmp, &base->fcr);
	173
	174	writel(0xf, &base->bir);
	175	writel(clk / (2 * baudrate), &base->bmr);
	176
	177	writel(UCR2_WS \| UCR2_IRTS \| UCR2_RXEN \| UCR2_TXEN \| UCR2_SRST,
	178	&base->cr2);
	179	writel(UCR1_UARTEN, &base->cr1);
	180	}
	181
e434b414	182	#if !CONFIG_IS_ENABLED(DM_SERIAL)
a8ba569c SG	183
	184	#ifndef CONFIG_MXC_UART_BASE
	185	#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
	186	#endif
	187
ffa8bcd7	188	#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
a8ba569c	189
a943472c	190	static void mxc_serial_setbrg(void)
9b56f4f0	191	{
71d64c0e	192	u32 clk = imx_get_uartclk();
9b56f4f0 SH	193
	194	if (!gd->baudrate)
	195	gd->baudrate = CONFIG_BAUDRATE;
	196
45d97511	197	_mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
9b56f4f0 SH	198	}
9b56f4f0 SH	199
a943472c	200	static int mxc_serial_getc(void)
9b56f4f0	201	{
ffa8bcd7	202	while (readl(&mxc_base->ts) & UTS_RXEMPTY)
4ec3d2a7	203	WATCHDOG_RESET();
ffa8bcd7	204	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
9b56f4f0 SH	205	}
9b56f4f0 SH	206
a943472c	207	static void mxc_serial_putc(const char c)
9b56f4f0	208	{
055457ef AW	209	/* If \n, also do \r */
	210	if (c == '\n')
	211	serial_putc('\r');
	212
ffa8bcd7	213	writel(c, &mxc_base->txd);
9b56f4f0 SH	214
9b56f4f0 SH	215	/* wait for transmitter to be ready */
ffa8bcd7	216	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
4ec3d2a7	217	WATCHDOG_RESET();
9b56f4f0 SH	218	}
9b56f4f0 SH	219
52c14cab	220	/* Test whether a character is in the RX buffer */
a943472c	221	static int mxc_serial_tstc(void)
9b56f4f0 SH	222	{
9b56f4f0 SH	223	/* If receive fifo is empty, return false */
ffa8bcd7	224	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
9b56f4f0 SH	225	return 0;
	226	return 1;
	227	}
	228
9b56f4f0 SH	229	/*
	230	* Initialise the serial port with the given baudrate. The settings
	231	* are always 8 data bits, no parity, 1 stop bit, no start bits.
9b56f4f0	232	*/
a943472c	233	static int mxc_serial_init(void)
9b56f4f0	234	{
a2453208	235	_mxc_serial_init(mxc_base, false);
9b56f4f0 SH	236
	237	serial_setbrg();
	238
9b56f4f0 SH	239	return 0;
9b56f4f0 SH	240	}
a943472c	241
a943472c MV	242	static struct serial_device mxc_serial_drv = {
	243	.name = "mxc_serial",
	244	.start = mxc_serial_init,
	245	.stop = NULL,
	246	.setbrg = mxc_serial_setbrg,
	247	.putc = mxc_serial_putc,
ec3fd689	248	.puts = default_serial_puts,
a943472c MV	249	.getc = mxc_serial_getc,
	250	.tstc = mxc_serial_tstc,
	251	};
	252
	253	void mxc_serial_initialize(void)
	254	{
	255	serial_register(&mxc_serial_drv);
	256	}
	257
	258	__weak struct serial_device *default_serial_console(void)
	259	{
	260	return &mxc_serial_drv;
	261	}
a8ba569c SG	262	#endif
a8ba569c SG	263
e434b414	264	#if CONFIG_IS_ENABLED(DM_SERIAL)
a8ba569c	265
a8ba569c SG	266	int mxc_serial_setbrg(struct udevice *dev, int baudrate)
a8ba569c SG	267	{
0fd3d911	268	struct mxc_serial_plat *plat = dev_get_plat(dev);
a8ba569c	269	u32 clk = imx_get_uartclk();
83fd908f	270
45d97511	271	_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
a8ba569c SG	272
	273	return 0;
	274	}
	275
	276	static int mxc_serial_probe(struct udevice *dev)
	277	{
0fd3d911	278	struct mxc_serial_plat *plat = dev_get_plat(dev);
a8ba569c	279
a2453208	280	_mxc_serial_init(plat->reg, plat->use_dte);
a8ba569c SG	281
	282	return 0;
	283	}
	284
	285	static int mxc_serial_getc(struct udevice *dev)
	286	{
0fd3d911	287	struct mxc_serial_plat *plat = dev_get_plat(dev);
a8ba569c SG	288	struct mxc_uart *const uart = plat->reg;
	289
	290	if (readl(&uart->ts) & UTS_RXEMPTY)
	291	return -EAGAIN;
	292
	293	return readl(&uart->rxd) & URXD_RX_DATA;
	294	}
	295
	296	static int mxc_serial_putc(struct udevice *dev, const char ch)
	297	{
0fd3d911	298	struct mxc_serial_plat *plat = dev_get_plat(dev);
a8ba569c SG	299	struct mxc_uart *const uart = plat->reg;
	300
	301	if (!(readl(&uart->ts) & UTS_TXEMPTY))
	302	return -EAGAIN;
	303
	304	writel(ch, &uart->txd);
	305
	306	return 0;
	307	}
	308
	309	static int mxc_serial_pending(struct udevice *dev, bool input)
	310	{
0fd3d911	311	struct mxc_serial_plat *plat = dev_get_plat(dev);
a8ba569c SG	312	struct mxc_uart *const uart = plat->reg;
	313	uint32_t sr2 = readl(&uart->sr2);
	314
	315	if (input)
	316	return sr2 & USR2_RDR ? 1 : 0;
	317	else
	318	return sr2 & USR2_TXDC ? 0 : 1;
	319	}
	320
	321	static const struct dm_serial_ops mxc_serial_ops = {
	322	.putc = mxc_serial_putc,
	323	.pending = mxc_serial_pending,
	324	.getc = mxc_serial_getc,
	325	.setbrg = mxc_serial_setbrg,
	326	};
	327
a99546ab	328	#if CONFIG_IS_ENABLED(OF_CONTROL)
d1998a9f	329	static int mxc_serial_of_to_plat(struct udevice *dev)
a99546ab	330	{
0fd3d911	331	struct mxc_serial_plat *plat = dev_get_plat(dev);
a99546ab SA	332	fdt_addr_t addr;
a99546ab SA	333
2548493a	334	addr = dev_read_addr(dev);
a99546ab SA	335	if (addr == FDT_ADDR_T_NONE)
	336	return -EINVAL;
	337
	338	plat->reg = (struct mxc_uart *)addr;
	339
e160f7d4	340	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
a99546ab SA	341	"fsl,dte-mode");
	342	return 0;
	343	}
	344
	345	static const struct udevice_id mxc_serial_ids[] = {
2756fd16 LM	346	{ .compatible = "fsl,imx21-uart" },
2756fd16 LM	347	{ .compatible = "fsl,imx53-uart" },
6757fa57	348	{ .compatible = "fsl,imx6sx-uart" },
3a5d6363	349	{ .compatible = "fsl,imx6ul-uart" },
a99546ab	350	{ .compatible = "fsl,imx7d-uart" },
4684fa8b	351	{ .compatible = "fsl,imx6q-uart" },
a99546ab SA	352	{ }
	353	};
	354	#endif
	355
a8ba569c SG	356	U_BOOT_DRIVER(serial_mxc) = {
	357	.name = "serial_mxc",
	358	.id = UCLASS_SERIAL,
a99546ab SA	359	#if CONFIG_IS_ENABLED(OF_CONTROL)
a99546ab SA	360	.of_match = mxc_serial_ids,
d1998a9f	361	.of_to_plat = mxc_serial_of_to_plat,
8a8d24bd	362	.plat_auto = sizeof(struct mxc_serial_plat),
a99546ab	363	#endif
a8ba569c SG	364	.probe = mxc_serial_probe,
	365	.ops = &mxc_serial_ops,
	366	.flags = DM_FLAG_PRE_RELOC,
	367	};
	368	#endif
61366b71 JT	369
	370	#ifdef CONFIG_DEBUG_UART_MXC
	371	#include <debug_uart.h>
	372
	373	static inline void _debug_uart_init(void)
	374	{
	375	struct mxc_uart base = (struct mxc_uart )CONFIG_DEBUG_UART_BASE;
	376
a2453208	377	_mxc_serial_init(base, false);
61366b71 JT	378	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
	379	CONFIG_BAUDRATE, false);
	380	}
	381
	382	static inline void _debug_uart_putc(int ch)
	383	{
	384	struct mxc_uart base = (struct mxc_uart )CONFIG_DEBUG_UART_BASE;
	385
	386	while (!(readl(&base->ts) & UTS_TXEMPTY))
	387	WATCHDOG_RESET();
	388
	389	writel(ch, &base->txd);
	390	}
	391
	392	DEBUG_UART_FUNCS
	393
	394	#endif