[J-u-boot.git] / drivers / mmc / iproc_sdhci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2019 Broadcom.
 *
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <sdhci.h>
#include <asm/global_data.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

struct sdhci_iproc_host {
	struct sdhci_host host;
	u32 shadow_cmd;
	u32 shadow_blk;
};

#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)

static inline struct sdhci_iproc_host *to_iproc(struct sdhci_host *host)
{
	return (struct sdhci_iproc_host *)host;
}

#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
static u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
{
	u32 val = readl(host->ioaddr + reg);
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
	printf("%s %d: readl [0x%02x] 0x%08x\n",
	       host->name, host->index, reg, val);
#endif
	return val;
}

static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
{
	u32 val = sdhci_iproc_readl(host, (reg & ~3));
	u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
	return word;
}

static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
{
	u32 val = sdhci_iproc_readl(host, (reg & ~3));
	u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
	return byte;
}

static void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
{
	u32 clock = 0;
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
	printf("%s %d: writel [0x%02x] 0x%08x\n",
	       host->name, host->index, reg, val);
#endif
	writel(val, host->ioaddr + reg);

	if (host->mmc)
		clock = host->mmc->clock;
	if (clock <= 400000) {
		/* Round up to micro-second four SD clock delay */
		if (clock)
			udelay((4 * 1000000 + clock - 1) / clock);
		else
			udelay(10);
	}
}

/*
 * The Arasan has a bugette whereby it may lose the content of successive
 * writes to the same register that are within two SD-card clock cycles of
 * each other (a clock domain crossing problem). The data
 * register does not have this problem, which is just as well - otherwise we'd
 * have to nobble the DMA engine too.
 *
 * This wouldn't be a problem with the code except that we can only write the
 * controller with 32-bit writes.  So two different 16-bit registers are
 * written back to back creates the problem.
 *
 * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
 * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
 * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
 * the work around can be further optimized. We can keep shadow values of
 * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
 * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
 * by the TRANSFER+COMMAND in another 32-bit write.
 */
static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_iproc_host *iproc_host = to_iproc(host);
	u32 word_shift = REG_OFFSET_IN_BITS(reg);
	u32 mask = 0xffff << word_shift;
	u32 oldval, newval;

	if (reg == SDHCI_COMMAND) {
		/* Write the block now as we are issuing a command */
		if (iproc_host->shadow_blk != 0) {
			sdhci_iproc_writel(host, iproc_host->shadow_blk,
					   SDHCI_BLOCK_SIZE);
			iproc_host->shadow_blk = 0;
		}
		oldval = iproc_host->shadow_cmd;
	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
		/* Block size and count are stored in shadow reg */
		oldval = iproc_host->shadow_blk;
	} else {
		/* Read reg, all other registers are not shadowed */
		oldval = sdhci_iproc_readl(host, (reg & ~3));
	}
	newval = (oldval & ~mask) | (val << word_shift);

	if (reg == SDHCI_TRANSFER_MODE) {
		/* Save the transfer mode until the command is issued */
		iproc_host->shadow_cmd = newval;
	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
		/* Save the block info until the command is issued */
		iproc_host->shadow_blk = newval;
	} else {
		/* Command or other regular 32-bit write */
		sdhci_iproc_writel(host, newval, reg & ~3);
	}
}

static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
{
	u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
	u32 mask = 0xff << byte_shift;
	u32 newval = (oldval & ~mask) | (val << byte_shift);

	sdhci_iproc_writel(host, newval, reg & ~3);
}
#endif

static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
{
	u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);

	/* Reset UHS mode bits */
	ctrl &= ~SDHCI_CTRL_UHS_MASK;

	if (host->mmc->ddr_mode)
		ctrl |= UHS_DDR50_BUS_SPEED;

	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);

	return 0;
}

static struct sdhci_ops sdhci_platform_ops = {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	.read_l = sdhci_iproc_readl,
	.read_w = sdhci_iproc_readw,
	.read_b = sdhci_iproc_readb,
	.write_l = sdhci_iproc_writel,
	.write_w = sdhci_iproc_writew,
	.write_b = sdhci_iproc_writeb,
#endif
	.set_ios_post = sdhci_iproc_set_ios_post,
};

struct iproc_sdhci_plat {
	struct mmc_config cfg;
	struct mmc mmc;
};

static int iproc_sdhci_probe(struct udevice *dev)
{
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct iproc_sdhci_plat *plat = dev_get_plat(dev);
	struct sdhci_host *host = dev_get_priv(dev);
	struct sdhci_iproc_host *iproc_host;
	int node = dev_of_offset(dev);
	u32 f_min_max[2];
	int ret;

	iproc_host = malloc(sizeof(struct sdhci_iproc_host));
	if (!iproc_host) {
		printf("%s: sdhci host malloc fail!\n", __func__);
		return -ENOMEM;
	}
	iproc_host->shadow_cmd = 0;
	iproc_host->shadow_blk = 0;

	host->name = dev->name;
	host->ioaddr = dev_read_addr_ptr(dev);
	host->voltages = MMC_VDD_165_195 |
			 MMC_VDD_32_33 | MMC_VDD_33_34;
	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B;
	host->host_caps = MMC_MODE_DDR_52MHz;
	host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
	host->ops = &sdhci_platform_ops;
	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
				   "clock-freq-min-max", f_min_max, 2);
	if (ret) {
		printf("sdhci: clock-freq-min-max not found\n");
		free(iproc_host);
		return ret;
	}
	host->max_clk = f_min_max[1];
	host->bus_width	= fdtdec_get_int(gd->fdt_blob,
					 dev_of_offset(dev), "bus-width", 4);

	/* Update host_caps for 8 bit bus width */
	if (host->bus_width == 8)
		host->host_caps |= MMC_MODE_8BIT;

	memcpy(&iproc_host->host, host, sizeof(struct sdhci_host));

	iproc_host->host.mmc = &plat->mmc;
	iproc_host->host.mmc->dev = dev;
	iproc_host->host.mmc->priv = &iproc_host->host;
	upriv->mmc = iproc_host->host.mmc;

	ret = sdhci_setup_cfg(&plat->cfg, &iproc_host->host,
			      f_min_max[1], f_min_max[0]);
	if (ret) {
		free(iproc_host);
		return ret;
	}

	return sdhci_probe(dev);
}

static int iproc_sdhci_bind(struct udevice *dev)
{
	struct iproc_sdhci_plat *plat = dev_get_plat(dev);

	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id iproc_sdhci_ids[] = {
	{ .compatible = "brcm,iproc-sdhci" },
	{ }
};

U_BOOT_DRIVER(iproc_sdhci_drv) = {
	.name = "iproc_sdhci",
	.id = UCLASS_MMC,
	.of_match = iproc_sdhci_ids,
	.ops = &sdhci_ops,
	.bind = iproc_sdhci_bind,
	.probe = iproc_sdhci_probe,
	.priv_auto	= sizeof(struct sdhci_host),
	.plat_auto	= sizeof(struct iproc_sdhci_plat),
};
Commit	Line	Data
36645f45 AP	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2019 Broadcom.
	4	*
	5	*/
	6
	7	#include <common.h>
	8	#include <dm.h>
	9	#include <errno.h>
	10	#include <malloc.h>
	11	#include <sdhci.h>
401d1c4f	12	#include <asm/global_data.h>
c05ed00a	13	#include <linux/delay.h>
36645f45 AP	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
	17	struct sdhci_iproc_host {
	18	struct sdhci_host host;
	19	u32 shadow_cmd;
	20	u32 shadow_blk;
	21	};
	22
	23	#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
	24
	25	static inline struct sdhci_iproc_host to_iproc(struct sdhci_host host)
	26	{
	27	return (struct sdhci_iproc_host *)host;
	28	}
	29
	30	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	31	static u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
	32	{
	33	u32 val = readl(host->ioaddr + reg);
	34	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
	35	printf("%s %d: readl [0x%02x] 0x%08x\n",
	36	host->name, host->index, reg, val);
	37	#endif
	38	return val;
	39	}
	40
	41	static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
	42	{
	43	u32 val = sdhci_iproc_readl(host, (reg & ~3));
	44	u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
	45	return word;
	46	}
	47
	48	static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
	49	{
	50	u32 val = sdhci_iproc_readl(host, (reg & ~3));
	51	u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
	52	return byte;
	53	}
	54
	55	static void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
	56	{
	57	u32 clock = 0;
	58	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
	59	printf("%s %d: writel [0x%02x] 0x%08x\n",
	60	host->name, host->index, reg, val);
	61	#endif
	62	writel(val, host->ioaddr + reg);
	63
	64	if (host->mmc)
	65	clock = host->mmc->clock;
	66	if (clock <= 400000) {
	67	/* Round up to micro-second four SD clock delay */
	68	if (clock)
	69	udelay((4 * 1000000 + clock - 1) / clock);
	70	else
	71	udelay(10);
	72	}
	73	}
	74
	75	/*
	76	* The Arasan has a bugette whereby it may lose the content of successive
	77	* writes to the same register that are within two SD-card clock cycles of
78	* each other (a clock domain crossing problem). The data
79	* register does not have this problem, which is just as well - otherwise we'd
80	* have to nobble the DMA engine too.
81	*
82	* This wouldn't be a problem with the code except that we can only write the
83	* controller with 32-bit writes. So two different 16-bit registers are
84	* written back to back creates the problem.
85	*
86	* In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
87	* are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
88	* The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
89	* the work around can be further optimized. We can keep shadow values of
90	* BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
91	* Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
92	* by the TRANSFER+COMMAND in another 32-bit write.
93	*/
94	static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
95	{
96	struct sdhci_iproc_host *iproc_host = to_iproc(host);
97	u32 word_shift = REG_OFFSET_IN_BITS(reg);
98	u32 mask = 0xffff << word_shift;
99	u32 oldval, newval;
100
101	if (reg == SDHCI_COMMAND) {
102	/* Write the block now as we are issuing a command */
103	if (iproc_host->shadow_blk != 0) {
104	sdhci_iproc_writel(host, iproc_host->shadow_blk,
105	SDHCI_BLOCK_SIZE);
106	iproc_host->shadow_blk = 0;
107	}
108	oldval = iproc_host->shadow_cmd;
109	} else if (reg == SDHCI_BLOCK_SIZE \|\| reg == SDHCI_BLOCK_COUNT) {
110	/* Block size and count are stored in shadow reg */
111	oldval = iproc_host->shadow_blk;
112	} else {
113	/* Read reg, all other registers are not shadowed */
114	oldval = sdhci_iproc_readl(host, (reg & ~3));
115	}
116	newval = (oldval & ~mask) \| (val << word_shift);
117
118	if (reg == SDHCI_TRANSFER_MODE) {
119	/* Save the transfer mode until the command is issued */
120	iproc_host->shadow_cmd = newval;
121	} else if (reg == SDHCI_BLOCK_SIZE \|\| reg == SDHCI_BLOCK_COUNT) {
122	/* Save the block info until the command is issued */
123	iproc_host->shadow_blk = newval;
124	} else {
125	/* Command or other regular 32-bit write */
126	sdhci_iproc_writel(host, newval, reg & ~3);
127	}
128	}
129
130	static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
131	{
132	u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
133	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
134	u32 mask = 0xff << byte_shift;
135	u32 newval = (oldval & ~mask) \| (val << byte_shift);
136
137	sdhci_iproc_writel(host, newval, reg & ~3);
138	}
139	#endif
140
7a65b8b6	141	static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
36645f45 AP	142	{
	143	u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	144
	145	/* Reset UHS mode bits */
	146	ctrl &= ~SDHCI_CTRL_UHS_MASK;
	147
	148	if (host->mmc->ddr_mode)
	149	ctrl \|= UHS_DDR50_BUS_SPEED;
	150
	151	sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7a65b8b6 RK	152
7a65b8b6 RK	153	return 0;
36645f45 AP	154	}
	155
	156	static struct sdhci_ops sdhci_platform_ops = {
	157	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	158	.read_l = sdhci_iproc_readl,
	159	.read_w = sdhci_iproc_readw,
	160	.read_b = sdhci_iproc_readb,
	161	.write_l = sdhci_iproc_writel,
	162	.write_w = sdhci_iproc_writew,
	163	.write_b = sdhci_iproc_writeb,
	164	#endif
	165	.set_ios_post = sdhci_iproc_set_ios_post,
	166	};
	167
	168	struct iproc_sdhci_plat {
	169	struct mmc_config cfg;
	170	struct mmc mmc;
	171	};
	172
	173	static int iproc_sdhci_probe(struct udevice *dev)
	174	{
	175	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
c69cda25	176	struct iproc_sdhci_plat *plat = dev_get_plat(dev);
36645f45 AP	177	struct sdhci_host *host = dev_get_priv(dev);
	178	struct sdhci_iproc_host *iproc_host;
	179	int node = dev_of_offset(dev);
	180	u32 f_min_max[2];
	181	int ret;
	182
d5b8500f	183	iproc_host = malloc(sizeof(struct sdhci_iproc_host));
36645f45 AP	184	if (!iproc_host) {
	185	printf("%s: sdhci host malloc fail!\n", __func__);
	186	return -ENOMEM;
	187	}
	188	iproc_host->shadow_cmd = 0;
	189	iproc_host->shadow_blk = 0;
	190
	191	host->name = dev->name;
8613c8d8	192	host->ioaddr = dev_read_addr_ptr(dev);
36645f45 AP	193	host->voltages = MMC_VDD_165_195 \|
36645f45 AP	194	MMC_VDD_32_33 \| MMC_VDD_33_34;
2bb02b1a	195	host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE \| SDHCI_QUIRK_BROKEN_R1B;
36645f45 AP	196	host->host_caps = MMC_MODE_DDR_52MHz;
	197	host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
	198	host->ops = &sdhci_platform_ops;
	199	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
	200	ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
	201	"clock-freq-min-max", f_min_max, 2);
	202	if (ret) {
	203	printf("sdhci: clock-freq-min-max not found\n");
d5b8500f	204	free(iproc_host);
36645f45 AP	205	return ret;
	206	}
	207	host->max_clk = f_min_max[1];
	208	host->bus_width = fdtdec_get_int(gd->fdt_blob,
	209	dev_of_offset(dev), "bus-width", 4);
	210
	211	/* Update host_caps for 8 bit bus width */
	212	if (host->bus_width == 8)
	213	host->host_caps \|= MMC_MODE_8BIT;
	214
	215	memcpy(&iproc_host->host, host, sizeof(struct sdhci_host));
	216
29617ca3 RK	217	iproc_host->host.mmc = &plat->mmc;
	218	iproc_host->host.mmc->dev = dev;
	219	iproc_host->host.mmc->priv = &iproc_host->host;
	220	upriv->mmc = iproc_host->host.mmc;
	221
36645f45 AP	222	ret = sdhci_setup_cfg(&plat->cfg, &iproc_host->host,
36645f45 AP	223	f_min_max[1], f_min_max[0]);
d5b8500f BKRG	224	if (ret) {
d5b8500f BKRG	225	free(iproc_host);
36645f45	226	return ret;
d5b8500f	227	}
36645f45	228
36645f45 AP	229	return sdhci_probe(dev);
	230	}
	231
	232	static int iproc_sdhci_bind(struct udevice *dev)
	233	{
c69cda25	234	struct iproc_sdhci_plat *plat = dev_get_plat(dev);
36645f45 AP	235
	236	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
	237	}
	238
	239	static const struct udevice_id iproc_sdhci_ids[] = {
	240	{ .compatible = "brcm,iproc-sdhci" },
	241	{ }
	242	};
	243
	244	U_BOOT_DRIVER(iproc_sdhci_drv) = {
	245	.name = "iproc_sdhci",
	246	.id = UCLASS_MMC,
	247	.of_match = iproc_sdhci_ids,
	248	.ops = &sdhci_ops,
	249	.bind = iproc_sdhci_bind,
	250	.probe = iproc_sdhci_probe,
41575d8e	251	.priv_auto = sizeof(struct sdhci_host),
caa4daa2	252	.plat_auto = sizeof(struct iproc_sdhci_plat),
36645f45	253	};