projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| bd39050c MV |
2 | /* |
| 3 | * board/renesas/ulcb/ulcb.c | |
| 4 | * This file is ULCB board support. | |
| 5 | * | |
| 6 | * Copyright (C) 2017 Renesas Electronics Corporation | |
| bd39050c MV |
7 | */ |
| 8 | ||
| 9 | #include <common.h> | |
| 4d72caa5 | 10 | #include <image.h> |
| 691d719d | 11 | #include <init.h> |
| bd39050c MV |
12 | #include <malloc.h> |
| 13 | #include <netdev.h> | |
| 14 | #include <dm.h> | |
| 401d1c4f | 15 | #include <asm/global_data.h> |
| bd39050c MV |
16 | #include <dm/platform_data/serial_sh.h> |
| 17 | #include <asm/processor.h> | |
| 18 | #include <asm/mach-types.h> | |
| 19 | #include <asm/io.h> | |
| cd93d625 | 20 | #include <linux/bitops.h> |
| bd39050c MV |
21 | #include <linux/errno.h> |
| 22 | #include <asm/arch/sys_proto.h> | |
| 23 | #include <asm/gpio.h> | |
| 24 | #include <asm/arch/gpio.h> | |
| 25 | #include <asm/arch/rmobile.h> | |
| 26 | #include <asm/arch/rcar-mstp.h> | |
| 27 | #include <asm/arch/sh_sdhi.h> | |
| 28 | #include <i2c.h> | |
| 29 | #include <mmc.h> | |
| 30 | ||
| 31 | DECLARE_GLOBAL_DATA_PTR; | |
| 32 | ||
| bd39050c | 33 | #define DVFS_MSTP926 BIT(26) |
| ef603233 | 34 | #define HSUSB_MSTP704 BIT(4) /* HSUSB */ |
| bd39050c | 35 | |
| bd39050c MV |
36 | int board_early_init_f(void) |
| 37 | { | |
| bd39050c MV |
38 | #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) |
| 39 | /* DVFS for reset */ | |
| cf97b221 | 40 | mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); |
| bd39050c MV |
41 | #endif |
| 42 | return 0; | |
| 43 | } | |
| 44 | ||
| ef603233 MV |
45 | /* HSUSB block registers */ |
| 46 | #define HSUSB_REG_LPSTS 0xE6590102 | |
| 47 | #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) | |
| 48 | #define HSUSB_REG_UGCTRL2 0xE6590184 | |
| 49 | #define HSUSB_REG_UGCTRL2_USB0SEL 0x30 | |
| 50 | #define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 | |
| 51 | ||
| bd39050c MV |
52 | int board_init(void) |
| 53 | { | |
| 54 | /* adress of boot parameters */ | |
| 55 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; | |
| 56 | ||
| bd39050c MV |
57 | /* USB1 pull-up */ |
| 58 | setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); | |
| 59 | ||
| ef603233 | 60 | /* Configure the HSUSB block */ |
| cf97b221 | 61 | mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704); |
| ef603233 MV |
62 | /* Choice USB0SEL */ |
| 63 | clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, | |
| 64 | HSUSB_REG_UGCTRL2_USB0SEL_EHCI); | |
| 65 | /* low power status */ | |
| 66 | setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); | |
| 67 | ||
| 6f380854 | 68 | return 0; |
| bd39050c | 69 | } |
| bd39050c | 70 | |
| 04513805 MV |
71 | #ifdef CONFIG_MULTI_DTB_FIT |
| 72 | int board_fit_config_name_match(const char *name) | |
| 73 | { | |
| 74 | /* PRR driver is not available yet */ | |
| 75 | u32 cpu_type = rmobile_get_cpu_type(); | |
| 76 | ||
| 77 | if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) && | |
| c7d68120 | 78 | !strcmp(name, "r8a77950-ulcb-u-boot")) |
| 04513805 MV |
79 | return 0; |
| 80 | ||
| 81 | if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) && | |
| c7d68120 | 82 | !strcmp(name, "r8a77960-ulcb-u-boot")) |
| 04513805 MV |
83 | return 0; |
| 84 | ||
| c4ea43d1 | 85 | if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && |
| c7d68120 | 86 | !strcmp(name, "r8a77965-ulcb-u-boot")) |
| c4ea43d1 MV |
87 | return 0; |
| 88 | ||
| 04513805 MV |
89 | return -1; |
| 90 | } | |
| 91 | #endif |