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e3aafef4 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright (C) 2019 | |
4 | * shuyiqi <[email protected]> | |
5 | * liuhao <[email protected]> | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
09140113 | 9 | #include <command.h> |
9a3b4ceb | 10 | #include <cpu_func.h> |
691d719d | 11 | #include <init.h> |
f7ae49fc | 12 | #include <log.h> |
e3aafef4 | 13 | #include <asm/armv8/mmu.h> |
90526e9f | 14 | #include <asm/cache.h> |
401d1c4f | 15 | #include <asm/global_data.h> |
e3aafef4 | 16 | #include <asm/system.h> |
17 | #include <asm/io.h> | |
18 | #include <linux/arm-smccc.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <scsi.h> | |
21 | #include "cpu.h" | |
22 | ||
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
25 | int dram_init(void) | |
26 | { | |
27 | gd->mem_clk = 0; | |
28 | gd->ram_size = PHYS_SDRAM_1_SIZE; | |
29 | return 0; | |
30 | } | |
31 | ||
32 | int dram_init_banksize(void) | |
33 | { | |
34 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
35 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
36 | ||
37 | return 0; | |
38 | } | |
39 | ||
40 | int board_init(void) | |
41 | { | |
42 | return 0; | |
43 | } | |
44 | ||
45 | void reset_cpu(ulong addr) | |
46 | { | |
47 | struct arm_smccc_res res; | |
48 | ||
49 | arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); | |
50 | debug("reset cpu error, %lx\n", res.a0); | |
51 | } | |
52 | ||
53 | static struct mm_region durian_mem_map[] = { | |
54 | { | |
55 | .virt = 0x0UL, | |
56 | .phys = 0x0UL, | |
57 | .size = 0x80000000UL, | |
58 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
59 | PTE_BLOCK_NON_SHARE | | |
60 | PTE_BLOCK_PXN | | |
61 | PTE_BLOCK_UXN | |
62 | }, | |
63 | { | |
64 | .virt = (u64)PHYS_SDRAM_1, | |
65 | .phys = (u64)PHYS_SDRAM_1, | |
66 | .size = (u64)PHYS_SDRAM_1_SIZE, | |
67 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
68 | PTE_BLOCK_NS | | |
69 | PTE_BLOCK_INNER_SHARE | |
70 | }, | |
71 | { | |
72 | 0, | |
73 | } | |
74 | }; | |
75 | ||
76 | struct mm_region *mem_map = durian_mem_map; | |
77 | ||
78 | int print_cpuinfo(void) | |
79 | { | |
80 | printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk); | |
81 | return 0; | |
82 | } | |
83 | ||
84 | int __asm_flush_l3_dcache(void) | |
85 | { | |
86 | int i, pstate; | |
87 | ||
88 | for (i = 0; i < HNF_COUNT; i++) | |
89 | writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); | |
90 | for (i = 0; i < HNF_COUNT; i++) { | |
91 | do { | |
92 | pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); | |
93 | } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); | |
94 | } | |
95 | ||
96 | for (i = 0; i < HNF_COUNT; i++) | |
97 | writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
102 | int last_stage_init(void) | |
103 | { | |
104 | int ret; | |
105 | ||
106 | /* pci e */ | |
107 | pci_init(); | |
108 | /* scsi scan */ | |
109 | ret = scsi_scan(true); | |
110 | if (ret) { | |
111 | printf("scsi scan failed\n"); | |
112 | return CMD_RET_FAILURE; | |
113 | } | |
114 | return ret; | |
115 | } | |
116 |