[J-u-boot.git] / board / freescale / m547xevb / m547xevb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 */

#include <config.h>
#include <common.h>
#include <init.h>
#include <pci.h>
#include <asm/global_data.h>
#include <asm/immap.h>
#include <asm/io.h>
#include <linux/delay.h>

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	puts("Board: ");
	puts("Freescale FireEngine 5475 EVB\n");
	return 0;
};

int dram_init(void)
{
	siu_t *siu = (siu_t *) (MMAP_SIU);
	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
	u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
	u32 temp;
#endif

	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);

	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
	for (i = 0x13; i < 0x20; i++) {
		if (dramsize == (1 << i))
			break;
	}
	i--;
	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);

#ifdef CONFIG_SYS_DRAMSZ1
	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
	for (i = 0x13; i < 0x20; i++) {
		if (temp == (1 << i))
			break;
	}
	i--;
	dramsize += temp;
	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif

	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);

	/* Issue PALL */
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);

	/* Issue LEMR */
	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);

	udelay(500);

	/* Issue PALL */
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);

	/* Perform two refresh cycles */
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);

	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);

	out_be32(&sdram->ctrl,
		(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);

	udelay(100);

	gd->ram_size = dramsize;

	return 0;
};

int testdram(void)
{
	/* TODO: XXX XXX XXX */
	printf("DRAM test not implemented!\n");

	return (0);
}

#if defined(CONFIG_PCI)
/*
 * Initialize PCI devices, report devices found.
 */
static struct pci_controller hose;
extern void pci_mcf547x_8x_init(struct pci_controller *hose);

void pci_init_board(void)
{
	pci_mcf547x_8x_init(&hose);
}
#endif				/* CONFIG_PCI */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
1aee1111 TL	2	/*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, [email protected].
	5	*
a4110eec	6	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
1aee1111	7	* TsiChung Liew ([email protected])
1aee1111 TL	8	*/
	9
	10	#include <config.h>
	11	#include <common.h>
2cf431c2	12	#include <init.h>
1aee1111	13	#include <pci.h>
401d1c4f	14	#include <asm/global_data.h>
1aee1111	15	#include <asm/immap.h>
a4110eec	16	#include <asm/io.h>
c05ed00a	17	#include <linux/delay.h>
1aee1111 TL	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	int checkboard(void)
	22	{
	23	puts("Board: ");
	24	puts("Freescale FireEngine 5475 EVB\n");
	25	return 0;
	26	};
	27
f1683aa7	28	int dram_init(void)
1aee1111	29	{
a4110eec AW	30	siu_t siu = (siu_t ) (MMAP_SIU);
a4110eec AW	31	sdram_t sdram = (sdram_t )(MMAP_SDRAM);
1aee1111	32	u32 dramsize, i;
6d0f6bcf	33	#ifdef CONFIG_SYS_DRAMSZ1
77878f16 TL	34	u32 temp;
77878f16 TL	35	#endif
1aee1111	36
a4110eec	37	out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
1aee1111	38
6d0f6bcf	39	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
1aee1111 TL	40	for (i = 0x13; i < 0x20; i++) {
	41	if (dramsize == (1 << i))
	42	break;
	43	}
	44	i--;
a4110eec	45	out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE \| i);
1aee1111	46
6d0f6bcf JCPV	47	#ifdef CONFIG_SYS_DRAMSZ1
6d0f6bcf JCPV	48	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
1aee1111 TL	49	for (i = 0x13; i < 0x20; i++) {
	50	if (temp == (1 << i))
	51	break;
	52	}
	53	i--;
	54	dramsize += temp;
a4110eec	55	out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) \| i);
1aee1111 TL	56	#endif
1aee1111 TL	57
a4110eec AW	58	out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
a4110eec AW	59	out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
1aee1111 TL	60
1aee1111 TL	61	/* Issue PALL */
a4110eec	62	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 2);
1aee1111 TL	63
1aee1111 TL	64	/* Issue LEMR */
a4110eec AW	65	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
a4110eec AW	66	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE \| 0x04000000);
1aee1111 TL	67
	68	udelay(500);
	69
	70	/* Issue PALL */
a4110eec	71	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 2);
1aee1111 TL	72
1aee1111 TL	73	/* Perform two refresh cycles */
a4110eec AW	74	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 4);
a4110eec AW	75	out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL \| 4);
1aee1111	76
a4110eec	77	out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
1aee1111	78
a4110eec AW	79	out_be32(&sdram->ctrl,
a4110eec AW	80	(CONFIG_SYS_SDRAM_CTRL & ~0x80000000) \| 0x10000F00);
1aee1111 TL	81
	82	udelay(100);
	83
088454cd SG	84	gd->ram_size = dramsize;
	85
	86	return 0;
1aee1111 TL	87	};
	88
	89	int testdram(void)
	90	{
	91	/* TODO: XXX XXX XXX */
	92	printf("DRAM test not implemented!\n");
	93
	94	return (0);
	95	}
	96
	97	#if defined(CONFIG_PCI)
	98	/*
	99	* Initialize PCI devices, report devices found.
	100	*/
	101	static struct pci_controller hose;
	102	extern void pci_mcf547x_8x_init(struct pci_controller *hose);
	103
	104	void pci_init_board(void)
	105	{
	106	pci_mcf547x_8x_init(&hose);
	107	}
	108	#endif /* CONFIG_PCI */